- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1419 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:06:59 +00:00
parent 0a2abde8bf
commit b06e84a2b7
2 changed files with 109 additions and 0 deletions
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+STD_OPT="--workdir=work --ieee=standard --std=93c"
+
+ghdl --clean $STD_OPT
+ghdl --xref-html $STD_OPT test.vhdl >./test.htm
+
+ghdl -a $STD_OPT test.vhdl
+ghdl -e $STD_OPT test
+ghdl -r $STD_OPT test --vcd=test.vcd --assert-level=note
+ 
@@ -0,0 +1,98 @@
+--  Hello world program.
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+
+use std.textio.all; --  Imports the standard textio package.
+
+--  Defines a design entity, without any ports.
+entity test is
+end test;
+
+architecture behaviour of test is
+subtype test_range_t is integer range -15 to 16;
+type test_t is array (test_range_t range <>) of std_ulogic;
+type natural_ptr is access natural;
+
+signal a_s, b_s : integer := 10;
+signal c_s : real := 0.0;
+signal clk_s : std_logic := '0';
+signal res_s : std_logic := '1';
+signal test_s : test_t(2 downto -5);
+
+begin
+resgen:
+  process
+    begin
+      wait for 10 ns;
+      res_s <= not res_s;
+      wait;
+  end process;
+
+clkgen:
+  process
+  variable count : natural_ptr;
+    begin
+      count := new natural'(10);
+      wait for 10 ns;
+        if (a_s > 0) then
+          clk_s <= not clk_s;
+        else
+          report "Ende der Simulation" severity note;
+        end if;
+        end process;
+
+output_proc:
+process (clk_s, res_s)
+  variable l : line;
+  variable b_v : integer := 0;
+  variable c_v : real := 1.0;
+begin
+  if (res_s = '1') then
+    write (l, String'("Hello world!"));
+    writeline (output, l);
+
+    write (l, String'("High="));
+    write (l, test_s'high);
+    writeline (output, l);
+
+    write (l, String'("Low="));
+    write (l, test_s'low);
+    writeline (output, l);
+
+    write (l, String'("Left="));
+    write (l, test_s'left);
+    writeline (output, l);
+
+    write (l, String'("Right="));
+    write (l, test_s'right);
+    writeline (output, l);
+
+    write (l, String'("Var="));
+    write (l, sin(math_pi_over_4));
+    writeline (output, l);
+
+
+  elsif (rising_edge(clk_s)) then
+    write (l, String'("a="));
+    write (l, a_s);
+    writeline (output, l);
+
+    write (l, String'("b="));
+    write (l, b_v);
+    writeline (output, l);
+
+    write (l, String'("c="));
+    write (l, c_v);
+    writeline (output, l);
+
+    a_s <= a_s - 1;
+    b_v := b_v + 1;
+    c_v := 0.1 * c_v;
+  end if;
+  b_s <= b_v after 3 ns;
+  c_s <= c_v after 3 ns;
+end process;
+
+end behaviour;
+