jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
68 lines
1.4 KiB
VHDL
68 lines
1.4 KiB
VHDL
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-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY eval2clk_tb IS
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END eval2clk_tb;
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ARCHITECTURE behavior OF eval2clk_tb IS
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COMPONENT eval2clk
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PORT(
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RES : IN std_logic;
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CLK : IN std_logic;
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SCLK : INOUT std_logic;
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dummy_out : INOUT std_logic
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);
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END COMPONENT;
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SIGNAL RES : std_logic := '1';
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SIGNAL CLK : std_logic := '0';
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SIGNAL SCLK : std_logic;
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SIGNAL dummy_out : std_logic := '0';
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constant ClockPeriod : Time := 16.667 ns;
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BEGIN
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uut: eval2clk PORT MAP(
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RES => RES,
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CLK => CLK,
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SCLK => SCLK,
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dummy_out => dummy_out
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);
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busclock: process
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begin
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CLK <= '1';
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loop
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wait for (ClockPeriod / 2);
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CLK <= not CLK;
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end loop;
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end process;
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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BEGIN
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wait for 20*ClockPeriod;
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RES <= '0';
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;
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