jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
16 lines
406 B
Plaintext
16 lines
406 B
Plaintext
## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for VHDL Post-PAR Simulation
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##
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vlib work
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## Compile Post-PAR Model for Module eval2clk
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vcom -87 -explicit eval2clk_timesim.vhd
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vcom -93 -explicit eval2clk_tb.vhd
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vsim -t 1ps -sdfmax /UUT=eval2clk_timesim.sdf -lib work eval2clk_tb
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do eval2clk_tb.udo
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view wave
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add wave *
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view structure
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view signals
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run 2000ns
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## End
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