jens
ca5f96d996
git-svn-id: http://moon:8086/svn/vhdl/trunk@1449 cc03376c-175c-47c8-b038-4cd826a8556b
54 lines
1.4 KiB
VHDL
54 lines
1.4 KiB
VHDL
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee;
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use ieee.fixed_float_types.all;
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use ieee.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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ENTITY test IS
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Generic (
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nbits : integer := 32;
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nbits_frac : integer := 30;
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nbits_out : integer := 32;
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nbits_frac_out : integer := 31
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);
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END test;
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ARCHITECTURE behavior OF test IS
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--Constants
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constant num_cycles : integer := 5;
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constant num_steps_per_cycle : integer := 100;
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constant PERIOD : time := 10 ns;
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constant one_sfix : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac));
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constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac));
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constant pi1_sfix : sfixed := to_sfixed(3.141592653589793, sproto(nbits, nbits_frac));
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constant pi2_sfix : sfixed := to_sfixed(3.141592653589793/2.0, sproto(nbits, nbits_frac));
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--Inputs
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SIGNAL clk : std_logic := '0';
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SIGNAL rst : std_logic := '1';
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SIGNAL ce : std_logic := '0';
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SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'range) := zero_sfix;
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BEGIN
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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END;
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