jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
61 lines
1.3 KiB
VHDL
61 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:55:59 09/18/2007
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-- Design Name:
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-- Module Name: top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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LIBRARY WORK;
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USE WORK.FIFO_CTRL_PKG.ALL;
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entity top is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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gcnt : out unsigned (13 downto 0);
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bcnt : out unsigned (13 downto 0);
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gnxt : out unsigned (13 downto 0);
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bnxt : out unsigned (13 downto 0)
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);
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end top;
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architecture Behavioral of top is
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begin
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inst_gray_counter : entity work.gray_counter
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generic map (width => 14)
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port map (
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rst => rst,
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clk => clk,
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ce => ce,
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bcnt => bcnt,
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bnxt => bnxt,
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gcnt => gcnt,
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gnxt => gnxt
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);
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end Behavioral;
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