212 lines
5.5 KiB
VHDL
212 lines
5.5 KiB
VHDL
LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.mips_util_pkg.all;
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ENTITY tb_tlb IS
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END tb_tlb;
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ARCHITECTURE behavior OF tb_tlb IS
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constant DATA_WIDTH : integer := 32;
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constant CLK_PERIOD : time := 10 ns;
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signal CLK_O : std_logic := '1';
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signal RST_O : std_logic := '1';
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signal ce : std_logic := '1';
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signal tlb_rdy : std_logic;
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signal tlb_ctrl_in : tlb_ctrl_in_t;
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signal tlb_ctrl_out : tlb_ctrl_out_t;
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signal tlb_query_in : tlb_query_in_t;
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signal tlb_query_out : tlb_query_out_t;
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BEGIN
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inst_uut : entity work.tlb
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GENERIC MAP
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(
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NUM_ENTRIES => TLB_NUM_ENTRIES,
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CACHE_KSEG1 => false,
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USE_TLB => true
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)
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PORT MAP
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(
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-- System signals
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rst => RST_O,
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clk => CLK_O,
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ce => ce,
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rdy => tlb_rdy,
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ctrl_in => tlb_ctrl_in,
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ctrl_out => tlb_ctrl_out,
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query_in => tlb_query_in,
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query_out => tlb_query_out
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK_O <= not CLK_O;
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end process;
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STIMULUS: process
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variable result : unsigned(31 downto 0);
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procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
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begin
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tlb_ctrl_in.entry_wr_idx <= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
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tlb_ctrl_in.entry_hi.vpn <= vpn;
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tlb_ctrl_in.entry_hi.asid <= asid;
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tlb_ctrl_in.entry_lo.pfn <= pfn;
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tlb_ctrl_in.entry_lo.g <= g;
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tlb_ctrl_in.entry_lo.n <= n;
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tlb_ctrl_in.entry_lo.d <= d;
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tlb_ctrl_in.entry_lo.v <= v;
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tlb_ctrl_in.entry_we <= '1';
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wait until rising_edge(CLK_O) and tlb_rdy = '1';
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tlb_ctrl_in.entry_we <= '0';
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end procedure cmd_entry_write;
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procedure cmd_read_single(addr : unsigned) is
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begin
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end procedure cmd_read_single;
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begin
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tlb_ctrl_in.entry_we <= '0';
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tlb_ctrl_in.entry_re <= '0';
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tlb_query_in.vld <= '0';
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tlb_query_in.write <= '0';
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tlb_query_in.vaddr <= X"BFC0_CAFE";
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wait for 6*CLK_PERIOD;
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RST_O <= '0';
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wait for 60*CLK_PERIOD;
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wait until rising_edge(CLK_O) and tlb_rdy = '1';
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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tlb_query_in.vaddr <= X"9FC0_CAFE";
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
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cmd_entry_write(1, "110000", X"0000_1", X"01DE_F", '0', '0', '0', '1');
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cmd_entry_write(2, "110000", X"0000_2", X"02DE_F", '0', '0', '0', '0');
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cmd_entry_write(3, "110000", X"0000_3", X"43DE_F", '0', '0', '0', '1');
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cmd_entry_write(4, "100000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
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cmd_entry_write(5, "110000", X"0000_5", X"65DE_F", '0', '0', '0', '1');
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cmd_entry_write(6, "100000", X"0000_6", X"66DE_F", '1', '0', '0', '1');
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cmd_entry_write(7, "110000", X"0000_7", X"67DE_F", '0', '0', '0', '1');
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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tlb_query_in.vaddr <= X"8000_BABE";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"8000_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"8100_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"8200_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"9000_BABE";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"9000_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"9100_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"9200_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"A000_BABE";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"A000_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"A100_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"A200_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"B000_BABE";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"B000_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"B100_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"B200_1234";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= X"0000_0CAF";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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tlb_query_in.vaddr <= X"0000_0CAF";
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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tlb_query_in.write <= '1';
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tlb_query_in.vaddr <= X"0008_0CAF";
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '1';
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tlb_query_in.write <= '1';
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tlb_query_in.vaddr <= X"0000_0CAF";
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wait until rising_edge(CLK_O);
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tlb_query_in.vld <= '0';
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wait;
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end process;
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END;
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