LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

library work;
use work.mips_types.all;
use work.mips_util_pkg.all;

ENTITY tb_tlb IS
END tb_tlb;

ARCHITECTURE behavior OF tb_tlb IS 

	constant DATA_WIDTH			: integer := 32;
	constant CLK_PERIOD			: time := 10 ns;

	signal CLK_O			: std_logic := '1';
	signal RST_O			: std_logic := '1';
	signal ce				: std_logic := '1';

	signal tlb_rdy				: std_logic;
	
	signal tlb_ctrl_in		: tlb_ctrl_in_t;
	signal tlb_ctrl_out		: tlb_ctrl_out_t;
	signal tlb_query_in		: tlb_query_in_t;
	signal tlb_query_out	: tlb_query_out_t;


BEGIN

inst_uut : entity work.tlb
	GENERIC MAP
	(
		NUM_ENTRIES			=> TLB_NUM_ENTRIES,
		CACHE_KSEG1			=> false,
		USE_TLB				=> true
	)
	PORT MAP
	(
		-- System signals
		rst					=> RST_O,
		clk					=> CLK_O,
		ce					=> ce,

		rdy					=> tlb_rdy,
		
		ctrl_in				=> tlb_ctrl_in,
		ctrl_out			=> tlb_ctrl_out,

		query_in			=> tlb_query_in,
		query_out			=> tlb_query_out

	);

CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		CLK_O <= not CLK_O;
	end process;

STIMULUS: process

	variable result : unsigned(31 downto 0);

	procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
	begin
	
	tlb_ctrl_in.entry_wr_idx	<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
	
	tlb_ctrl_in.entry_hi.vpn	<= vpn;
	tlb_ctrl_in.entry_hi.asid	<= asid;

	tlb_ctrl_in.entry_lo.pfn	<= pfn;	
	tlb_ctrl_in.entry_lo.g		<= g;
	tlb_ctrl_in.entry_lo.n		<= n;	
	tlb_ctrl_in.entry_lo.d		<= d;	
	tlb_ctrl_in.entry_lo.v		<= v;	
	
	tlb_ctrl_in.entry_we		<= '1';
	wait until rising_edge(CLK_O) and tlb_rdy = '1';
	tlb_ctrl_in.entry_we		<= '0';
	
	end procedure cmd_entry_write;

	procedure cmd_read_single(addr : unsigned) is
	begin
	
	end procedure cmd_read_single;

	begin

		tlb_ctrl_in.entry_we	<= '0';
		tlb_ctrl_in.entry_re	<= '0';
		tlb_query_in.vld		<= '0';
		tlb_query_in.write		<= '0';
		tlb_query_in.vaddr		<= X"BFC0_CAFE";
		
		wait for 6*CLK_PERIOD;
		RST_O <= '0';
		wait for 60*CLK_PERIOD;
		wait until rising_edge(CLK_O) and tlb_rdy = '1';

		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';
		tlb_query_in.vaddr <= X"9FC0_CAFE";
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';

		cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
		cmd_entry_write(1, "110000", X"0000_1", X"01DE_F", '0', '0', '0', '1');
		cmd_entry_write(2, "110000", X"0000_2", X"02DE_F", '0', '0', '0', '0');
		cmd_entry_write(3, "110000", X"0000_3", X"43DE_F", '0', '0', '0', '1');
		cmd_entry_write(4, "100000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
		cmd_entry_write(5, "110000", X"0000_5", X"65DE_F", '0', '0', '0', '1');
		cmd_entry_write(6, "100000", X"0000_6", X"66DE_F", '1', '0', '0', '1');
		cmd_entry_write(7, "110000", X"0000_7", X"67DE_F", '0', '0', '0', '1');
		
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';

		tlb_query_in.vaddr <= X"8000_BABE";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"8000_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"8100_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"8200_1234";
		
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"9000_BABE";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"9000_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"9100_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"9200_1234";

		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"A000_BABE";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"A000_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"A100_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"A200_1234";
		
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"B000_BABE";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"B000_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"B100_1234";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"B200_1234";


		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= X"0000_0CAF";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
		wait until rising_edge(CLK_O);
		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";

		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';

		cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');

		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';
		tlb_query_in.vaddr <= X"0000_0CAF";
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';

		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';
		tlb_query_in.write	<= '1';
		tlb_query_in.vaddr <= X"0008_0CAF";
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';

		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '1';
		tlb_query_in.write	<= '1';
		tlb_query_in.vaddr <= X"0000_0CAF";
		wait until rising_edge(CLK_O);
		tlb_query_in.vld	<= '0';

	wait;
	
	end process;
	
END;