jens
55ee041c08
git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
283 lines
7.1 KiB
VHDL
283 lines
7.1 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.fixed_pkg.all;
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use work.nco_pkg.all;
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--use work.PCK_FIO.all;
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ENTITY tb_syn_nco IS
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Generic (
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nbits_wave : integer := 12;
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nbits_phase : integer := 16;
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nbits_lut_depth : integer := 12;
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nbits_dither : integer := 5;
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has_pipe_reg : boolean := true;
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has_out_reg : boolean := true
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);
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END tb_syn_nco;
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ARCHITECTURE behavior OF tb_syn_nco IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT syn_nco
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GENERIC (
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nbits_wave : integer;
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nbits_phase : integer;
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nbits_lut_depth : integer;
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nbits_dither : integer;
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has_pipe_reg : boolean;
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has_out_reg : boolean
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);
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PORT(
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sys_rst : in std_logic;
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sys_clk : in std_logic;
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sys_pacc_clr : in std_logic;
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sys_pacc_inc : in std_logic;
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sys_freq_in : in unsigned(nbits_phase-1 downto 0);
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sys_freq_load : in std_logic;
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sys_phase_in : in unsigned(nbits_phase-1 downto 0);
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sys_phase_load : in std_logic;
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sys_phase_out : out unsigned(nbits_phase-1 downto 0);
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sys_wave_out_i : out signed(nbits_wave-1 downto 0);
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sys_wave_out_q : out signed(nbits_wave-1 downto 0);
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sys_out_valid : out std_logic
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);
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END COMPONENT;
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--Constants
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constant f : REAL := 10.2E6;
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constant df : REAL := 10.0E3;
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constant fa : REAL := 100.0E6;
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constant PERIOD : time := 10 ns;
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constant nbits_wave_frac : integer := nbits_wave;
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SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
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SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
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--Inputs
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SIGNAL clk : std_logic := '0';
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SIGNAL srst : std_logic := '1';
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SIGNAL pacc_clr : std_logic := '0';
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SIGNAL pacc_inc : std_logic := '0';
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SIGNAL phase_load : std_logic := '0';
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SIGNAL freq_load : std_logic := '0';
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SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
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SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
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--Outputs
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SIGNAL wave_out_i : signed(nbits_wave-1 downto 0);
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SIGNAL wave_out_q : signed(nbits_wave-1 downto 0);
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SIGNAL out_valid : std_logic;
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SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
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SIGNAL fileout_enable : std_logic := '0';
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: syn_nco
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GENERIC MAP (
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nbits_wave => nbits_wave,
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nbits_phase => nbits_phase,
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nbits_lut_depth => nbits_lut_depth,
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nbits_dither => nbits_dither,
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has_pipe_reg => has_pipe_reg,
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has_out_reg => has_out_reg
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)
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PORT MAP(
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sys_rst => srst,
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sys_clk => clk,
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sys_pacc_clr => pacc_clr,
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sys_pacc_inc => pacc_inc,
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sys_freq_in => freq_in,
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sys_freq_load => freq_load,
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sys_phase_in => phase_in,
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sys_phase_load => phase_load,
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sys_phase_out => phase_out,
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sys_wave_out_i => wave_out_i,
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sys_wave_out_q => wave_out_q,
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sys_out_valid => out_valid
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);
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 4*PERIOD;
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srst <= '0';
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wait for 2*PERIOD;
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-------------------------------------------
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-- 1
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freq_in <= to_unsigned(0,nbits_phase);
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wait until rising_edge(clk);
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phase_load <= '1';
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wait until rising_edge(clk);
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phase_load <= '0';
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freq_in <= to_unsigned(1411,nbits_phase);
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wait until rising_edge(clk);
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freq_load <= '1';
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wait until rising_edge(clk);
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freq_load <= '0';
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wait for 2*PERIOD;
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pacc_inc <= '1';
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wait for 2*PERIOD;
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wait until rising_edge(clk);
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wait for 40*PERIOD;
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-------------------------------------------
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freq_in <= to_unsigned(643,nbits_phase);
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wait until rising_edge(clk);
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freq_load <= '1';
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wait until rising_edge(clk);
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freq_load <= '0';
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wait for 40*PERIOD;
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-------------------------------------------
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phase_in <= to_unsigned(800,nbits_phase);
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wait until rising_edge(clk);
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phase_load <= '1';
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wait until rising_edge(clk);
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phase_load <= '0';
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wait for 20*PERIOD;
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-------------------------------------------
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phase_in <= to_unsigned(45072,nbits_phase);
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wait until rising_edge(clk);
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phase_load <= '1';
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wait until rising_edge(clk);
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phase_load <= '0';
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wait for 20*PERIOD;
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-------------------------------------------
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phase_in <= to_unsigned(20593,nbits_phase);
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wait until rising_edge(clk);
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phase_load <= '1';
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wait until rising_edge(clk);
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phase_load <= '0';
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-------------------------------------------
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freq_in <= to_unsigned(freq_word,nbits_phase);
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wait until rising_edge(clk);
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freq_load <= '1';
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wait until rising_edge(clk);
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freq_load <= '0';
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wait for 20*PERIOD;
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fileout_enable <= '1';
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wait for 20000*PERIOD;
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fileout_enable <= '0';
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-------------------------------------------
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-- Sweep
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freq_word <= 100;
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for i in 1 to 200 loop
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wait for 20*PERIOD;
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freq_word <= freq_word + dfreq_word;
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freq_in <= to_unsigned(freq_word,nbits_phase);
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wait until rising_edge(clk);
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freq_load <= '1';
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wait until rising_edge(clk);
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freq_load <= '0';
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end loop;
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pacc_inc <= '0';
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wait for 20*PERIOD;
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fileout_enable <= '0';
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wait until rising_edge(clk);
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pacc_clr <= '1';
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wait until rising_edge(clk);
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pacc_clr <= '0';
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wait for 20*PERIOD;
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pacc_inc <= '1';
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wait for 20*PERIOD;
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wait until rising_edge(clk);
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pacc_clr <= '1';
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wait until rising_edge(clk);
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pacc_clr <= '0';
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wait for 20*PERIOD;
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pacc_inc <= '0';
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wait for 20*PERIOD;
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wait until rising_edge(clk);
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pacc_inc <= '1';
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wait until rising_edge(clk);
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pacc_inc <= '0';
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wait for 20*PERIOD;
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wait until rising_edge(clk);
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srst <= '1';
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wait until rising_edge(clk);
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srst <= '0';
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freq_in <= to_unsigned(freq_word,nbits_phase);
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wait until rising_edge(clk);
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freq_load <= '1';
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wait until rising_edge(clk);
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freq_load <= '0';
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wait for 20*PERIOD;
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pacc_inc <= '1';
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wait for 20*PERIOD;
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wait until rising_edge(clk);
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srst <= '1';
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wait until rising_edge(clk);
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srst <= '0';
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wait for 20*PERIOD;
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pacc_inc <= '0';
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wait for 20*PERIOD;
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assert false report "Test finished" severity error;
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wait;
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END PROCESS;
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-- tb_fo : PROCESS(clk, fileout_enable, out_valid)
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-- file RESULT_I: text open write_mode is "i_ud.txt";
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-- file RESULT_Q: text open write_mode is "q_ud.txt";
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-- file RESULT_ID: text open write_mode is "i_d.txt";
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-- file RESULT_QD: text open write_mode is "q_d.txt";
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-- file RESULT_LFSR: text open write_mode is "lfsr.txt";
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--- variable L: line;
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-- BEGIN
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-- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
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-- fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
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-- fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
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-- fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
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-- fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
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-- fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
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-- end if;
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-- END PROCESS;
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END;
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