Files
vhdl/lib/FIFO/ghdl/fifo_async.inc
T
jens fc50f1f9d3 - added read register stage to fifo
git-svn-id: http://moon:8086/svn/vhdl/trunk@1612 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-31 09:37:17 +00:00

17 lines
724 B
PHP

# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -----------------------------------------------------------
PKG_NAME := FIFO_ASYNC
# -----------------------------------------------------------
$(PKG_NAME)_SRCS := $(LIB_PATH)/rams/sim/src/dpram_1w1r2c_ra.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/fifo_ctrl_pkg.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/gray_counter.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/fifo_async_ctrl.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/fifo_async_stage.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd
$(PKG_NAME)_SRCS += $(LIB_PATH)/FIFO/src/fifo_async.vhd
# -----------------------------------------------------------