106 lines
3.5 KiB
VHDL
106 lines
3.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:25:45 10/15/05
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-- Design Name:
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-- Module Name: vga_ctrl_core - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.vga_types.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity clkgen is
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Generic
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(
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sys_freq : integer := 100E6;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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vga_clk : out std_logic;
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dcm_locked : out std_logic
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);
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end clkgen;
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architecture tech of clkgen is
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signal vga_clk0 : std_logic;
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signal dcm_clk0 : std_logic;
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signal dcm_clk_fb : std_logic;
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begin
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-- Compnent instantiation
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DCM_VGA_CLK_inst : DCM_BASE
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
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CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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-- an integer from 0 to 15
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DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
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PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
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STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
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port map (
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CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => open, -- 270 degree DCM CLK output
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CLK2X => open, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLK90 => open, -- 90 degree DCM CLK output
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => dcm_locked, -- DCM LOCK status output
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CLKFB => dcm_clk_fb, -- DCM clock feedback
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CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM)
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RST => rst -- DCM asynchronous reset input
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);
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BUFG_dcm_clk_fb : BUFG
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port map
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(
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O => dcm_clk_fb, -- Clock buffer output
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I => dcm_clk0 -- Clock buffer input
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);
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BUFG_vga_clk : BUFG
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port map
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(
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O => vga_clk, -- Clock buffer output
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I => vga_clk0 -- Clock buffer input
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);
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end tech;
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