jens
55ee041c08
git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
115 lines
3.0 KiB
VHDL
115 lines
3.0 KiB
VHDL
--------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 17:16:42 13.05.2007
|
|
-- Design Name: tb_nco
|
|
-- Module Name: tb_nco.vhd
|
|
-- Project Name: nco
|
|
-- Target Device:
|
|
-- Tool versions:
|
|
-- Description:
|
|
--
|
|
--------------------------------------------------------------------------------
|
|
LIBRARY ieee;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.MATH_REAL.ALL;
|
|
USE ieee.numeric_std.ALL;
|
|
use std.textio.all; -- Imports the standard textio package.
|
|
|
|
library work;
|
|
use work.fixed_pkg.all;
|
|
use work.nco_pkg.all;
|
|
|
|
ENTITY syn_nco IS
|
|
Generic (
|
|
nbits_wave : integer := 12;
|
|
nbits_phase : integer := 16;
|
|
nbits_lut_depth : integer := 8;
|
|
nbits_dither : integer := 5;
|
|
has_pipe_reg : boolean := true;
|
|
has_out_reg : boolean := true
|
|
);
|
|
PORT(
|
|
sys_rst : in std_logic;
|
|
sys_clk : in std_logic;
|
|
sys_pacc_clr : in std_logic;
|
|
sys_pacc_inc : in std_logic;
|
|
sys_freq_in : in unsigned(nbits_phase-1 downto 0);
|
|
sys_freq_load : in std_logic;
|
|
sys_phase_in : in unsigned(nbits_phase-1 downto 0);
|
|
sys_phase_load : in std_logic;
|
|
sys_phase_out : out unsigned(nbits_phase-1 downto 0);
|
|
sys_wave_out_i : out signed(nbits_wave-1 downto 0);
|
|
sys_wave_out_q : out signed(nbits_wave-1 downto 0);
|
|
sys_out_valid : out std_logic
|
|
);
|
|
END syn_nco;
|
|
|
|
ARCHITECTURE behavior OF syn_nco IS
|
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
|
COMPONENT nco
|
|
GENERIC (
|
|
nbits_wave : integer;
|
|
nbits_phase : integer;
|
|
nbits_lut_depth : integer;
|
|
nbits_dither : integer;
|
|
has_pipe_reg : boolean;
|
|
has_out_reg : boolean
|
|
);
|
|
PORT(
|
|
srst : in std_logic;
|
|
clk : in std_logic;
|
|
pacc_clr : in std_logic;
|
|
pacc_inc : in std_logic;
|
|
freq_in : in unsigned(nbits_phase-1 downto 0);
|
|
freq_load : in std_logic;
|
|
phase_in : in unsigned(nbits_phase-1 downto 0);
|
|
phase_load : in std_logic;
|
|
phase_out : out unsigned(nbits_phase-1 downto 0);
|
|
wave_out_i : out sfixed;
|
|
wave_out_q : out sfixed;
|
|
out_valid : out std_logic
|
|
);
|
|
END COMPONENT;
|
|
|
|
--Constants
|
|
constant nbits_wave_frac : integer := nbits_wave;
|
|
|
|
--Outputs
|
|
SIGNAL wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
|
SIGNAL wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
|
|
|
BEGIN
|
|
|
|
-- Instantiate the Unit Under Test (UUT)
|
|
inst_nco: nco
|
|
GENERIC MAP (
|
|
nbits_wave => nbits_wave,
|
|
nbits_phase => nbits_phase,
|
|
nbits_lut_depth => nbits_lut_depth,
|
|
nbits_dither => nbits_dither,
|
|
has_pipe_reg => has_pipe_reg,
|
|
has_out_reg => has_out_reg
|
|
)
|
|
PORT MAP(
|
|
srst => sys_rst,
|
|
clk => sys_clk,
|
|
pacc_clr => sys_pacc_clr,
|
|
pacc_inc => sys_pacc_inc,
|
|
freq_in => sys_freq_in,
|
|
freq_load => sys_freq_load,
|
|
phase_in => sys_phase_in,
|
|
phase_load => sys_phase_load,
|
|
phase_out => sys_phase_out,
|
|
wave_out_i => wave_i,
|
|
wave_out_q => wave_q,
|
|
out_valid => sys_out_valid
|
|
);
|
|
|
|
sys_wave_out_i <= signed(wave_i);
|
|
sys_wave_out_q <= signed(wave_q);
|
|
|
|
END;
|