jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
30 lines
857 B
Plaintext
30 lines
857 B
Plaintext
component_name={name};
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width_a=18;
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depth_a=1024;
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configuration_port_a=read_only;
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port_a_enable_pin=false;
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port_a_handshaking_pins=false;
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port_a_register_inputs=false;
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port_a_init_pin=false;
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port_a_init_value=00000;
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port_a_additional_output_pipe_stages = 0;
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port_a_register_inputs = false;
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port_a_active_clock_edge = Rising_Edge_Triggered;
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width_b=18;
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depth_b=1024;
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configuration_port_b=read_and_write;
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write_mode_port_b=read_after_write;
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port_b_enable_pin=false;
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port_b_handshaking_pins=false;
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port_b_register_inputs=false;
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port_b_init_pin=false;
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port_b_init_value=00000;
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port_b_additional_output_pipe_stages = 0;
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port_b_register_inputs = false;
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port_b_active_clock_edge = Rising_Edge_Triggered;
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port_b_write_enable_polarity = Active_High;
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memory_initialization_radix=16;
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global_init_value=00000;
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memory_initialization_vector=
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