jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
63 lines
1.2 KiB
VHDL
63 lines
1.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity eval2clk is
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Port ( RES : in std_logic;
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CLK : in std_logic;
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SCLK : inout std_logic;
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dummy_out : inout std_logic);
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end eval2clk;
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architecture Behavioral of eval2clk is
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signal count, scount : integer range 0 to 63;
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signal SCLK1 : std_logic;
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begin
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process (RES, SCLK1)
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begin
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if (RES = '1') then
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dummy_out <= '1';
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scount <= 2;
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elsif SCLK1='1' and SCLK1'event then
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if (scount = 0) then
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scount <= 2;
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dummy_out <= not dummy_out;
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else
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scount <= scount - 1;
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end if;
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end if;
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end process;
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process (RES, CLK)
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begin
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if (RES = '1') then
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SCLK1 <= '1';
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COUNT <= 4;
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elsif CLK='1' and CLK'event then
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if (COUNT = 0) then
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COUNT <= 4;
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SCLK1 <= not SCLK1;
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else
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COUNT <= COUNT - 1;
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end if;
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end if;
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end process;
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SCLK <= RES;
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end Behavioral;
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