jens
0afb7b1758
git-svn-id: http://moon:8086/svn/vhdl/trunk@1097 cc03376c-175c-47c8-b038-4cd826a8556b
95 lines
4.0 KiB
VHDL
95 lines
4.0 KiB
VHDL
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus II License Agreement,
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-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-----------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2006 by Altera Corp. All rights reserved. --
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-- --
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-- --
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-- Description: Package containing Attribute Declarations for all --
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-- attributes that control Quartus II Integrated Synthesis. --
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-- Please refer to the Quartus II Help for documentation --
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-- on using these attributes. --
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-- --
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-- --
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-----------------------------------------------------------------------------
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library std;
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use std.standard.all;
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PACKAGE altera_syn_attributes is
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-- Directs Quartus II to implement input, output, and output
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-- enable registers in I/O cells that have fast, direct connections to
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-- an I/O pin, when possible
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ATTRIBUTE useioff : BOOLEAN;
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-- Prevents Quartus II from minimizing or removing a register
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ATTRIBUTE preserve : BOOLEAN;
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-- Prevents Quartus II from removing a dangling register
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ATTRIBUTE noprune : BOOLEAN;
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-- Prevents Quartus II from merging a register with a duplicate
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ATTRIBUTE dont_merge : BOOLEAN;
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-- Prevents Quartus II from replicating a register to improve timing
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ATTRIBUTE dont_replicate : BOOLEAN;
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-- Prevents Quartus II from retiming a register
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ATTRIBUTE dont_retime : BOOLEAN;
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-- Identifies the critical clock enable signal for a register. The
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-- Quartus II software will attempt to connect this signal to the
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-- dedicated clock enable port.
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ATTRIBUTE direct_enable : BOOLEAN;
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-- Prevents Quartus II from minimizing or removing a particular
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-- signal net during combinational logic optimization
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ATTRIBUTE keep : BOOLEAN;
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-- Sets a fan-out limit on a register or net.
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ATTRIBUTE maxfan : NATURAL;
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-- Controls the implementation of a multiplication (*) operations in VHDL
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ATTRIBUTE multstyle : STRING;
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-- Controls the implementation of inferred memories
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ATTRIBUTE ramstyle : STRING;
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-- Controls the implementation of inferred ROMs
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ATTRIBUTE romstyle : STRING;
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-- Specifies a Memory Initialization File (.mif) for an inferred RAM
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ATTRIBUTE ram_init_file : STRING;
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-- Assigns a logic encoding to an enumerated type. Prevents state
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-- machine extraction for all objects with the enumerated type.
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ATTRIBUTE enum_encoding : STRING;
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-- Assigns a state encoding to an enumerated type that models the states
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-- of an extracted state machine.
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ATTRIBUTE syn_encoding : STRING;
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-- Specifies device pin assignments for a VHDL entity port
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ATTRIBUTE chip_pin : STRING;
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-- Applies an arbitrary number of Quartus Settings File (QSF) assignments
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-- to a signal, entity, architecture, instance, or inferred register
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ATTRIBUTE altera_attribute : STRING;
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END altera_syn_attributes;
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