jens
2edaa4d7cb
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
243 lines
6.3 KiB
VHDL
243 lines
6.3 KiB
VHDL
---------------------------------------------------------------------------------
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--COMMAND FORMAT --
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-- --
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-- write(column address(integer), bank(bit), first data(integer), dqm(bit), cke(bit));--
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-- read(column address(integer), bank(bit), dqm(bit), cke(bit)); --
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-- active(row address(integer), bank(bit), data bus (integer), dqm(bit), cke(bit));--
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-- precharge(bank(bit), data bus(integer), dqm(bit), cke(bit)); --
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-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
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-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
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-- load_array('1'); --
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-- load_mode_reg(register(integer), cke(bit)); --
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-- next_cycle(clk); This is used after every command(incl. nop) to clock --
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-- at the correct clock frequency entered in the clock --
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-- period constant below --
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-- unload_array(row_start(integer), row_end(integer), bank(bit)) --
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-- load_mode_reg(op_code(integer)) --
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-- --
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---------------------------------------------------------------------------------
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LIBRARY work;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE std.textio.all;
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USE work.generate_vectors.all;
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ENTITY vector_generate IS
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END vector_generate;
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ARCHITECTURE vector_generate OF vector_generate IS
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SIGNAL stim_done : BOOLEAN := FALSE;
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SIGNAL clk : BIT := '0';
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CONSTANT clk_start : time := 15 ns;
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CONSTANT clk_period : time := 10 ns;
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CONSTANT Z : INTEGER := -100;
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BEGIN
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PROCESS
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BEGIN
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WAIT UNTIL clk = '1' AND clk'EVENT;
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--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
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--******************DO NOT USE -100 FOR A DQ VALUE*************************----
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--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
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--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
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nop(Z, "00", '1', '1'); -- Always begin with one nop when using Micron's testbench
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FOR i IN 1 to 5 LOOP -- You will need 100 us for powerup.
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next_cycle(clk); -- I used 5 here just for an example.
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nop(Z, "00", '1', '1');
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END LOOP;
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next_cycle(clk);
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precharge('0', 1024, Z, "00", '1'); -- Precharge all banks
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FOR i IN 1 to 2 LOOP
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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END LOOP;
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next_cycle(clk);
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auto_refresh; -- First auto refresh
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FOR i IN 1 TO 8 LOOP
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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END LOOP;
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next_cycle(clk);
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auto_refresh; -- Second auto refresh
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FOR i IN 1 TO 8 LOOP
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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END LOOP;
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next_cycle(clk);
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load_mode_reg(51, '1'); -- Load mode register (lat=3, bl=8, mode=seq)
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FOR i IN 1 TO 2 LOOP
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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END LOOP;
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-- Alternate bank write access
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next_cycle(clk);
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active(0, '0', Z, "00", '1'); -- Activate Bank 0, Row 0
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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next_cycle(clk);
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write(1024, '0', 100, "00", '1'); -- Write Bank 0, Col 0, Data 100 (auto precharge)
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next_cycle(clk);
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nop (101, "00", '1', '1');
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next_cycle(clk);
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nop (102, "00", '1', '1');
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next_cycle(clk);
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nop (103, "00", '1', '1');
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next_cycle(clk);
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nop (104, "00", '1', '1');
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next_cycle(clk);
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active(0, '1', 105, "00", '1'); -- Activate Bank 1, Row 0
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next_cycle(clk);
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nop (106, "00", '1', '1');
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next_cycle(clk);
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nop (107, "00", '1', '1');
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next_cycle(clk);
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write(1024, '1', 200, "00", '1'); -- Write Bank 1, Col 0, Data 200 (auto precharge)
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next_cycle(clk);
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nop (201, "00", '1', '1');
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next_cycle(clk);
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nop (202, "00", '1', '1');
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next_cycle(clk);
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nop (203, "00", '1', '1');
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next_cycle(clk);
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nop (204, "00", '1', '1');
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next_cycle(clk);
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active(0, '0', 205, "00", '1'); -- Activate Bank 0, Row 0
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next_cycle(clk);
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nop (206, "00", '1', '1');
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next_cycle(clk);
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nop (207, "00", '1', '1');
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-- Alternate bank read access
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next_cycle(clk);
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read(1024, '0', "00", '1'); -- Read Bank 0, Col 0 (auto precharge)
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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active(0, '1', Z, "00", '1'); -- Activate Bank 1, Row 0
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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read(1024, '1', "00", '1'); -- Read Bank 1, Col 0 (auto precharge)
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop (Z, "00", '1', '1');
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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next_cycle(clk);
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nop(Z, "00", '1', '1');
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stim_done <= TRUE; --always include this line at the end of your stimulus
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-------------------------------------------------------------------------------
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--*************************************************************************----
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END PROCESS;
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clock:
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PROCESS
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VARIABLE done_time : time;
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VARIABLE cycle_var : integer := 0;
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BEGIN
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cycle <= 0;
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clk <= '0';
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WAIT for clk_start;
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WHILE not stim_done loop
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clk <= '1';
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cycle <= cycle_var;
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WAIT for clk_period/2;
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cycle_var := cycle_var + 1;
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clk <= '0';
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WAIT for clk_period/2;
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END LOOP;
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ASSERT (FALSE)
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REPORT "Test Vectors Generated"
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SEVERITY note;
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WAIT;
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END PROCESS;
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END;
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