64 lines
1.0 KiB
VHDL
64 lines
1.0 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE STD.TEXTIO.ALL;
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-- LIBRARY WORK;
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-- USE.YOURLIB.WHATELSE
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ENTITY tb_template IS
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END tb_template;
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ARCHITECTURE behavior OF tb_template IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT your_comp
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GENERIC
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(
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);
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PORT
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(
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);
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END COMPONENT;
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--Constants
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constant PERIOD : time := 10 ns;
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--Inputs
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signal clk : STD_LOGIC := '0';
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--Outputs
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: your_comp
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GENERIC MAP
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(
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)
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PORT MAP
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(
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);
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 4*PERIOD;
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assert false report "Test finished" severity error;
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wait;
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END PROCESS;
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END tb_template;
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