vhdl/projects/eval_timingconstraint/main_top_timesim.vhd

-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command       : -intstyle ise -s 6 -pcf main_top.pcf -ngm main_top.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ncd main_top_timesim.vhd 
-- Input file    : main_top.ncd
-- Output file   : main_top_timesim.vhd
-- Design name   : main_top
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 2v250cs144-6 (PRODUCTION 1.118 2004-03-12, STEPPING 1)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity main_top is
  port (
    clko : out STD_LOGIC; 
    do : out STD_LOGIC; 
    res : in STD_LOGIC := 'X'; 
    clki : in STD_LOGIC := 'X'; 
    di : in STD_LOGIC := 'X' 
  );
end main_top;

architecture Structure of main_top is
  signal di_IBUF : STD_LOGIC; 
  signal do_OBUF : STD_LOGIC; 
  signal clki_IBUFG : STD_LOGIC; 
  signal clko_OBUF : STD_LOGIC; 
  signal res_BUFGP_IBUFG : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal res_BUFGP : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal di_INBUF : STD_LOGIC; 
  signal do_ENABLE : STD_LOGIC; 
  signal do_GTS_OR_T : STD_LOGIC; 
  signal do_O : STD_LOGIC; 
  signal clki_INBUF : STD_LOGIC; 
  signal clko_ENABLE : STD_LOGIC; 
  signal clko_GTS_OR_T : STD_LOGIC; 
  signal clko_O : STD_LOGIC; 
  signal res_INBUF : STD_LOGIC; 
  signal U1_S_INVNOT : STD_LOGIC; 
  signal res_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal nextstate_1_DXMUX : STD_LOGIC; 
  signal nextstate_1_F : STD_LOGIC; 
  signal nextstate_1_DYMUX : STD_LOGIC; 
  signal nextstate_1_G : STD_LOGIC; 
  signal nextstate_1_CLKINV : STD_LOGIC; 
  signal state_1_DXMUX : STD_LOGIC; 
  signal state_1_DYMUX : STD_LOGIC; 
  signal state_1_SRFFMUX : STD_LOGIC; 
  signal state_1_CLKINV : STD_LOGIC; 
  signal do_OBUF_G : STD_LOGIC; 
  signal nextstate_1_FFY_SET : STD_LOGIC; 
  signal nextstate_1_FFX_RST : STD_LOGIC; 
  signal state_1_FFY_SET : STD_LOGIC; 
  signal state_1_FFX_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NlwInverterSignal_nextstate_0_CLK : STD_LOGIC; 
  signal NlwInverterSignal_nextstate_1_CLK : STD_LOGIC; 
  signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Q_n0003 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal nextstate : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  di_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => di,
      O => di_INBUF
    );
  do_OBUF_1 : X_TRI_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => do_O,
      CTL => do_ENABLE,
      O => do
    );
  do_ENABLEINV : X_INV
    port map (
      I => do_GTS_OR_T,
      O => do_ENABLE
    );
  do_GTS_OR_T_2 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => GTS,
      O => do_GTS_OR_T
    );
  clki_IBUFG_3 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => clki,
      O => clki_INBUF
    );
  clko_OBUF_4 : X_TRI_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => clko_O,
      CTL => clko_ENABLE,
      O => clko
    );
  clko_ENABLEINV : X_INV
    port map (
      I => clko_GTS_OR_T,
      O => clko_ENABLE
    );
  clko_GTS_OR_T_5 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => GTS,
      O => clko_GTS_OR_T
    );
  res_BUFGP_IBUFG_6 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => res,
      O => res_INBUF
    );
  U1 : X_BUFGMUX
    port map (
      I0 => clki_IBUFG,
      I1 => GND,
      S => U1_S_INVNOT,
      O => clko_OBUF,
      GSR => GSR
    );
  U1_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => U1_S_INVNOT
    );
  res_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => res_BUFGP_IBUFG,
      I1 => GND,
      S => res_BUFGP_BUFG_S_INVNOT,
      O => res_BUFGP,
      GSR => GSR
    );
  res_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_0,
      O => res_BUFGP_BUFG_S_INVNOT
    );
  nextstate_1_DXMUX_7 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => Q_n0003(1),
      O => nextstate_1_DXMUX
    );
  nextstate_1_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => nextstate_1_F,
      O => Q_n0003(1)
    );
  nextstate_1_DYMUX_8 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => Q_n0003(0),
      O => nextstate_1_DYMUX
    );
  nextstate_1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => nextstate_1_G,
      O => Q_n0003(0)
    );
  nextstate_1_CLKINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => res_BUFGP,
      O => nextstate_1_CLKINV
    );
  state_1_DXMUX_10 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => nextstate(1),
      O => state_1_DXMUX
    );
  state_1_DYMUX_11 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => nextstate(0),
      O => state_1_DYMUX
    );
  state_1_SRFFMUX_12 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => res_BUFGP,
      O => state_1_SRFFMUX
    );
  state_1_CLKINV_13 : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => clko_OBUF,
      O => state_1_CLKINV
    );
  do_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => do_OBUF_G,
      O => do_OBUF
    );
  Q_n0003_0_1 : X_LUT4
    generic map(
      INIT => X"5544"
    )
    port map (
      ADR0 => di_IBUF,
      ADR1 => state(1),
      ADR2 => VCC,
      ADR3 => state(0),
      O => nextstate_1_G
    );
  nextstate_0 : X_LATCHE
    generic map(
      INIT => '1'
    )
    port map (
      I => nextstate_1_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_nextstate_0_CLK,
      SET => nextstate_1_FFY_SET,
      RST => GND,
      O => nextstate(0)
    );
  nextstate_1_FFY_SETOR : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => GSR,
      O => nextstate_1_FFY_SET
    );
  Q_n0003_1_1 : X_LUT4
    generic map(
      INIT => X"AA88"
    )
    port map (
      ADR0 => di_IBUF,
      ADR1 => state(1),
      ADR2 => VCC,
      ADR3 => state(0),
      O => nextstate_1_F
    );
  nextstate_1 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => nextstate_1_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_nextstate_1_CLK,
      SET => GND,
      RST => nextstate_1_FFX_RST,
      O => nextstate(1)
    );
  nextstate_1_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => GSR,
      O => nextstate_1_FFX_RST
    );
  state_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => state_1_DYMUX,
      CE => VCC,
      CLK => state_1_CLKINV,
      SET => state_1_FFY_SET,
      RST => GND,
      O => state(0)
    );
  state_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => state_1_SRFFMUX,
      O => state_1_FFY_SET
    );
  Q_n00061 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => res_BUFGP,
      ADR1 => state(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => do_OBUF_G
    );
  state_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_1_DXMUX,
      CE => VCC,
      CLK => state_1_CLKINV,
      SET => GND,
      RST => state_1_FFX_RST,
      O => state(1)
    );
  state_1_FFX_RSTOR : X_OR2
    port map (
      I0 => state_1_SRFFMUX,
      I1 => GSR,
      O => state_1_FFX_RST
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  PWR_VCC_1_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1_0
    );
  di_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => di_INBUF,
      O => di_IBUF
    );
  do_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => do_OBUF,
      O => do_O
    );
  clki_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => clki_INBUF,
      O => clki_IBUFG
    );
  clko_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => clko_OBUF,
      O => clko_O
    );
  res_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 605 ps
    )
    port map (
      I => res_INBUF,
      O => res_BUFGP_IBUFG
    );
  NlwBlock_main_top_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_main_top_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwInverterBlock_nextstate_0_CLK : X_INV
    port map (
      I => nextstate_1_CLKINV,
      O => NlwInverterSignal_nextstate_0_CLK
    );
  NlwInverterBlock_nextstate_1_CLK : X_INV
    port map (
      I => nextstate_1_CLKINV,
      O => NlwInverterSignal_nextstate_1_CLK
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;