Compare commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
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9e28b9588c |
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vlib simprim
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vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
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vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
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vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
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vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
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vlib unisim
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vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
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vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
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vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
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vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../src/core/mips_instr.vhd"
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vcom -explicit -93 "../src/tb_eval_muldiv.vhd"
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vsim -t 1ps -lib work tb_eval_muldiv
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do {tb_eval_muldiv.wdo}
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view wave
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view structure
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view signals
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run 2400ns
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_eval_muldiv/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
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add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
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configure wave -namecolwidth 149
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configure wave -valuecolwidth 171
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {2520 ns}
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@@ -0,0 +1,22 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../src/core/mips_instr.vhd"
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vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
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vcom -explicit -93 "../src/core/mips_reg.vhd"
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vcom -explicit -93 "../src/core/mips_shifter.vhd"
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vcom -explicit -93 "../src/core/mips_alu.vhd"
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vcom -explicit -93 "../src/core/mips_bcu.vhd"
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vcom -explicit -93 "../src/core/mips_pipeline.vhd"
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vcom -explicit -93 "../src/core/mips_top.vhd"
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vcom -explicit -93 "../src/ram.vhd"
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vcom -explicit -93 "../asm/fibonacci.vhd"
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vcom -explicit -93 "../src/mips_embedded.vhd"
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vcom -explicit -93 "../src/tb_mips_embedded.vhd"
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vsim -t 1ps -lib work tb_mips_embedded
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do {tb_mips_embedded.wdo}
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view wave
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view structure
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view signals
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run 20us
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mips_embedded/rst
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout
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add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re
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add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage
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add wave -noupdate -format Logic /tb_mips_embedded/clk
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add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {624000 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {2520 ns}
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@@ -0,0 +1,31 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../src/core/mips_instr.vhd"
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vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
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vcom -explicit -93 "../src/core/mips_reg.vhd"
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vcom -explicit -93 "../src/core/mips_shifter.vhd"
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vcom -explicit -93 "../src/core/mips_alu.vhd"
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vcom -explicit -93 "../src/core/mips_bcu.vhd"
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vcom -explicit -93 "../src/core/mips_pipeline.vhd"
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vcom -explicit -93 "../src/core/mips_muldiv.vhd"
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vcom -explicit -93 "../src/core/mips_cop.vhd"
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vcom -explicit -93 "../src/core/mips_bui.vhd"
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vcom -explicit -93 "../src/core/mips_top.vhd"
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vcom -explicit -93 "../src/core/dcache.vhd"
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vcom -explicit -93 "../asm/testbench.ROM.vhd"
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vcom -explicit -93 "../src/mips_embedded.vhd"
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vcom -explicit -93 "../src/mips_embedded_syn.vhd"
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vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
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vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
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vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
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vcom -explicit -93 "../../../uart/uart_rx.vhd"
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vcom -explicit -93 "../../../uart/uart_tx.vhd"
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vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
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vsim -t 1ps -lib work tb_mips_embedded_syn
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do {tb_mips_embedded_syn.wdo}
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view wave
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view structure
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view signals
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run 100us
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@@ -0,0 +1,13 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd"
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vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
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vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf" -lib work tb_mips_embedded_syn
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do {tb_mips_embedded_syn.wdo}
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view wave
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#add wave *
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view structure
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view signals
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run 2400ns
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@@ -0,0 +1,112 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx
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add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in
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add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in
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add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led
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add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip
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add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn
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add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port
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add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re
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add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout
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add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s
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add wave -noupdate -divider DMEM
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en
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add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we
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add wave -noupdate -divider IMEM
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run
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add wave -noupdate -divider PC
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc
|
||||||
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add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu
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||||||
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add wave -noupdate -divider Stages
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt
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||||||
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add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem
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||||||
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add wave -noupdate -divider Cop
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
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||||||
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc
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||||||
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause
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||||||
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add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
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||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status
|
||||||
|
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events
|
||||||
|
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe
|
||||||
|
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip
|
||||||
|
add wave -noupdate -divider Stages
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage
|
||||||
|
add wave -noupdate -divider Muldiv
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy
|
||||||
|
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo
|
||||||
|
TreeUpdate [SetDefaultTree]
|
||||||
|
WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0}
|
||||||
|
configure wave -namecolwidth 179
|
||||||
|
configure wave -valuecolwidth 89
|
||||||
|
configure wave -justifyvalue left
|
||||||
|
configure wave -signalnamewidth 1
|
||||||
|
configure wave -snapdistance 10
|
||||||
|
configure wave -datasetprefix 0
|
||||||
|
configure wave -rowmargin 4
|
||||||
|
configure wave -childrowmargin 2
|
||||||
|
configure wave -gridoffset 0
|
||||||
|
configure wave -gridperiod 100
|
||||||
|
configure wave -griddelta 40
|
||||||
|
configure wave -timeline 1
|
||||||
|
update
|
||||||
|
WaveRestoreZoom {1351336 ps} {1583596 ps}
|
||||||
@@ -12,4 +12,4 @@ view wave
|
|||||||
|
|
||||||
view structure
|
view structure
|
||||||
view signals
|
view signals
|
||||||
run 8ms
|
run 5000us
|
||||||
|
|||||||
@@ -0,0 +1,19 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
## Compile Post-Translate Model
|
||||||
|
vcom -explicit -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd"
|
||||||
|
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
|
||||||
|
|
||||||
|
vsim -t 1ps -lib work tb_mips_muldiv
|
||||||
|
#do {tb_mips_muldiv.udo}
|
||||||
|
view wave
|
||||||
|
add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 1000ns
|
||||||
|
## End
|
||||||
@@ -0,0 +1,19 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
## Compile Post-Translate Model
|
||||||
|
vcom -explicit -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd"
|
||||||
|
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
|
||||||
|
|
||||||
|
vsim -t 1ps -lib work tb_mips_muldiv
|
||||||
|
do {tb_mips_muldiv.wdo}
|
||||||
|
view wave
|
||||||
|
#add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 1000ns
|
||||||
|
## End
|
||||||
@@ -6,15 +6,16 @@ add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
|
|||||||
add wave -noupdate -format Logic /tb_mips_muldiv/start
|
add wave -noupdate -format Logic /tb_mips_muldiv/start
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/busy
|
add wave -noupdate -format Logic /tb_mips_muldiv/busy
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
|
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
|
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
|
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/check
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
|
add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
|
add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
|
||||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
|
add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
|
||||||
@@ -61,7 +62,7 @@ add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
|
|||||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
|
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
|
||||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
|
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
|
||||||
configure wave -namecolwidth 149
|
configure wave -namecolwidth 149
|
||||||
configure wave -valuecolwidth 171
|
configure wave -valuecolwidth 171
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@@ -75,4 +76,4 @@ configure wave -gridperiod 100
|
|||||||
configure wave -griddelta 40
|
configure wave -griddelta 40
|
||||||
configure wave -timeline 1
|
configure wave -timeline 1
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ps} {8400 us}
|
WaveRestoreZoom {0 ps} {5250 us}
|
||||||
|
|||||||
@@ -1,57 +1,22 @@
|
|||||||
## NOTE: Do not edit this file.
|
## NOTE: Do not edit this file.
|
||||||
##
|
##
|
||||||
vlib work
|
vlib work
|
||||||
|
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||||
# RAMS
|
|
||||||
vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
|
|
||||||
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
|
|
||||||
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
|
|
||||||
|
|
||||||
# FIFOS
|
|
||||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
|
||||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
|
||||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
|
|
||||||
|
|
||||||
# UART
|
|
||||||
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
|
|
||||||
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
|
|
||||||
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
|
|
||||||
vcom -explicit -93 "../../../uart/uart_rx.vhd"
|
|
||||||
vcom -explicit -93 "../../../uart/uart_tx.vhd"
|
|
||||||
vcom -explicit -93 "../../../uart/uart_wb.vhd"
|
|
||||||
|
|
||||||
# GPIO
|
|
||||||
vcom -explicit -93 "../../../misc/gpio_wb.vhd"
|
|
||||||
|
|
||||||
# Async port
|
|
||||||
vcom -explicit -93 "../../../misc/async_types.vhd"
|
|
||||||
vcom -explicit -93 "../../../misc/async_port_wb.vhd"
|
|
||||||
vcom -explicit -93 "../src/async_defs.vhd"
|
|
||||||
|
|
||||||
# ROM
|
|
||||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
|
||||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
|
|
||||||
|
|
||||||
# MIPS
|
|
||||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
|
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_reg.vhd"
|
vcom -explicit -93 "../src/core/mips_reg.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_shifter.vhd"
|
vcom -explicit -93 "../src/core/mips_shifter.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_alu.vhd"
|
vcom -explicit -93 "../src/core/mips_alu.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
|
|
||||||
vcom -explicit -93 "../src/core/mips_cop.vhd"
|
|
||||||
vcom -explicit -93 "../src/core/mips_icache.vhd"
|
|
||||||
vcom -explicit -93 "../src/core/mips_dcache.vhd"
|
|
||||||
vcom -explicit -93 "../src/core/mips_biu.vhd"
|
|
||||||
vcom -explicit -93 "../src/core/mips_bcu.vhd"
|
vcom -explicit -93 "../src/core/mips_bcu.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
|
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
|
||||||
vcom -explicit -93 "../src/core/mips_top.vhd"
|
vcom -explicit -93 "../src/core/mips_top.vhd"
|
||||||
|
vcom -explicit -93 "../asm/fibonacci.vhd"
|
||||||
|
vcom -explicit -93 "../src/ram.vhd"
|
||||||
vcom -explicit -93 "../src/tb_mips_top.vhd"
|
vcom -explicit -93 "../src/tb_mips_top.vhd"
|
||||||
vsim -t 1ps -lib work tb_mips_top
|
vsim -t 1ps -lib work tb_mips_top
|
||||||
do {tb_mips_top.wdo}
|
do {tb_mips_top.wdo}
|
||||||
view wave
|
view wave
|
||||||
view structure
|
view structure
|
||||||
view signals
|
view signals
|
||||||
run 1600us
|
run 40000ns
|
||||||
|
|||||||
@@ -0,0 +1,18 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
## Compile Post-Map Model
|
||||||
|
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_map.vhd"
|
||||||
|
vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf" -lib work mips_top
|
||||||
|
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/irom_hello.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_top.vhd"
|
||||||
|
vsim -t 1ps -lib work tb_mips_top
|
||||||
|
do {tb_mips_top.mwdo}
|
||||||
|
view wave
|
||||||
|
#add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 2400ns
|
||||||
@@ -0,0 +1,31 @@
|
|||||||
|
onerror {resume}
|
||||||
|
quietly WaveActivateNextPane {} 0
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/rst
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/ce
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/dmem_we
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/dmem_re
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram
|
||||||
|
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2
|
||||||
|
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result
|
||||||
|
TreeUpdate [SetDefaultTree]
|
||||||
|
WaveRestoreCursors {{Cursor 1} {77481 ps} 0}
|
||||||
|
configure wave -namecolwidth 150
|
||||||
|
configure wave -valuecolwidth 100
|
||||||
|
configure wave -justifyvalue left
|
||||||
|
configure wave -signalnamewidth 1
|
||||||
|
configure wave -snapdistance 10
|
||||||
|
configure wave -datasetprefix 0
|
||||||
|
configure wave -rowmargin 4
|
||||||
|
configure wave -childrowmargin 2
|
||||||
|
configure wave -gridoffset 0
|
||||||
|
configure wave -gridperiod 100
|
||||||
|
configure wave -griddelta 40
|
||||||
|
configure wave -timeline 1
|
||||||
|
update
|
||||||
|
WaveRestoreZoom {0 ps} {729730 ps}
|
||||||
@@ -0,0 +1,16 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
vcom -explicit -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd"
|
||||||
|
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/irom_hello.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_top.vhd"
|
||||||
|
vsim -t 1ps -lib work tb_mips_top
|
||||||
|
#do {tb_mips_top.wdo}
|
||||||
|
view wave
|
||||||
|
add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 2400ns
|
||||||
@@ -1,56 +1,40 @@
|
|||||||
onerror {resume}
|
onerror {resume}
|
||||||
quietly WaveActivateNextPane {} 0
|
quietly WaveActivateNextPane {} 0
|
||||||
add wave -noupdate -divider {TOP interface}
|
add wave -noupdate -format Logic /tb_mips_top/rst
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal /tb_mips_top/debug
|
add wave -noupdate -format Logic /tb_mips_top/cpu_halt
|
||||||
add wave -noupdate -format Logic /tb_mips_top/stb_o
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
|
||||||
add wave -noupdate -format Logic /tb_mips_top/ack_i
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
|
||||||
add wave -noupdate -format Logic /tb_mips_top/srdy_i
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
|
add wave -noupdate -format Logic /tb_mips_top/dmem_re
|
||||||
add wave -noupdate -format Logic /tb_mips_top/we_o
|
add wave -noupdate -format Logic /tb_mips_top/dmem_we
|
||||||
add wave -noupdate -format Literal /tb_mips_top/sel_o
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
|
||||||
add wave -noupdate -format Logic /tb_mips_top/cyc_o
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/mrdy_o
|
|
||||||
add wave -noupdate -format Literal /tb_mips_top/int
|
|
||||||
add wave -noupdate -divider {External components}
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/rx
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/tx
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
|
||||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
|
|
||||||
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
|
|
||||||
add wave -noupdate -divider ALU
|
add wave -noupdate -divider ALU
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
|
||||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
|
add wave -noupdate -divider PC
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
|
||||||
add wave -noupdate -divider PC
|
add wave -noupdate -divider PC
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
|
||||||
add wave -noupdate -divider PC
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||||
configure wave -namecolwidth 188
|
configure wave -namecolwidth 188
|
||||||
configure wave -valuecolwidth 100
|
configure wave -valuecolwidth 100
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@@ -64,4 +48,4 @@ configure wave -gridperiod 100
|
|||||||
configure wave -griddelta 40
|
configure wave -griddelta 40
|
||||||
configure wave -timeline 1
|
configure wave -timeline 1
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ps} {1260 us}
|
WaveRestoreZoom {0 ps} {42 us}
|
||||||
|
|||||||
@@ -0,0 +1,17 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
## Compile Post-Map Model
|
||||||
|
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd"
|
||||||
|
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf" -lib work mips_top_syn
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/irom_hello.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
|
||||||
|
vsim -t 1ps -lib work tb_mips_top_syn
|
||||||
|
do {tb_mips_top_syn.wdo}
|
||||||
|
view wave
|
||||||
|
#add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 2400ns
|
||||||
@@ -0,0 +1,17 @@
|
|||||||
|
## NOTE: Do not edit this file.
|
||||||
|
##
|
||||||
|
vlib work
|
||||||
|
## Compile Post-Map Model
|
||||||
|
vcom -explicit -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd"
|
||||||
|
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf" -lib work mips_top_syn
|
||||||
|
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||||
|
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||||
|
vcom -explicit -93 "../src/irom_hello.vhd"
|
||||||
|
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
|
||||||
|
vsim -t 1ps -lib work tb_mips_top_syn
|
||||||
|
do {tb_mips_top_syn.wdo}
|
||||||
|
view wave
|
||||||
|
#add wave *
|
||||||
|
view structure
|
||||||
|
view signals
|
||||||
|
run 2400ns
|
||||||
@@ -0,0 +1,31 @@
|
|||||||
|
onerror {resume}
|
||||||
|
quietly WaveActivateNextPane {} 0
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top_syn/rst
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top_syn/clk
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top_syn/ce
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we
|
||||||
|
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram
|
||||||
|
TreeUpdate [SetDefaultTree]
|
||||||
|
WaveRestoreCursors {{Cursor 1} {118199 ps} 0}
|
||||||
|
configure wave -namecolwidth 188
|
||||||
|
configure wave -valuecolwidth 100
|
||||||
|
configure wave -justifyvalue left
|
||||||
|
configure wave -signalnamewidth 1
|
||||||
|
configure wave -snapdistance 10
|
||||||
|
configure wave -datasetprefix 0
|
||||||
|
configure wave -rowmargin 4
|
||||||
|
configure wave -childrowmargin 2
|
||||||
|
configure wave -gridoffset 0
|
||||||
|
configure wave -gridperiod 100
|
||||||
|
configure wave -griddelta 40
|
||||||
|
configure wave -timeline 1
|
||||||
|
update
|
||||||
|
WaveRestoreZoom {0 ps} {2520 ns}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -92,13 +92,14 @@ END COMPONENT;
|
|||||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||||
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
|
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
|
||||||
constant tag_parity_width : natural := 3;
|
constant tag_parity_width : natural := 3;
|
||||||
constant tram_data_width : natural := 1 + tag_parity_width + tag_width;
|
constant tram_data_width : natural := 2 + tag_parity_width + tag_width;
|
||||||
constant tram_addr_width : natural := cache_index_width;
|
constant tram_addr_width : natural := cache_index_width;
|
||||||
|
|
||||||
subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
|
subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
|
||||||
|
|
||||||
type dcache_entry_t is record
|
type dcache_entry_t is record
|
||||||
valid : std_logic;
|
valid : std_logic;
|
||||||
|
dirty : std_logic;
|
||||||
tv_p : unsigned(tag_parity_width-1 downto 0);
|
tv_p : unsigned(tag_parity_width-1 downto 0);
|
||||||
tag : unsigned(tag_width-1 downto 0);
|
tag : unsigned(tag_width-1 downto 0);
|
||||||
end record;
|
end record;
|
||||||
@@ -111,8 +112,9 @@ END COMPONENT;
|
|||||||
variable result : dcache_entry_t;
|
variable result : dcache_entry_t;
|
||||||
begin
|
begin
|
||||||
result.valid := x(0);
|
result.valid := x(0);
|
||||||
result.tv_p := x(3 downto 1);
|
result.dirty := x(1);
|
||||||
result.tag := x(tag_width+3 downto 4);
|
result.tv_p := x(4 downto 2);
|
||||||
|
result.tag := x(tag_width+4 downto 5);
|
||||||
|
|
||||||
return result;
|
return result;
|
||||||
end to_dcache_entry;
|
end to_dcache_entry;
|
||||||
@@ -121,8 +123,9 @@ END COMPONENT;
|
|||||||
variable result : tram_data_t;
|
variable result : tram_data_t;
|
||||||
begin
|
begin
|
||||||
result(0) := x.valid;
|
result(0) := x.valid;
|
||||||
result(3 downto 1) := x.tv_p;
|
result(1) := x.dirty;
|
||||||
result(tag_width+3 downto 4) := x.tag;
|
result(4 downto 2) := x.tv_p;
|
||||||
|
result(tag_width+4 downto 5) := x.tag;
|
||||||
|
|
||||||
return result;
|
return result;
|
||||||
end to_tram_data;
|
end to_tram_data;
|
||||||
@@ -318,6 +321,7 @@ cache_state:
|
|||||||
cache_entry_in.tv_p <= (others => '0');
|
cache_entry_in.tv_p <= (others => '0');
|
||||||
cache_entry_in.tag <= tag_index_reg;
|
cache_entry_in.tag <= tag_index_reg;
|
||||||
cache_entry_in.valid <= '0';
|
cache_entry_in.valid <= '0';
|
||||||
|
cache_entry_in.dirty <= '0';
|
||||||
sn <= s;
|
sn <= s;
|
||||||
|
|
||||||
case s is
|
case s is
|
||||||
@@ -374,6 +378,7 @@ cache_state:
|
|||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
when upd_cache =>
|
when upd_cache =>
|
||||||
|
CYC_O <= '1';
|
||||||
tram_addr_wr <= cache_index_reg;
|
tram_addr_wr <= cache_index_reg;
|
||||||
tram_we <= '1';
|
tram_we <= '1';
|
||||||
cache_entry_in.valid <= '1';
|
cache_entry_in.valid <= '1';
|
||||||
|
|||||||
@@ -296,12 +296,14 @@ cache_state:
|
|||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
when upd_cache =>
|
when upd_cache =>
|
||||||
|
CYC_O <= '1';
|
||||||
tag_ram_addr_wr <= cache_index_reg;
|
tag_ram_addr_wr <= cache_index_reg;
|
||||||
tag_ram_we <= '1';
|
tag_ram_we <= '1';
|
||||||
cache_entry_in.valid <= '1';
|
cache_entry_in.valid <= '1';
|
||||||
sn <= rd_cache;
|
sn <= rd_cache;
|
||||||
|
|
||||||
when rd_cache =>
|
when rd_cache =>
|
||||||
|
-- CYC_O <= '1';
|
||||||
tag_ram_re <= '1';
|
tag_ram_re <= '1';
|
||||||
data_ram_re <= '1';
|
data_ram_re <= '1';
|
||||||
was_miss <= '1';
|
was_miss <= '1';
|
||||||
|
|||||||
@@ -28,12 +28,7 @@ use IEEE.numeric_std.ALL;
|
|||||||
library work;
|
library work;
|
||||||
use work.mips_types.all;
|
use work.mips_types.all;
|
||||||
|
|
||||||
entity biu is
|
entity bui is
|
||||||
Generic
|
|
||||||
(
|
|
||||||
icache_size : natural := 2048; -- words
|
|
||||||
dcache_size : natural := 2048 -- words
|
|
||||||
);
|
|
||||||
Port
|
Port
|
||||||
(
|
(
|
||||||
RST_I : in STD_LOGIC;
|
RST_I : in STD_LOGIC;
|
||||||
@@ -62,15 +57,15 @@ entity biu is
|
|||||||
cpu_dmem_din : out word_t;
|
cpu_dmem_din : out word_t;
|
||||||
cpu_dmem_addr : in word_t
|
cpu_dmem_addr : in word_t
|
||||||
);
|
);
|
||||||
end biu;
|
end bui;
|
||||||
|
|
||||||
architecture behavior of biu is
|
architecture behavior of bui is
|
||||||
|
|
||||||
COMPONENT icache
|
COMPONENT icache
|
||||||
GENERIC
|
GENERIC
|
||||||
(
|
(
|
||||||
cache_size : natural; -- words
|
cache_size : natural := 2048; -- words
|
||||||
line_size : natural -- words
|
line_size : natural := 8 -- words
|
||||||
);
|
);
|
||||||
PORT
|
PORT
|
||||||
(
|
(
|
||||||
@@ -93,8 +88,8 @@ architecture behavior of biu is
|
|||||||
COMPONENT dcache
|
COMPONENT dcache
|
||||||
GENERIC
|
GENERIC
|
||||||
(
|
(
|
||||||
cache_size : natural; -- words
|
cache_size : natural := 2048; -- words
|
||||||
line_size : natural -- words
|
line_size : natural := 8 -- words
|
||||||
);
|
);
|
||||||
PORT
|
PORT
|
||||||
(
|
(
|
||||||
@@ -187,28 +182,11 @@ architecture behavior of biu is
|
|||||||
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
|
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
|
||||||
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
|
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
|
||||||
|
|
||||||
signal read_cycle : std_logic;
|
|
||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
|
|
||||||
MRDY_O <= '1';
|
MRDY_O <= '1';
|
||||||
|
CYC_O <= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
|
||||||
read_cyc_register:
|
|
||||||
process(CLK_I)
|
|
||||||
begin
|
|
||||||
if rising_edge(CLK_I) then
|
|
||||||
if RST_I = '1' then
|
|
||||||
read_cycle <= '0';
|
|
||||||
else
|
|
||||||
read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd)
|
|
||||||
or (dcache_mem_gnt and CYC_O_dcache)
|
|
||||||
or (icache_mem_gnt and CYC_O_icache);
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
CYC_O <= not bout_fifo_empty or read_cycle;
|
|
||||||
STB_O <= not bout_fifo_empty;
|
STB_O <= not bout_fifo_empty;
|
||||||
ADDR_O <= bout_fifo_addr_out;
|
ADDR_O <= bout_fifo_addr_out;
|
||||||
DAT_O <= bout_fifo_data_out;
|
DAT_O <= bout_fifo_data_out;
|
||||||
@@ -222,7 +200,7 @@ read_cyc_register:
|
|||||||
inst_icache : icache
|
inst_icache : icache
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
cache_size => icache_size, -- words
|
cache_size => 2048, -- words
|
||||||
line_size => 8
|
line_size => 8
|
||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
@@ -247,7 +225,7 @@ inst_icache : icache
|
|||||||
inst_dcache : dcache
|
inst_dcache : dcache
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
cache_size => dcache_size, -- words
|
cache_size => 2048, -- words
|
||||||
line_size => 8
|
line_size => 8
|
||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
@@ -277,7 +255,7 @@ inst_dcache : dcache
|
|||||||
dcache_en <= cpu_dmem_en and not busy;
|
dcache_en <= cpu_dmem_en and not busy;
|
||||||
|
|
||||||
-- Instantiate synchronous FIFO
|
-- Instantiate synchronous FIFO
|
||||||
inst_bout_fifo: entity work.fifo_sync_dist
|
inst_bout_fifo: entity work.fifo_sync
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
addr_width => 4,
|
addr_width => 4,
|
||||||
@@ -299,7 +277,11 @@ inst_bout_fifo: entity work.fifo_sync_dist
|
|||||||
bout_rdy <= not bout_fifo_full;
|
bout_rdy <= not bout_fifo_full;
|
||||||
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
|
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
|
||||||
|
|
||||||
bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
|
bout_fifo_we <= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
||||||
|
STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
|
||||||
|
STB_O_dcache when dcache_mem_gnt = '1' else
|
||||||
|
STB_O_icache when icache_mem_gnt = '1' else '0';
|
||||||
|
|
||||||
|
|
||||||
bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
|
bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
|
||||||
|
|
||||||
@@ -312,11 +294,13 @@ inst_bout_fifo: entity work.fifo_sync_dist
|
|||||||
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
||||||
|
|
||||||
-- Instantiate synchronous FIFO
|
-- Instantiate synchronous FIFO
|
||||||
inst_write_fifo: entity work.fifo_sync_dist
|
inst_write_fifo: entity work.fifo_sync
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
addr_width => 4,
|
addr_width => 4,
|
||||||
data_width => 68
|
data_width => 68,
|
||||||
|
almost_full_thresh => 12,
|
||||||
|
almost_empty_thresh => 4
|
||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
|
|||||||
@@ -338,10 +338,10 @@ cop_register_read:
|
|||||||
reg := test_reg;
|
reg := test_reg;
|
||||||
|
|
||||||
when others =>
|
when others =>
|
||||||
reg := (others => '-');
|
reg := X"DEADBEEF";
|
||||||
|
|
||||||
end case;
|
end case;
|
||||||
dout <= reg after 1 ns;
|
dout <= reg;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
|||||||
@@ -615,7 +615,7 @@ proc_stage_DMEM_ADDR:
|
|||||||
process(clk_1)
|
process(clk_1)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk_1) then
|
if rising_edge(clk_1) then
|
||||||
if sdu.EX_stall = '0' then
|
if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then
|
||||||
EX_stage.va <= vaddr;
|
EX_stage.va <= vaddr;
|
||||||
if cop_stat.RE = '1' then
|
if cop_stat.RE = '1' then
|
||||||
EX_stage.pa_off <= not vaddr(1 downto 0);
|
EX_stage.pa_off <= not vaddr(1 downto 0);
|
||||||
@@ -677,7 +677,28 @@ proc_stage_bcu_op:
|
|||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
EX_stage.alu_op1 <= EX_stage.reg_a;
|
alu_op1_mux:
|
||||||
|
process(EX_stage)
|
||||||
|
variable data : word_t;
|
||||||
|
begin
|
||||||
|
|
||||||
|
data := EX_stage.reg_a;
|
||||||
|
|
||||||
|
-- case EX_stage.ctrl.alu.op1_src is
|
||||||
|
--
|
||||||
|
-- when alu_src_reg =>
|
||||||
|
-- data := EX_stage.reg_a;
|
||||||
|
--
|
||||||
|
-- when alu_src_muldiv =>
|
||||||
|
-- data := mul_result;
|
||||||
|
--
|
||||||
|
-- when others => null;
|
||||||
|
--
|
||||||
|
-- end case;
|
||||||
|
|
||||||
|
EX_stage.alu_op1 <= data;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
alu_op2_mux:
|
alu_op2_mux:
|
||||||
process(clk_1)
|
process(clk_1)
|
||||||
@@ -789,6 +810,11 @@ proc_stage_MEM_n:
|
|||||||
MEM_stage.ctrl <= ctrl_lines_default;
|
MEM_stage.ctrl <= ctrl_lines_default;
|
||||||
MEM_stage.pa_off <= (others => '0');
|
MEM_stage.pa_off <= (others => '0');
|
||||||
MEM_stage.events_in <= events_clr;
|
MEM_stage.events_in <= events_clr;
|
||||||
|
-- MEM_stage.epc <= (others => '0');
|
||||||
|
-- MEM_stage.pcn <= (others => '0');
|
||||||
|
-- MEM_stage.va <= (others => '0');
|
||||||
|
-- MEM_stage.reg_wptr <= (others => '0');
|
||||||
|
-- MEM_stage.ex_result <= (others => '0');
|
||||||
elsif sdu.MEM_stall = '0' then
|
elsif sdu.MEM_stall = '0' then
|
||||||
MEM_stage.events_in <= EX_stage.events;
|
MEM_stage.events_in <= EX_stage.events;
|
||||||
MEM_stage.op <= EX_stage.op;
|
MEM_stage.op <= EX_stage.op;
|
||||||
@@ -868,6 +894,9 @@ proc_stage_WB_p:
|
|||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
WB_stage.op <= NOP;
|
WB_stage.op <= NOP;
|
||||||
WB_stage.wreg_we <= '0';
|
WB_stage.wreg_we <= '0';
|
||||||
|
-- WB_stage.epc <= (others => '0');
|
||||||
|
-- WB_stage.reg_wptr <= (others => '0');
|
||||||
|
-- WB_stage.data <= (others => '0');
|
||||||
elsif sdu.WB_stall = '0' then
|
elsif sdu.WB_stall = '0' then
|
||||||
WB_stage.op <= MEM_stage.op;
|
WB_stage.op <= MEM_stage.op;
|
||||||
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
||||||
|
|||||||
@@ -88,12 +88,7 @@ architecture rtl of mips_top is
|
|||||||
signal dmem_be : unsigned(3 downto 0);
|
signal dmem_be : unsigned(3 downto 0);
|
||||||
|
|
||||||
|
|
||||||
COMPONENT biu
|
COMPONENT bui
|
||||||
GENERIC
|
|
||||||
(
|
|
||||||
icache_size : natural;
|
|
||||||
dcache_size : natural
|
|
||||||
);
|
|
||||||
PORT
|
PORT
|
||||||
(
|
(
|
||||||
RST_I : in STD_LOGIC;
|
RST_I : in STD_LOGIC;
|
||||||
@@ -152,12 +147,7 @@ inst_pipeline: pipeline
|
|||||||
dmem_dout => dmem_dout
|
dmem_dout => dmem_dout
|
||||||
);
|
);
|
||||||
|
|
||||||
inst_biu: biu
|
inst_bui: bui
|
||||||
GENERIC MAP
|
|
||||||
(
|
|
||||||
icache_size => 4096, -- words
|
|
||||||
dcache_size => 4096 -- words
|
|
||||||
)
|
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
RST_I => RST_I,
|
RST_I => RST_I,
|
||||||
|
|||||||
@@ -30,7 +30,7 @@ use IEEE.numeric_std.ALL;
|
|||||||
package mips_types is
|
package mips_types is
|
||||||
|
|
||||||
-- Revision of the CPU
|
-- Revision of the CPU
|
||||||
constant REVISION : integer := 9;
|
constant REVISION : integer := 1;
|
||||||
constant WORD_WIDTH : integer := 32;
|
constant WORD_WIDTH : integer := 32;
|
||||||
|
|
||||||
--Types
|
--Types
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,320 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2008 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"3C1D7FFF", -- 00000000
|
||||||
|
X"0C100014", -- 00000004
|
||||||
|
X"37BDEFFC", -- 00000008
|
||||||
|
X"24080002", -- 0000000C
|
||||||
|
X"0107102A", -- 00000010
|
||||||
|
X"ACC40000", -- 00000014
|
||||||
|
X"1040000B", -- 00000018
|
||||||
|
X"ACC50004", -- 0000001C
|
||||||
|
X"24C60008", -- 00000020
|
||||||
|
X"24E8FFFE", -- 00000024
|
||||||
|
X"8CC2FFF8", -- 00000028
|
||||||
|
X"8CC3FFFC", -- 0000002C
|
||||||
|
X"2508FFFF", -- 00000030
|
||||||
|
X"00431021", -- 00000034
|
||||||
|
X"ACC20000", -- 00000038
|
||||||
|
X"1500FFFA", -- 0000003C
|
||||||
|
X"24C60004", -- 00000040
|
||||||
|
X"00E04021", -- 00000044
|
||||||
|
X"03E00008", -- 00000048
|
||||||
|
X"01001021", -- 0000004C
|
||||||
|
X"27BDFF78", -- 00000050
|
||||||
|
X"3C021003", -- 00000054
|
||||||
|
X"3C030001", -- 00000058
|
||||||
|
X"AFB60078", -- 0000005C
|
||||||
|
X"3456FFFC", -- 00000060
|
||||||
|
X"3C02AAAA", -- 00000064
|
||||||
|
X"AFB7007C", -- 00000068
|
||||||
|
X"AFB50074", -- 0000006C
|
||||||
|
X"AFB40070", -- 00000070
|
||||||
|
X"AFB20068", -- 00000074
|
||||||
|
X"AFB00060", -- 00000078
|
||||||
|
X"AFBF0080", -- 0000007C
|
||||||
|
X"AFB3006C", -- 00000080
|
||||||
|
X"AFB10064", -- 00000084
|
||||||
|
X"AEC00000", -- 00000088
|
||||||
|
X"3450AAAA", -- 0000008C
|
||||||
|
X"347786A0", -- 00000090
|
||||||
|
X"27B20010", -- 00000094
|
||||||
|
X"24150014", -- 00000098
|
||||||
|
X"3474869F", -- 0000009C
|
||||||
|
X"00009821", -- 000000A0
|
||||||
|
X"00002021", -- 000000A4
|
||||||
|
X"02401021", -- 000000A8
|
||||||
|
X"24060013", -- 000000AC
|
||||||
|
X"24C6FFFF", -- 000000B0
|
||||||
|
X"AC500000", -- 000000B4
|
||||||
|
X"04C1FFFD", -- 000000B8
|
||||||
|
X"24420004", -- 000000BC
|
||||||
|
X"02041026", -- 000000C0
|
||||||
|
X"24910001", -- 000000C4
|
||||||
|
X"24420001", -- 000000C8
|
||||||
|
X"02202821", -- 000000CC
|
||||||
|
X"27A60010", -- 000000D0
|
||||||
|
X"24070014", -- 000000D4
|
||||||
|
X"0C100003", -- 000000D8
|
||||||
|
X"00028040", -- 000000DC
|
||||||
|
X"24070002", -- 000000E0
|
||||||
|
X"26450008", -- 000000E4
|
||||||
|
X"0810003E", -- 000000E8
|
||||||
|
X"24060011", -- 000000EC
|
||||||
|
X"04C0000A", -- 000000F0
|
||||||
|
X"00000000", -- 000000F4
|
||||||
|
X"8CA20000", -- 000000F8
|
||||||
|
X"8CA3FFFC", -- 000000FC
|
||||||
|
X"8CA4FFF8", -- 00000100
|
||||||
|
X"00431023", -- 00000104
|
||||||
|
X"24C6FFFF", -- 00000108
|
||||||
|
X"1482FFF8", -- 0000010C
|
||||||
|
X"24A50004", -- 00000110
|
||||||
|
X"04C1FFF8", -- 00000114
|
||||||
|
X"24E70001", -- 00000118
|
||||||
|
X"10F5000C", -- 0000011C
|
||||||
|
X"00000000", -- 00000120
|
||||||
|
X"0291102A", -- 00000124
|
||||||
|
X"1040FFDF", -- 00000128
|
||||||
|
X"02202021", -- 0000012C
|
||||||
|
X"1677FFDB", -- 00000130
|
||||||
|
X"00009821", -- 00000134
|
||||||
|
X"8EC20000", -- 00000138
|
||||||
|
X"00000000", -- 0000013C
|
||||||
|
X"24420001", -- 00000140
|
||||||
|
X"AEC20000", -- 00000144
|
||||||
|
X"0810002A", -- 00000148
|
||||||
|
X"00002021", -- 0000014C
|
||||||
|
X"08100049", -- 00000150
|
||||||
|
X"26730001", -- 00000154
|
||||||
|
X"00000000", -- 00000158
|
||||||
|
X"00000000", -- 0000015C
|
||||||
|
X"00000000", -- 00000160
|
||||||
|
X"00000000", -- 00000164
|
||||||
|
X"00000000", -- 00000168
|
||||||
|
X"00000000", -- 0000016C
|
||||||
|
X"00000000", -- 00000170
|
||||||
|
X"00000000", -- 00000174
|
||||||
|
X"00000000", -- 00000178
|
||||||
|
X"00000000", -- 0000017C
|
||||||
|
X"00000000", -- 00000180
|
||||||
|
X"00000000", -- 00000184
|
||||||
|
X"00000000", -- 00000188
|
||||||
|
X"00000000", -- 0000018C
|
||||||
|
X"00000000", -- 00000190
|
||||||
|
X"00000000", -- 00000194
|
||||||
|
X"00000000", -- 00000198
|
||||||
|
X"00000000", -- 0000019C
|
||||||
|
X"00000000", -- 000001A0
|
||||||
|
X"00000000", -- 000001A4
|
||||||
|
X"00000000", -- 000001A8
|
||||||
|
X"00000000", -- 000001AC
|
||||||
|
X"00000000", -- 000001B0
|
||||||
|
X"00000000", -- 000001B4
|
||||||
|
X"00000000", -- 000001B8
|
||||||
|
X"00000000", -- 000001BC
|
||||||
|
X"00000000", -- 000001C0
|
||||||
|
X"00000000", -- 000001C4
|
||||||
|
X"00000000", -- 000001C8
|
||||||
|
X"00000000", -- 000001CC
|
||||||
|
X"00000000", -- 000001D0
|
||||||
|
X"00000000", -- 000001D4
|
||||||
|
X"00000000", -- 000001D8
|
||||||
|
X"00000000", -- 000001DC
|
||||||
|
X"00000000", -- 000001E0
|
||||||
|
X"00000000", -- 000001E4
|
||||||
|
X"00000000", -- 000001E8
|
||||||
|
X"00000000", -- 000001EC
|
||||||
|
X"00000000", -- 000001F0
|
||||||
|
X"00000000", -- 000001F4
|
||||||
|
X"00000000", -- 000001F8
|
||||||
|
X"00000000", -- 000001FC
|
||||||
|
X"00000000", -- 00000200
|
||||||
|
X"00000000", -- 00000204
|
||||||
|
X"00000000", -- 00000208
|
||||||
|
X"00000000", -- 0000020C
|
||||||
|
X"00000000", -- 00000210
|
||||||
|
X"00000000", -- 00000214
|
||||||
|
X"00000000", -- 00000218
|
||||||
|
X"00000000", -- 0000021C
|
||||||
|
X"00000000", -- 00000220
|
||||||
|
X"00000000", -- 00000224
|
||||||
|
X"00000000", -- 00000228
|
||||||
|
X"00000000", -- 0000022C
|
||||||
|
X"00000000", -- 00000230
|
||||||
|
X"00000000", -- 00000234
|
||||||
|
X"00000000", -- 00000238
|
||||||
|
X"00000000", -- 0000023C
|
||||||
|
X"00000000", -- 00000240
|
||||||
|
X"00000000", -- 00000244
|
||||||
|
X"00000000", -- 00000248
|
||||||
|
X"00000000", -- 0000024C
|
||||||
|
X"00000000", -- 00000250
|
||||||
|
X"00000000", -- 00000254
|
||||||
|
X"00000000", -- 00000258
|
||||||
|
X"00000000", -- 0000025C
|
||||||
|
X"00000000", -- 00000260
|
||||||
|
X"00000000", -- 00000264
|
||||||
|
X"00000000", -- 00000268
|
||||||
|
X"00000000", -- 0000026C
|
||||||
|
X"00000000", -- 00000270
|
||||||
|
X"00000000", -- 00000274
|
||||||
|
X"00000000", -- 00000278
|
||||||
|
X"00000000", -- 0000027C
|
||||||
|
X"00000000", -- 00000280
|
||||||
|
X"00000000", -- 00000284
|
||||||
|
X"00000000", -- 00000288
|
||||||
|
X"00000000", -- 0000028C
|
||||||
|
X"00000000", -- 00000290
|
||||||
|
X"00000000", -- 00000294
|
||||||
|
X"00000000", -- 00000298
|
||||||
|
X"00000000", -- 0000029C
|
||||||
|
X"00000000", -- 000002A0
|
||||||
|
X"00000000", -- 000002A4
|
||||||
|
X"00000000", -- 000002A8
|
||||||
|
X"00000000", -- 000002AC
|
||||||
|
X"00000000", -- 000002B0
|
||||||
|
X"00000000", -- 000002B4
|
||||||
|
X"00000000", -- 000002B8
|
||||||
|
X"00000000", -- 000002BC
|
||||||
|
X"00000000", -- 000002C0
|
||||||
|
X"00000000", -- 000002C4
|
||||||
|
X"00000000", -- 000002C8
|
||||||
|
X"00000000", -- 000002CC
|
||||||
|
X"00000000", -- 000002D0
|
||||||
|
X"00000000", -- 000002D4
|
||||||
|
X"00000000", -- 000002D8
|
||||||
|
X"00000000", -- 000002DC
|
||||||
|
X"00000000", -- 000002E0
|
||||||
|
X"00000000", -- 000002E4
|
||||||
|
X"00000000", -- 000002E8
|
||||||
|
X"00000000", -- 000002EC
|
||||||
|
X"00000000", -- 000002F0
|
||||||
|
X"00000000", -- 000002F4
|
||||||
|
X"00000000", -- 000002F8
|
||||||
|
X"00000000", -- 000002FC
|
||||||
|
X"00000000", -- 00000300
|
||||||
|
X"00000000", -- 00000304
|
||||||
|
X"00000000", -- 00000308
|
||||||
|
X"00000000", -- 0000030C
|
||||||
|
X"00000000", -- 00000310
|
||||||
|
X"00000000", -- 00000314
|
||||||
|
X"00000000", -- 00000318
|
||||||
|
X"00000000", -- 0000031C
|
||||||
|
X"00000000", -- 00000320
|
||||||
|
X"00000000", -- 00000324
|
||||||
|
X"00000000", -- 00000328
|
||||||
|
X"00000000", -- 0000032C
|
||||||
|
X"00000000", -- 00000330
|
||||||
|
X"00000000", -- 00000334
|
||||||
|
X"00000000", -- 00000338
|
||||||
|
X"00000000", -- 0000033C
|
||||||
|
X"00000000", -- 00000340
|
||||||
|
X"00000000", -- 00000344
|
||||||
|
X"00000000", -- 00000348
|
||||||
|
X"00000000", -- 0000034C
|
||||||
|
X"00000000", -- 00000350
|
||||||
|
X"00000000", -- 00000354
|
||||||
|
X"00000000", -- 00000358
|
||||||
|
X"00000000", -- 0000035C
|
||||||
|
X"00000000", -- 00000360
|
||||||
|
X"00000000", -- 00000364
|
||||||
|
X"00000000", -- 00000368
|
||||||
|
X"00000000", -- 0000036C
|
||||||
|
X"00000000", -- 00000370
|
||||||
|
X"00000000", -- 00000374
|
||||||
|
X"00000000", -- 00000378
|
||||||
|
X"00000000", -- 0000037C
|
||||||
|
X"00000000", -- 00000380
|
||||||
|
X"00000000", -- 00000384
|
||||||
|
X"00000000", -- 00000388
|
||||||
|
X"00000000", -- 0000038C
|
||||||
|
X"00000000", -- 00000390
|
||||||
|
X"00000000", -- 00000394
|
||||||
|
X"00000000", -- 00000398
|
||||||
|
X"00000000", -- 0000039C
|
||||||
|
X"00000000", -- 000003A0
|
||||||
|
X"00000000", -- 000003A4
|
||||||
|
X"00000000", -- 000003A8
|
||||||
|
X"00000000", -- 000003AC
|
||||||
|
X"00000000", -- 000003B0
|
||||||
|
X"00000000", -- 000003B4
|
||||||
|
X"00000000", -- 000003B8
|
||||||
|
X"00000000", -- 000003BC
|
||||||
|
X"00000000", -- 000003C0
|
||||||
|
X"00000000", -- 000003C4
|
||||||
|
X"00000000", -- 000003C8
|
||||||
|
X"00000000", -- 000003CC
|
||||||
|
X"00000000", -- 000003D0
|
||||||
|
X"00000000", -- 000003D4
|
||||||
|
X"00000000", -- 000003D8
|
||||||
|
X"00000000", -- 000003DC
|
||||||
|
X"00000000", -- 000003E0
|
||||||
|
X"00000000", -- 000003E4
|
||||||
|
X"00000000", -- 000003E8
|
||||||
|
X"00000000", -- 000003EC
|
||||||
|
X"00000000", -- 000003F0
|
||||||
|
X"00000000", -- 000003F4
|
||||||
|
X"00000000", -- 000003F8
|
||||||
|
X"00000000" -- 000003FC
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||||
|
X"3c011234", -- [0x00400004] lui $1, 4660
|
||||||
|
X"34215678", -- [0x00400008] ori $1, $1, 22136
|
||||||
|
X"3021f00f", -- [0x0040000c] andi $1, $1, -4081
|
||||||
|
X"2021affc", -- [0x00400010] addi $1, $1, -20484
|
||||||
|
X"2021ffff", -- [0x00400014] addi $1, $1, -1
|
||||||
|
X"1c20fffe", -- [0x00400018] bgtz $1 -8 [loop-0x00400018]
|
||||||
|
X"3c020000", -- [0x0040001c] lui $2, 0
|
||||||
|
X"34420001", -- [0x00400020] ori $2, $2, 1
|
||||||
|
X"3c010000", -- [0x00400024] lui $1, 0
|
||||||
|
X"34210004", -- [0x00400028] ori $1, $1, 4
|
||||||
|
X"00220822", -- [0x0040002c] sub $1, $1, $2
|
||||||
|
X"1c20fffe", -- [0x00400030] bgtz $1 -8 [loop2-0x00400030]
|
||||||
|
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||||
|
X"03e00008", -- [0x00400038] jr $31
|
||||||
|
X"00000000", -- [0x0040003c] nop
|
||||||
|
X"00000000", -- [0x00400040] nop
|
||||||
|
X"00000000", -- [0x00400044] nop
|
||||||
|
X"00000000", -- [0x00400048] nop
|
||||||
|
X"00000000", -- [0x0040004c] nop
|
||||||
|
X"00000000", -- [0x00400050] nop
|
||||||
|
X"00000000", -- [0x00400054] nop
|
||||||
|
X"00000000", -- [0x00400058] nop
|
||||||
|
X"00000000", -- [0x0040005c] nop
|
||||||
|
X"00000000", -- [0x00400060] nop
|
||||||
|
X"00000000", -- [0x00400064] nop
|
||||||
|
X"00000000", -- [0x00400068] nop
|
||||||
|
X"00000000", -- [0x0040006c] nop
|
||||||
|
X"00000000", -- [0x00400070] nop
|
||||||
|
X"00000000", -- [0x00400074] nop
|
||||||
|
X"00000000", -- [0x00400078] nop
|
||||||
|
X"00000000", -- [0x0040007c] nop
|
||||||
|
X"00000000", -- [0x00400080] nop
|
||||||
|
X"00000000", -- [0x00400084] nop
|
||||||
|
X"00000000", -- [0x00400088] nop
|
||||||
|
X"00000000", -- [0x0040008c] nop
|
||||||
|
X"00000000", -- [0x00400090] nop
|
||||||
|
X"00000000", -- [0x00400094] nop
|
||||||
|
X"00000000", -- [0x00400098] nop
|
||||||
|
X"00000000", -- [0x0040009c] nop
|
||||||
|
X"00000000", -- [0x004000a0] nop
|
||||||
|
X"00000000", -- [0x004000a4] nop
|
||||||
|
X"00000000", -- [0x004000a8] nop
|
||||||
|
X"00000000", -- [0x004000ac] nop
|
||||||
|
X"00000000", -- [0x004000b0] nop
|
||||||
|
X"00000000", -- [0x004000b4] nop
|
||||||
|
X"00000000", -- [0x004000b8] nop
|
||||||
|
X"00000000", -- [0x004000bc] nop
|
||||||
|
X"00000000", -- [0x004000c0] nop
|
||||||
|
X"00000000", -- [0x004000c4] nop
|
||||||
|
X"00000000", -- [0x004000c8] nop
|
||||||
|
X"00000000", -- [0x004000cc] nop
|
||||||
|
X"00000000", -- [0x004000d0] nop
|
||||||
|
X"00000000", -- [0x004000d4] nop
|
||||||
|
X"00000000", -- [0x004000d8] nop
|
||||||
|
X"00000000", -- [0x004000dc] nop
|
||||||
|
X"00000000", -- [0x004000e0] nop
|
||||||
|
X"00000000", -- [0x004000e4] nop
|
||||||
|
X"00000000", -- [0x004000e8] nop
|
||||||
|
X"00000000", -- [0x004000ec] nop
|
||||||
|
X"00000000", -- [0x004000f0] nop
|
||||||
|
X"00000000", -- [0x004000f4] nop
|
||||||
|
X"00000000", -- [0x004000f8] nop
|
||||||
|
X"00000000" -- [0x004000fc] nop
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,73 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"08100001", -- j 0x00400004 [main] ; 5: j main
|
||||||
|
X"3c011234", -- lui $1, 4660 ; 7: lui $1, 0x1234
|
||||||
|
X"34215678", -- ori $1, $1, 22136 ; 8: ori $1, $1, 0x5678
|
||||||
|
X"3c035555", -- lui $3, 21845 ; 9: lui $3, 0x5555
|
||||||
|
X"3463aaaa", -- ori $3, $3, -21846 ; 10: ori $3, $3, 0xAAAA
|
||||||
|
X"3c021000", -- lui $2, 4096 ; 11: lui $2, 0x1000
|
||||||
|
X"ac410000", -- sw $1, 0($2) ; 12: sw $1, 0($2)
|
||||||
|
X"ac430004", -- sw $3, 4($2) ; 13: sw $3, 4($2)
|
||||||
|
X"00000000", -- nop ; 14: sll $0, $0, 0
|
||||||
|
X"ac400000", -- sw $0, 0($2) ; 15: sw $0, 0($2)
|
||||||
|
X"ac400004", -- sw $0, 4($2) ; 16: sw $0, 4($2)
|
||||||
|
X"8c410000", -- lw $1, 0($2) ; 17: lw $1, 0($2)
|
||||||
|
X"8c430004", -- lw $3, 4($2) ; 18: lw $3, 4($2)
|
||||||
|
X"00000000", -- nop ; 19: sll $0, $0, 0
|
||||||
|
X"00000000", -- nop ; 20: sll $0, $0, 0
|
||||||
|
X"08100001" -- j 0x00400004 [main] ; 21: j main
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,122 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
|
||||||
|
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||||
|
X"3c011234", -- [0x00400004] lui $1, 4660
|
||||||
|
X"34215a5a", -- [0x00400008] ori $1, $1, 23130
|
||||||
|
X"00010840", -- [0x0040000c] sll $1, $1, 1
|
||||||
|
X"00010900", -- [0x00400010] sll $1, $1, 4
|
||||||
|
X"00010880", -- [0x00400014] sll $1, $1, 2
|
||||||
|
X"00010840", -- [0x00400018] sll $1, $1, 1
|
||||||
|
X"00010a00", -- [0x0040001c] sll $1, $1, 8
|
||||||
|
X"00010882", -- [0x00400020] srl $1, $1, 2
|
||||||
|
X"00010942", -- [0x00400024] srl $1, $1, 5
|
||||||
|
X"00010842", -- [0x00400028] srl $1, $1, 1
|
||||||
|
X"00010a02", -- [0x0040002c] srl $1, $1, 8
|
||||||
|
X"3821ffff", -- [0x00400030] xori $1, $1, -1
|
||||||
|
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||||
|
X"03e00008", -- [0x00400038] jr $31
|
||||||
|
X"003f0826", -- [0x0040003c] xor $1, $1, $31
|
||||||
|
X"00000000", -- [0x00400040] nop
|
||||||
|
X"00000000", -- [0x00400044] nop
|
||||||
|
X"00000000", -- [0x00400048] nop
|
||||||
|
X"00000000", -- [0x0040004c] nop
|
||||||
|
X"00000000", -- [0x00400050] nop
|
||||||
|
X"00000000", -- [0x00400054] nop
|
||||||
|
X"00000000", -- [0x00400058] nop
|
||||||
|
X"00000000", -- [0x0040005c] nop
|
||||||
|
X"00000000", -- [0x00400060] nop
|
||||||
|
X"00000000", -- [0x00400064] nop
|
||||||
|
X"00000000", -- [0x00400068] nop
|
||||||
|
X"00000000", -- [0x0040006c] nop
|
||||||
|
X"00000000", -- [0x00400070] nop
|
||||||
|
X"00000000", -- [0x00400074] nop
|
||||||
|
X"00000000", -- [0x00400078] nop
|
||||||
|
X"00000000", -- [0x0040007c] nop
|
||||||
|
X"00000000", -- [0x00400080] nop
|
||||||
|
X"00000000", -- [0x00400084] nop
|
||||||
|
X"00000000", -- [0x00400088] nop
|
||||||
|
X"00000000", -- [0x0040008c] nop
|
||||||
|
X"00000000", -- [0x00400090] nop
|
||||||
|
X"00000000", -- [0x00400094] nop
|
||||||
|
X"00000000", -- [0x00400098] nop
|
||||||
|
X"00000000", -- [0x0040009c] nop
|
||||||
|
X"00000000", -- [0x004000a0] nop
|
||||||
|
X"00000000", -- [0x004000a4] nop
|
||||||
|
X"00000000", -- [0x004000a8] nop
|
||||||
|
X"00000000", -- [0x004000ac] nop
|
||||||
|
X"00000000", -- [0x004000b0] nop
|
||||||
|
X"00000000", -- [0x004000b4] nop
|
||||||
|
X"00000000", -- [0x004000b8]
|
||||||
|
X"00000000", -- [0x004000bc]
|
||||||
|
X"00000000", -- [0x004000c0]
|
||||||
|
X"00000000", -- [0x004000c4]
|
||||||
|
X"00000000", -- [0x004000c8]
|
||||||
|
X"00000000", -- [0x004000cc]
|
||||||
|
X"00000000", -- [0x004000d0]
|
||||||
|
X"00000000", -- [0x004000d4]
|
||||||
|
X"00000000", -- [0x004000d8]
|
||||||
|
X"00000000", -- [0x004000dc]
|
||||||
|
X"00000000", -- [0x004000e0]
|
||||||
|
X"00000000", -- [0x004000e4]
|
||||||
|
X"00000000", -- [0x004000e8]
|
||||||
|
X"00000000", -- [0x004000ec]
|
||||||
|
X"00000000", -- [0x004000f0]
|
||||||
|
X"00000000", -- [0x004000f4]
|
||||||
|
X"00000000", -- [0x004000f8]
|
||||||
|
X"00000000" -- [0x004000fc]
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,122 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
|
||||||
|
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
|
||||||
|
X"00000000", -- [0x00400004] nop ; 7: sll $0, $0, 0
|
||||||
|
X"3c011000", -- [0x00400008] lui $1, 4096 ; 8: lui $1, 0x1000
|
||||||
|
X"20220000", -- [0x0040000c] addi $2, $1, 0 ; 9: addi $2, $1, 0
|
||||||
|
X"3c071234", -- [0x00400010] lui $7, 4660 ; 10: lui $7, 0x1234
|
||||||
|
X"3c050001", -- [0x00400014] lui $5, 1 ; 11: lui $5, 0x0001
|
||||||
|
X"ac270000", -- [0x00400018] sw $7, 0($1) ; 12: sw $7, 0($1)
|
||||||
|
X"8c430000", -- [0x0040001c] lw $3, 0($2) ; 13: lw $3, 0($2)
|
||||||
|
X"00654020", -- [0x00400020] add $8, $3, $5 ; 14: add $8, $3, $5
|
||||||
|
X"00654820", -- [0x00400024] add $9, $3, $5 ; 15: add $9, $3, $5
|
||||||
|
X"00655020", -- [0x00400028] add $10, $3, $5 ; 16: add $10, $3, $5
|
||||||
|
X"00655820", -- [0x0040002c] add $11, $3, $5 ; 17: add $11, $3, $5
|
||||||
|
X"00000000", -- [0x00400030] nop ; 18: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
|
||||||
|
X"08100001", -- [0x00400038] j 0x00400004 [main] ; 20: j main
|
||||||
|
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,122 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
|
||||||
|
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||||
|
X"3c018000", -- [0x00400004] lui $1, -32768
|
||||||
|
X"3c020000", -- [0x00400008] lui $2, 0
|
||||||
|
X"3c030000", -- [0x0040000c] lui $3, 0
|
||||||
|
X"34420001", -- [0x00400010] ori $2, $2, 1
|
||||||
|
X"34630003", -- [0x00400014] ori $3, $3, 3
|
||||||
|
X"00010842", -- [0x00400018] srl $1, $1, 1
|
||||||
|
X"00010840", -- [0x0040001c] sll $1, $1, 1
|
||||||
|
X"00010843", -- [0x00400020] sra $1, $1, 1
|
||||||
|
X"000108c3", -- [0x00400024] sra $1, $1, 3
|
||||||
|
X"00612004", -- [0x00400028] sllv $4, $1, $3
|
||||||
|
X"00412807", -- [0x0040002c] srav $5, $1, $2
|
||||||
|
X"00613007", -- [0x00400030] srav $6, $1, $3
|
||||||
|
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||||
|
X"03e00008", -- [0x00400038] jr $31
|
||||||
|
X"00000000", -- [0x0040003c] nop
|
||||||
|
X"00000000", -- [0x00400040] nop
|
||||||
|
X"00000000", -- [0x00400044] nop
|
||||||
|
X"00000000", -- [0x00400048] nop
|
||||||
|
X"00000000", -- [0x0040004c] nop
|
||||||
|
X"00000000", -- [0x00400050] nop
|
||||||
|
X"00000000", -- [0x00400054] nop
|
||||||
|
X"00000000", -- [0x00400058] nop
|
||||||
|
X"00000000", -- [0x0040005c] nop
|
||||||
|
X"00000000", -- [0x00400060] nop
|
||||||
|
X"00000000", -- [0x00400064] nop
|
||||||
|
X"00000000", -- [0x00400068] nop
|
||||||
|
X"00000000", -- [0x0040006c] nop
|
||||||
|
X"00000000", -- [0x00400070] nop
|
||||||
|
X"00000000", -- [0x00400074] nop
|
||||||
|
X"00000000", -- [0x00400078] nop
|
||||||
|
X"00000000", -- [0x0040007c] nop
|
||||||
|
X"00000000", -- [0x00400080] nop
|
||||||
|
X"00000000", -- [0x00400084] nop
|
||||||
|
X"00000000", -- [0x00400088] nop
|
||||||
|
X"00000000", -- [0x0040008c] nop
|
||||||
|
X"00000000", -- [0x00400090] nop
|
||||||
|
X"00000000", -- [0x00400094] nop
|
||||||
|
X"00000000", -- [0x00400098] nop
|
||||||
|
X"00000000", -- [0x0040009c] nop
|
||||||
|
X"00000000", -- [0x004000a0] nop
|
||||||
|
X"00000000", -- [0x004000a4] nop
|
||||||
|
X"00000000", -- [0x004000a8] nop
|
||||||
|
X"00000000", -- [0x004000ac] nop
|
||||||
|
X"00000000", -- [0x004000b0] nop
|
||||||
|
X"00000000", -- [0x004000b4] nop
|
||||||
|
X"00000000", -- [0x004000b8] nop
|
||||||
|
X"00000000", -- [0x004000bc] nop
|
||||||
|
X"00000000", -- [0x004000c0] nop
|
||||||
|
X"00000000", -- [0x004000c4] nop
|
||||||
|
X"00000000", -- [0x004000c8] nop
|
||||||
|
X"00000000", -- [0x004000cc] nop
|
||||||
|
X"00000000", -- [0x004000d0] nop
|
||||||
|
X"00000000", -- [0x004000d4] nop
|
||||||
|
X"00000000", -- [0x004000d8] nop
|
||||||
|
X"00000000", -- [0x004000dc] nop
|
||||||
|
X"00000000", -- [0x004000e0] nop
|
||||||
|
X"00000000", -- [0x004000e4] nop
|
||||||
|
X"00000000", -- [0x004000e8] nop
|
||||||
|
X"00000000", -- [0x004000ec] nop
|
||||||
|
X"00000000", -- [0x004000f0] nop
|
||||||
|
X"00000000", -- [0x004000f4] nop
|
||||||
|
X"00000000", -- [0x004000f8] nop
|
||||||
|
X"00000000" -- [0x004000fc] nop
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
|
||||||
|
X"3c080000", -- [0x00400004] lui $8, 0 ; 7: lui $8, 0
|
||||||
|
X"00000000", -- [0x00400008] nop ; 8: sll $0, $0, 0
|
||||||
|
X"0c100009", -- [0x0040000c] jal 0x00400024 [subr1] ; 9: jal subr1
|
||||||
|
X"3c010040", -- [0x00400010] lui $1, 64 [subr2] ; 10: la $2, subr2
|
||||||
|
X"34220030", -- [0x00400014] ori $2, $1, 48 [subr2]
|
||||||
|
X"00407809", -- [0x00400018] jalr $15, $2 ; 11: jalr $15, $2
|
||||||
|
X"00000000", -- [0x0040001c] nop ; 12: sll $0, $0, 0
|
||||||
|
X"08100002", -- [0x00400020] j 0x00400008 [loop] ; 13: j loop
|
||||||
|
X"21080001", -- [0x00400024] addi $8, $8, 1 ; 15: addi $8, 1
|
||||||
|
X"00000000", -- [0x00400028] nop ; 16: sll $0, $0, 0
|
||||||
|
X"03e00008", -- [0x0040002c] jr $31 ; 17: jr $31
|
||||||
|
X"21080010", -- [0x00400030] addi $8, $8, 16 ; 18: addi $8, 16
|
||||||
|
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
|
||||||
|
X"01e00008", -- [0x00400038] jr $15 ; 20: jr $15
|
||||||
|
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
|
||||||
|
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||||
|
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||||
|
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||||
|
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||||
|
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||||
|
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||||
|
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||||
|
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||||
|
X"00000000", -- [0x00400020] nop
|
||||||
|
X"00427823", -- [0x00400024] subu $15, $2, $2
|
||||||
|
X"00437823", -- [0x00400028] subu $15, $2, $3
|
||||||
|
X"00447823", -- [0x0040002c] subu $15, $2, $4
|
||||||
|
X"00457823", -- [0x00400030] subu $15, $2, $5
|
||||||
|
X"00627823", -- [0x00400034] subu $15, $3, $2
|
||||||
|
X"00637823", -- [0x00400038] subu $15, $3, $3
|
||||||
|
X"00647823", -- [0x0040003c] subu $15, $3, $4
|
||||||
|
X"00657823", -- [0x00400040] subu $15, $3, $5
|
||||||
|
X"00827823", -- [0x00400044] subu $15, $4, $2
|
||||||
|
X"00837823", -- [0x00400048] subu $15, $4, $3
|
||||||
|
X"00847823", -- [0x0040004c] subu $15, $4, $4
|
||||||
|
X"00857823", -- [0x00400050] subu $15, $4, $5
|
||||||
|
X"00a27823", -- [0x00400054] subu $15, $5, $2
|
||||||
|
X"00a37823", -- [0x00400058] subu $15, $5, $3
|
||||||
|
X"00a47823", -- [0x0040005c] subu $15, $5, $4
|
||||||
|
X"00a57823", -- [0x00400060] subu $15, $5, $5
|
||||||
|
X"00000000", -- [0x00400064] nop
|
||||||
|
X"00427822", -- [0x00400068] sub $15, $2, $2
|
||||||
|
X"00437822", -- [0x0040006c] sub $15, $2, $3
|
||||||
|
X"00447822", -- [0x00400070] sub $15, $2, $4
|
||||||
|
X"00457822", -- [0x00400074] sub $15, $2, $5
|
||||||
|
X"00627822", -- [0x00400078] sub $15, $3, $2
|
||||||
|
X"00637822", -- [0x0040007c] sub $15, $3, $3
|
||||||
|
X"00647822", -- [0x00400080] sub $15, $3, $4
|
||||||
|
X"00657822", -- [0x00400084] sub $15, $3, $5
|
||||||
|
X"00827822", -- [0x00400088] sub $15, $4, $2
|
||||||
|
X"00837822", -- [0x0040008c] sub $15, $4, $3
|
||||||
|
X"00847822", -- [0x00400090] sub $15, $4, $4
|
||||||
|
X"00857822", -- [0x00400094] sub $15, $4, $5
|
||||||
|
X"00a27822", -- [0x00400098] sub $15, $5, $2
|
||||||
|
X"00a37822", -- [0x0040009c] sub $15, $5, $3
|
||||||
|
X"00a47822", -- [0x004000a0] sub $15, $5, $4
|
||||||
|
X"00a57822", -- [0x004000a4] sub $15, $5, $5
|
||||||
|
X"00000000", -- [0x004000a8] nop
|
||||||
|
X"08104000", -- [0x004000ac] j 0x00410000 [main]
|
||||||
|
X"00000000", -- [0x004000b0] nop
|
||||||
|
X"00000000", -- [0x004000b4]
|
||||||
|
X"00000000", -- [0x004000b8]
|
||||||
|
X"00000000", -- [0x004000bc]
|
||||||
|
X"00000000", -- [0x004000c0]
|
||||||
|
X"00000000", -- [0x004000c4]
|
||||||
|
X"00000000", -- [0x004000c8]
|
||||||
|
X"00000000", -- [0x004000cc]
|
||||||
|
X"00000000", -- [0x004000d0]
|
||||||
|
X"00000000", -- [0x004000d4]
|
||||||
|
X"00000000", -- [0x004000d8]
|
||||||
|
X"00000000", -- [0x004000dc]
|
||||||
|
X"00000000", -- [0x004000e0]
|
||||||
|
X"00000000", -- [0x004000e4]
|
||||||
|
X"00000000", -- [0x004000e8]
|
||||||
|
X"00000000", -- [0x004000ec]
|
||||||
|
X"00000000", -- [0x004000f0]
|
||||||
|
X"00000000", -- [0x004000f4]
|
||||||
|
X"00000000", -- [0x004000f8]
|
||||||
|
X"00000000" -- [0x004000fc]
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||||
|
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||||
|
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||||
|
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||||
|
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||||
|
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||||
|
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||||
|
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||||
|
X"3c081000", -- [0x00400020] lui $8, 4096
|
||||||
|
X"00000000", -- [0x00400024] nop
|
||||||
|
X"0042782b", -- [0x00400028] sltu $15, $2, $2
|
||||||
|
X"0043782b", -- [0x0040002c] sltu $15, $2, $3
|
||||||
|
X"0044782b", -- [0x00400030] sltu $15, $2, $4
|
||||||
|
X"0045782b", -- [0x00400034] sltu $15, $2, $5
|
||||||
|
X"0062782b", -- [0x00400038] sltu $15, $3, $2
|
||||||
|
X"0063782b", -- [0x0040003c] sltu $15, $3, $3
|
||||||
|
X"0064782b", -- [0x00400040] sltu $15, $3, $4
|
||||||
|
X"0065782b", -- [0x00400044] sltu $15, $3, $5
|
||||||
|
X"0082782b", -- [0x00400048] sltu $15, $4, $2
|
||||||
|
X"0083782b", -- [0x0040004c] sltu $15, $4, $3
|
||||||
|
X"0084782b", -- [0x00400050] sltu $15, $4, $4
|
||||||
|
X"0085782b", -- [0x00400054] sltu $15, $4, $5
|
||||||
|
X"00a2782b", -- [0x00400058] sltu $15, $5, $2
|
||||||
|
X"00a3782b", -- [0x0040005c] sltu $15, $5, $3
|
||||||
|
X"00a4782b", -- [0x00400060] sltu $15, $5, $4
|
||||||
|
X"00a5782b", -- [0x00400064] sltu $15, $5, $5
|
||||||
|
X"00000000", -- [0x00400068] nop
|
||||||
|
X"0042782a", -- [0x0040006c] slt $15, $2, $2
|
||||||
|
X"0043782a", -- [0x00400070] slt $15, $2, $3
|
||||||
|
X"0044782a", -- [0x00400074] slt $15, $2, $4
|
||||||
|
X"0045782a", -- [0x00400078] slt $15, $2, $5
|
||||||
|
X"0062782a", -- [0x0040007c] slt $15, $3, $2
|
||||||
|
X"0063782a", -- [0x00400080] slt $15, $3, $3
|
||||||
|
X"0064782a", -- [0x00400084] slt $15, $3, $4
|
||||||
|
X"0065782a", -- [0x00400088] slt $15, $3, $5
|
||||||
|
X"0082782a", -- [0x0040008c] slt $15, $4, $2
|
||||||
|
X"0083782a", -- [0x00400090] slt $15, $4, $3
|
||||||
|
X"0084782a", -- [0x00400094] slt $15, $4, $4
|
||||||
|
X"0085782a", -- [0x00400098] slt $15, $4, $5
|
||||||
|
X"00a2782a", -- [0x0040009c] slt $15, $5, $2
|
||||||
|
X"00a3782a", -- [0x004000a0] slt $15, $5, $3
|
||||||
|
X"00a4782a", -- [0x004000a4] slt $15, $5, $4
|
||||||
|
X"00a5782a", -- [0x004000a8] slt $15, $5, $5
|
||||||
|
X"00000000", -- [0x004000ac] nop
|
||||||
|
X"08104000", -- [0x004000b0] j 0x00410000 [main]
|
||||||
|
X"00000000", -- [0x004000b4] nop
|
||||||
|
X"00000000", -- [0x004000b8]
|
||||||
|
X"00000000", -- [0x004000bc]
|
||||||
|
X"00000000", -- [0x004000c0]
|
||||||
|
X"00000000", -- [0x004000c4]
|
||||||
|
X"00000000", -- [0x004000c8]
|
||||||
|
X"00000000", -- [0x004000cc]
|
||||||
|
X"00000000", -- [0x004000d0]
|
||||||
|
X"00000000", -- [0x004000d4]
|
||||||
|
X"00000000", -- [0x004000d8]
|
||||||
|
X"00000000", -- [0x004000dc]
|
||||||
|
X"00000000", -- [0x004000e0]
|
||||||
|
X"00000000", -- [0x004000e4]
|
||||||
|
X"00000000", -- [0x004000e8]
|
||||||
|
X"00000000", -- [0x004000ec]
|
||||||
|
X"00000000", -- [0x004000f0]
|
||||||
|
X"00000000", -- [0x004000f4]
|
||||||
|
X"00000000", -- [0x004000f8]
|
||||||
|
X"00000000" -- [0x004000fc]
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||||
|
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||||
|
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||||
|
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||||
|
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||||
|
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||||
|
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||||
|
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||||
|
X"3c081000", -- [0x00400020] lui $8, 4096
|
||||||
|
X"00000000", -- [0x00400024] nop
|
||||||
|
X"2c4f1234", -- [0x00400028] sltiu $15, $2, 4660
|
||||||
|
X"2c4f2345", -- [0x0040002c] sltiu $15, $2, 9029
|
||||||
|
X"2c4fedcc", -- [0x00400030] sltiu $15, $2, -4660
|
||||||
|
X"2c4fdcbb", -- [0x00400034] sltiu $15, $2, -9029
|
||||||
|
X"2c6f1234", -- [0x00400038] sltiu $15, $3, 4660
|
||||||
|
X"2c6f2345", -- [0x0040003c] sltiu $15, $3, 9029
|
||||||
|
X"2c6fedcc", -- [0x00400040] sltiu $15, $3, -4660
|
||||||
|
X"2c6fdcbb", -- [0x00400044] sltiu $15, $3, -9029
|
||||||
|
X"2c8f1234", -- [0x00400048] sltiu $15, $4, 4660
|
||||||
|
X"2c8f2345", -- [0x0040004c] sltiu $15, $4, 9029
|
||||||
|
X"2c8fedcc", -- [0x00400050] sltiu $15, $4, -4660
|
||||||
|
X"2c8fdcbb", -- [0x00400054] sltiu $15, $4, -9029
|
||||||
|
X"2caf1234", -- [0x00400058] sltiu $15, $5, 4660
|
||||||
|
X"2caf2345", -- [0x0040005c] sltiu $15, $5, 9029
|
||||||
|
X"2cafedcc", -- [0x00400060] sltiu $15, $5, -4660
|
||||||
|
X"2cafdcbb", -- [0x00400064] sltiu $15, $5, -9029
|
||||||
|
X"00000000", -- [0x00400068] nop
|
||||||
|
X"284f1234", -- [0x0040006c] slti $15, $2, 4660
|
||||||
|
X"284f2345", -- [0x00400070] slti $15, $2, 9029
|
||||||
|
X"284fedcc", -- [0x00400074] slti $15, $2, -4660
|
||||||
|
X"284fdcbb", -- [0x00400078] slti $15, $2, -9029
|
||||||
|
X"286f1234", -- [0x0040007c] slti $15, $3, 4660
|
||||||
|
X"286f2345", -- [0x00400080] slti $15, $3, 9029
|
||||||
|
X"286fedcc", -- [0x00400084] slti $15, $3, -4660
|
||||||
|
X"286fdcbb", -- [0x00400088] slti $15, $3, -9029
|
||||||
|
X"288f1234", -- [0x0040008c] slti $15, $4, 4660
|
||||||
|
X"288f2345", -- [0x00400090] slti $15, $4, 9029
|
||||||
|
X"288fedcc", -- [0x00400094] slti $15, $4, -4660
|
||||||
|
X"288fdcbb", -- [0x00400098] slti $15, $4, -9029
|
||||||
|
X"28af1234", -- [0x0040009c] slti $15, $5, 4660
|
||||||
|
X"28af2345", -- [0x004000a0] slti $15, $5, 9029
|
||||||
|
X"28afedcc", -- [0x004000a4] slti $15, $5, -4660
|
||||||
|
X"28afdcbb", -- [0x004000a8] slti $15, $5, -9029
|
||||||
|
X"00000000", -- [0x004000ac] nop
|
||||||
|
X"08104000", -- [0x004000b0] j 0x00410000 [main]
|
||||||
|
X"00000000", -- [0x004000b4] nop
|
||||||
|
X"00000000", -- [0x004000b8]
|
||||||
|
X"00000000", -- [0x004000bc]
|
||||||
|
X"00000000", -- [0x004000c0]
|
||||||
|
X"00000000", -- [0x004000c4]
|
||||||
|
X"00000000", -- [0x004000c8]
|
||||||
|
X"00000000", -- [0x004000cc]
|
||||||
|
X"00000000", -- [0x004000d0]
|
||||||
|
X"00000000", -- [0x004000d4]
|
||||||
|
X"00000000", -- [0x004000d8]
|
||||||
|
X"00000000", -- [0x004000dc]
|
||||||
|
X"00000000", -- [0x004000e0]
|
||||||
|
X"00000000", -- [0x004000e4]
|
||||||
|
X"00000000", -- [0x004000e8]
|
||||||
|
X"00000000", -- [0x004000ec]
|
||||||
|
X"00000000", -- [0x004000f0]
|
||||||
|
X"00000000", -- [0x004000f4]
|
||||||
|
X"00000000", -- [0x004000f8]
|
||||||
|
X"00000000" -- [0x004000fc]
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,121 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY rom IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer := 2;
|
||||||
|
data_width : integer := 32
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
addr : in unsigned(addr_width-1 downto 0);
|
||||||
|
dout : out unsigned(data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END rom;
|
||||||
|
|
||||||
|
ARCHITECTURE itest OF rom IS
|
||||||
|
|
||||||
|
subtype word_t is unsigned(data_width-1 downto 0);
|
||||||
|
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||||
|
|
||||||
|
-- Assembled from itest.jsm
|
||||||
|
constant word_array : word_array_t :=
|
||||||
|
(
|
||||||
|
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||||
|
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||||
|
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||||
|
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||||
|
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||||
|
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||||
|
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||||
|
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||||
|
X"00000000", -- [0x00400020] nop
|
||||||
|
X"00427823", -- [0x00400024] subu $15, $2, $2
|
||||||
|
X"00437823", -- [0x00400028] subu $15, $2, $3
|
||||||
|
X"00447823", -- [0x0040002c] subu $15, $2, $4
|
||||||
|
X"00457823", -- [0x00400030] subu $15, $2, $5
|
||||||
|
X"00627823", -- [0x00400034] subu $15, $3, $2
|
||||||
|
X"00637823", -- [0x00400038] subu $15, $3, $3
|
||||||
|
X"00647823", -- [0x0040003c] subu $15, $3, $4
|
||||||
|
X"00657823", -- [0x00400040] subu $15, $3, $5
|
||||||
|
X"00827823", -- [0x00400044] subu $15, $4, $2
|
||||||
|
X"00837823", -- [0x00400048] subu $15, $4, $3
|
||||||
|
X"00847823", -- [0x0040004c] subu $15, $4, $4
|
||||||
|
X"00857823", -- [0x00400050] subu $15, $4, $5
|
||||||
|
X"00a27823", -- [0x00400054] subu $15, $5, $2
|
||||||
|
X"00a37823", -- [0x00400058] subu $15, $5, $3
|
||||||
|
X"00a47823", -- [0x0040005c] subu $15, $5, $4
|
||||||
|
X"00a57823", -- [0x00400060] subu $15, $5, $5
|
||||||
|
X"00000000", -- [0x00400064] nop
|
||||||
|
X"00427822", -- [0x00400068] sub $15, $2, $2
|
||||||
|
X"00437822", -- [0x0040006c] sub $15, $2, $3
|
||||||
|
X"00447822", -- [0x00400070] sub $15, $2, $4
|
||||||
|
X"00457822", -- [0x00400074] sub $15, $2, $5
|
||||||
|
X"00627822", -- [0x00400078] sub $15, $3, $2
|
||||||
|
X"00637822", -- [0x0040007c] sub $15, $3, $3
|
||||||
|
X"00647822", -- [0x00400080] sub $15, $3, $4
|
||||||
|
X"00657822", -- [0x00400084] sub $15, $3, $5
|
||||||
|
X"00827822", -- [0x00400088] sub $15, $4, $2
|
||||||
|
X"00837822", -- [0x0040008c] sub $15, $4, $3
|
||||||
|
X"00847822", -- [0x00400090] sub $15, $4, $4
|
||||||
|
X"00857822", -- [0x00400094] sub $15, $4, $5
|
||||||
|
X"00a27822", -- [0x00400098] sub $15, $5, $2
|
||||||
|
X"00a37822", -- [0x0040009c] sub $15, $5, $3
|
||||||
|
X"00a47822", -- [0x004000a0] sub $15, $5, $4
|
||||||
|
X"00a57822", -- [0x004000a4] sub $15, $5, $5
|
||||||
|
X"00000000", -- [0x004000a8] nop
|
||||||
|
X"08104000", -- [0x004000ac] j 0x00410000 [main]
|
||||||
|
X"00000000", -- [0x004000b0] nop
|
||||||
|
X"00000000", -- [0x004000b4]
|
||||||
|
X"00000000", -- [0x004000b8]
|
||||||
|
X"00000000", -- [0x004000bc]
|
||||||
|
X"00000000", -- [0x004000c0]
|
||||||
|
X"00000000", -- [0x004000c4]
|
||||||
|
X"00000000", -- [0x004000c8]
|
||||||
|
X"00000000", -- [0x004000cc]
|
||||||
|
X"00000000", -- [0x004000d0]
|
||||||
|
X"00000000", -- [0x004000d4]
|
||||||
|
X"00000000", -- [0x004000d8]
|
||||||
|
X"00000000", -- [0x004000dc]
|
||||||
|
X"00000000", -- [0x004000e0]
|
||||||
|
X"00000000", -- [0x004000e4]
|
||||||
|
X"00000000", -- [0x004000e8]
|
||||||
|
X"00000000", -- [0x004000ec]
|
||||||
|
X"00000000", -- [0x004000f0]
|
||||||
|
X"00000000", -- [0x004000f4]
|
||||||
|
X"00000000", -- [0x004000f8]
|
||||||
|
X"00000000" -- [0x004000fc]
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
PROM_READ:
|
||||||
|
dout <= word_array(to_integer(addr));
|
||||||
|
|
||||||
|
end itest;
|
||||||
@@ -0,0 +1,332 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: cpu_embedded using cpu_core and rom
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.numeric_std.ALL;
|
||||||
|
|
||||||
|
library work;
|
||||||
|
use work.mips_types.all;
|
||||||
|
|
||||||
|
entity mips_embedded is
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
rst : in STD_LOGIC;
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
halt : in STD_LOGIC;
|
||||||
|
int : in unsigned(5 downto 0);
|
||||||
|
rxd : in STD_LOGIC;
|
||||||
|
txd : out STD_LOGIC;
|
||||||
|
dout : out word_t
|
||||||
|
);
|
||||||
|
end mips_embedded;
|
||||||
|
|
||||||
|
architecture rtl of mips_embedded is
|
||||||
|
|
||||||
|
COMPONENT mips_top
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
rst : in STD_LOGIC;
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
int : in unsigned(5 downto 0);
|
||||||
|
mem_rdy : in STD_LOGIC;
|
||||||
|
mem_re : out STD_LOGIC;
|
||||||
|
mem_en : out STD_LOGIC;
|
||||||
|
mem_we : out unsigned(3 downto 0);
|
||||||
|
mem_din : in word_t;
|
||||||
|
mem_dout : out word_t;
|
||||||
|
mem_addr : out word_t
|
||||||
|
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
signal mem_din : word_t;
|
||||||
|
signal mem_dout : word_t;
|
||||||
|
signal mem_addr : word_t;
|
||||||
|
signal mem_re : std_logic;
|
||||||
|
signal mem_en : std_logic;
|
||||||
|
signal mem_we : unsigned(3 downto 0);
|
||||||
|
signal mem_rdy : std_logic;
|
||||||
|
|
||||||
|
subtype tick_usec_t is natural range 0 to 99;
|
||||||
|
signal tick_usec : tick_usec_t;
|
||||||
|
signal cnt_usec : word_t;
|
||||||
|
signal cnt_sec : word_t;
|
||||||
|
signal cnt_usec_preset : word_t;
|
||||||
|
signal cnt_sec_preset : word_t;
|
||||||
|
signal cnt_usec_en : std_logic;
|
||||||
|
signal cnt_usec_we : std_logic;
|
||||||
|
signal cnt_sec_en : std_logic;
|
||||||
|
signal cnt_sec_we : std_logic;
|
||||||
|
|
||||||
|
COMPONENT uart_tx
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
data_in : in std_logic_vector(7 downto 0);
|
||||||
|
write_buffer : in std_logic;
|
||||||
|
reset_buffer : in std_logic;
|
||||||
|
en_16_x_baud : in std_logic;
|
||||||
|
serial_out : out std_logic;
|
||||||
|
buffer_full : out std_logic;
|
||||||
|
buffer_half_full : out std_logic;
|
||||||
|
clk : in std_logic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
COMPONENT uart_rx
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
serial_in : in std_logic;
|
||||||
|
data_out : out std_logic_vector(7 downto 0);
|
||||||
|
read_buffer : in std_logic;
|
||||||
|
reset_buffer : in std_logic;
|
||||||
|
en_16_x_baud : in std_logic;
|
||||||
|
buffer_data_present : out std_logic;
|
||||||
|
buffer_full : out std_logic;
|
||||||
|
buffer_half_full : out std_logic;
|
||||||
|
clk : in std_logic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
signal baud_count : unsigned(7 downto 0);
|
||||||
|
signal en_16_x_baud : std_logic;
|
||||||
|
signal reg_we_uart_tx : std_logic;
|
||||||
|
signal tx_full : std_logic;
|
||||||
|
signal tx_half_full : std_logic;
|
||||||
|
signal reg_uart_tx : unsigned(7 downto 0);
|
||||||
|
signal reg_re_uart_rx : std_logic;
|
||||||
|
signal reg_uart_rx : std_logic_vector(7 downto 0);
|
||||||
|
signal rx_data_present : std_logic;
|
||||||
|
signal rx_full : std_logic;
|
||||||
|
signal rx_half_full : std_logic;
|
||||||
|
signal uart_status_port : unsigned(7 downto 0);
|
||||||
|
signal reg_uart_ctrl : unsigned(7 downto 0);
|
||||||
|
signal reg_uart_baud : unsigned(7 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
registers_write:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
reg_we_uart_tx <= '0';
|
||||||
|
cnt_usec_we <= '0';
|
||||||
|
cnt_sec_we <= '0';
|
||||||
|
if rst = '1' then
|
||||||
|
dout <= (others => '0');
|
||||||
|
reg_uart_baud <= to_unsigned(53, 8);
|
||||||
|
reg_uart_ctrl <= to_unsigned(0, 8);
|
||||||
|
elsif mem_en = '1' then
|
||||||
|
case mem_addr(5 downto 2) is
|
||||||
|
|
||||||
|
when "0000" =>
|
||||||
|
if mem_we(0) = '1' then
|
||||||
|
dout(7 downto 0) <= mem_dout(7 downto 0);
|
||||||
|
end if;
|
||||||
|
if mem_we(1) = '1' then
|
||||||
|
dout(15 downto 8) <= mem_dout(15 downto 8);
|
||||||
|
end if;
|
||||||
|
if mem_we(2) = '1' then
|
||||||
|
dout(23 downto 16) <= mem_dout(23 downto 16);
|
||||||
|
end if;
|
||||||
|
if mem_we(3) = '1' then
|
||||||
|
dout(31 downto 24) <= mem_dout(31 downto 24);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when "0001" =>
|
||||||
|
if mem_we(0) = '1' then
|
||||||
|
reg_we_uart_tx <= '1';
|
||||||
|
reg_uart_tx <= mem_dout(7 downto 0);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when "0010" =>
|
||||||
|
if mem_we(0) = '1' then
|
||||||
|
reg_uart_ctrl <= mem_dout(7 downto 0);
|
||||||
|
end if;
|
||||||
|
if mem_we(1) = '1' then
|
||||||
|
reg_uart_baud <= mem_dout(15 downto 8);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when "0100" =>
|
||||||
|
if mem_we(3) = '1' then
|
||||||
|
cnt_usec_we <= '1';
|
||||||
|
cnt_usec_preset <= mem_dout;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when "0101" =>
|
||||||
|
if mem_we(3) = '1' then
|
||||||
|
cnt_sec_we <= '1';
|
||||||
|
cnt_sec_preset <= mem_dout;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when others => null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
registers_read:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
reg_re_uart_rx <= '0';
|
||||||
|
if mem_en = '1' then
|
||||||
|
mem_din <= (others => '0');
|
||||||
|
case mem_addr(5 downto 2) is
|
||||||
|
|
||||||
|
when "0000" => null;
|
||||||
|
|
||||||
|
when "0001" =>
|
||||||
|
reg_re_uart_rx <= '1';
|
||||||
|
mem_din(7 downto 0) <= unsigned(reg_uart_rx);
|
||||||
|
|
||||||
|
when "0010" =>
|
||||||
|
mem_din(7 downto 0) <= uart_status_port;
|
||||||
|
mem_din(15 downto 8) <= reg_uart_baud;
|
||||||
|
|
||||||
|
when "0100" =>
|
||||||
|
mem_din <= cnt_usec;
|
||||||
|
|
||||||
|
when "0101" =>
|
||||||
|
mem_din <= cnt_sec;
|
||||||
|
|
||||||
|
when others => null;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
mem_rdy <= not halt;
|
||||||
|
|
||||||
|
inst_mips_top: mips_top
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => rst,
|
||||||
|
clk => clk,
|
||||||
|
int => int,
|
||||||
|
mem_rdy => mem_rdy,
|
||||||
|
mem_en => mem_en,
|
||||||
|
mem_we => mem_we,
|
||||||
|
mem_din => mem_din,
|
||||||
|
mem_dout => mem_dout,
|
||||||
|
mem_addr => mem_addr
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_uart_tx: uart_tx
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
data_in => std_logic_vector(reg_uart_tx),
|
||||||
|
write_buffer => reg_we_uart_tx,
|
||||||
|
reset_buffer => rst,
|
||||||
|
en_16_x_baud => en_16_x_baud,
|
||||||
|
serial_out => txd,
|
||||||
|
buffer_full => tx_full,
|
||||||
|
buffer_half_full => tx_half_full,
|
||||||
|
clk => clk
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_uart_rx: uart_rx
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
serial_in => rxd,
|
||||||
|
data_out => reg_uart_rx,
|
||||||
|
read_buffer => reg_re_uart_rx,
|
||||||
|
reset_buffer => rst,
|
||||||
|
en_16_x_baud => en_16_x_baud,
|
||||||
|
buffer_data_present => rx_data_present,
|
||||||
|
buffer_full => rx_full,
|
||||||
|
buffer_half_full => rx_half_full,
|
||||||
|
clk => clk
|
||||||
|
);
|
||||||
|
|
||||||
|
uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
|
||||||
|
|
||||||
|
tick_usec_timer:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if clk'event and clk='1' then
|
||||||
|
cnt_usec_en <= '0';
|
||||||
|
if rst = '1' then
|
||||||
|
tick_usec <= 0;
|
||||||
|
cnt_usec_en <= '0';
|
||||||
|
elsif tick_usec = tick_usec_t'high then
|
||||||
|
tick_usec <= 0;
|
||||||
|
cnt_usec_en <= '1';
|
||||||
|
else
|
||||||
|
tick_usec <= tick_usec + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
cnt_usec_timer:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if clk'event and clk='1' then
|
||||||
|
cnt_sec_en <= '0';
|
||||||
|
if rst = '1' then
|
||||||
|
cnt_usec <= (others => '0');
|
||||||
|
cnt_sec_en <= '0';
|
||||||
|
elsif cnt_usec_we = '1' then
|
||||||
|
cnt_usec <= cnt_usec_preset;
|
||||||
|
elsif cnt_usec_en = '1' then
|
||||||
|
if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then
|
||||||
|
cnt_usec <= (others => '0');
|
||||||
|
cnt_sec_en <= '1';
|
||||||
|
else
|
||||||
|
cnt_usec <= cnt_usec + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
cnt_sec_timer:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if clk'event and clk='1' then
|
||||||
|
if rst = '1' then
|
||||||
|
cnt_sec <= (others => '0');
|
||||||
|
elsif cnt_sec_we = '1' then
|
||||||
|
cnt_sec <= cnt_sec_preset;
|
||||||
|
elsif cnt_sec_en = '1' then
|
||||||
|
cnt_sec <= cnt_sec + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
baud_timer:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if clk'event and clk='1' then
|
||||||
|
if rst = '1' then
|
||||||
|
baud_count <= (others => '0');
|
||||||
|
elsif baud_count = reg_uart_baud then
|
||||||
|
baud_count <= (others => '0');
|
||||||
|
en_16_x_baud <= '1';
|
||||||
|
else
|
||||||
|
baud_count <= baud_count + 1;
|
||||||
|
en_16_x_baud <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end rtl;
|
||||||
@@ -0,0 +1,137 @@
|
|||||||
|
--------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: JIPS top file
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.numeric_std.ALL;
|
||||||
|
|
||||||
|
library work;
|
||||||
|
use work.mips_types.all;
|
||||||
|
|
||||||
|
entity mips_embedded_syn is
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
sys_rst_n_in : in STD_LOGIC;
|
||||||
|
sys_clk_in : in STD_LOGIC;
|
||||||
|
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
|
||||||
|
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
sys_rx : in STD_LOGIC;
|
||||||
|
sys_tx : out STD_LOGIC;
|
||||||
|
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
end mips_embedded_syn;
|
||||||
|
|
||||||
|
architecture struct of mips_embedded_syn is
|
||||||
|
|
||||||
|
COMPONENT mips_embedded
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
rst : in STD_LOGIC;
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
halt : in STD_LOGIC;
|
||||||
|
int : in unsigned(5 downto 0);
|
||||||
|
rxd : in STD_LOGIC;
|
||||||
|
txd : out STD_LOGIC;
|
||||||
|
dout : out word_t
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
signal dout : word_t;
|
||||||
|
signal rst : STD_LOGIC;
|
||||||
|
signal clk : STD_LOGIC;
|
||||||
|
signal halt : STD_LOGIC;
|
||||||
|
signal int : unsigned(5 downto 0);
|
||||||
|
signal btn_r : unsigned (8 downto 0);
|
||||||
|
signal dip_r : unsigned (7 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
-------------------------------------------------------------------
|
||||||
|
inst_mips_embedded: mips_embedded
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => rst,
|
||||||
|
clk => clk,
|
||||||
|
halt => halt,
|
||||||
|
int => int,
|
||||||
|
rxd => sys_rx,
|
||||||
|
txd => sys_tx,
|
||||||
|
dout => dout
|
||||||
|
);
|
||||||
|
|
||||||
|
clk <= sys_clk_in;
|
||||||
|
rst <= not sys_rst_n_in;
|
||||||
|
|
||||||
|
ERR_LED_reg:
|
||||||
|
process(rst, clk)
|
||||||
|
begin
|
||||||
|
if rst = '1' then
|
||||||
|
sys_error <= (others => '1');
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
LED_reg:
|
||||||
|
process(rst, clk)
|
||||||
|
begin
|
||||||
|
if rst = '1' then
|
||||||
|
sys_led <= (others => '0');
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
DIP_reg:
|
||||||
|
process(rst, clk)
|
||||||
|
begin
|
||||||
|
if rst = '1' then
|
||||||
|
dip_r <= (others => '0');
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
dip_r <= unsigned(sys_dip);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
BTN_reg:
|
||||||
|
process(rst, clk)
|
||||||
|
begin
|
||||||
|
if rst = '1' then
|
||||||
|
btn_r <= (others => '0');
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
btn_r <= unsigned(sys_btn);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
halt <= btn_r(4) after 6.5 ns;
|
||||||
|
int(0) <= dip_r(0) and btn_r(3) after 1 ns;
|
||||||
|
int(1) <= dip_r(1) and btn_r(3) after 1 ns;
|
||||||
|
int(2) <= dip_r(2) and btn_r(3) after 1 ns;
|
||||||
|
int(3) <= dip_r(3) and btn_r(3) after 1 ns;
|
||||||
|
int(4) <= dip_r(4) and btn_r(3) after 1 ns;
|
||||||
|
int(5) <= dip_r(5) and btn_r(3) after 1 ns;
|
||||||
|
|
||||||
|
-------------------------------------------------------------------
|
||||||
|
|
||||||
|
end struct;
|
||||||
@@ -0,0 +1,83 @@
|
|||||||
|
--------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The arithmetic logic unit
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2008 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
use IEEE.numeric_std.ALL;
|
||||||
|
|
||||||
|
use work.mips_types.all;
|
||||||
|
|
||||||
|
entity muldiv is
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
rst : in std_logic;
|
||||||
|
clk : in std_logic;
|
||||||
|
din_vld_hi : in std_logic;
|
||||||
|
din_vld_lo : in std_logic;
|
||||||
|
din_hi : in word_t;
|
||||||
|
din_lo : in word_t;
|
||||||
|
hilo_sel : in std_logic;
|
||||||
|
dout : out word_t
|
||||||
|
);
|
||||||
|
end muldiv;
|
||||||
|
|
||||||
|
architecture Behavioral of muldiv is
|
||||||
|
|
||||||
|
signal reg_hi, reg_lo : word_t;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
begin
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
proc_reg_out:
|
||||||
|
process(hilo_sel, reg_hi, reg_lo)
|
||||||
|
begin
|
||||||
|
if hilo_sel = '1' then
|
||||||
|
dout <= reg_hi;
|
||||||
|
else
|
||||||
|
dout <= reg_lo;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
proc_reg_in:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_hi <= (others => '0');
|
||||||
|
reg_lo <= (others => '0');
|
||||||
|
elsif din_vld_hi = '1' then
|
||||||
|
if hilo_sel = '1' then
|
||||||
|
reg_hi <= din_hi;
|
||||||
|
else
|
||||||
|
reg_lo <= din_hi;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if din_vld_lo = '1' then
|
||||||
|
reg_lo <= din_lo;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
end Behavioral;
|
||||||
@@ -0,0 +1,115 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY ram IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
word_addr_width : integer := 6
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
we : in unsigned(3 downto 0);
|
||||||
|
ce : in STD_LOGIC;
|
||||||
|
addr : in unsigned(31 downto 0);
|
||||||
|
din : in unsigned(31 downto 0);
|
||||||
|
dout : out unsigned(31 downto 0)
|
||||||
|
);
|
||||||
|
END ram;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF ram IS
|
||||||
|
|
||||||
|
constant depth : natural := 2**word_addr_width;
|
||||||
|
|
||||||
|
type sram_t is array (0 to depth-1) of unsigned(7 downto 0);
|
||||||
|
|
||||||
|
function sram_clear return sram_t is
|
||||||
|
|
||||||
|
variable result : sram_t;
|
||||||
|
begin
|
||||||
|
for i in 0 to sram_t'length-1 loop
|
||||||
|
result(i) := (others => '0');
|
||||||
|
end loop;
|
||||||
|
return result;
|
||||||
|
end sram_clear;
|
||||||
|
|
||||||
|
signal sram0, sram1, sram2, sram3 : sram_t := sram_clear;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
|
||||||
|
SRAM_RW:
|
||||||
|
process(clk)
|
||||||
|
variable index : natural range 0 to depth-1;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) and ce = '1' then
|
||||||
|
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||||
|
if we(0) = '1' then
|
||||||
|
sram0(index)<= din(7 downto 0);
|
||||||
|
end if;
|
||||||
|
dout(7 downto 0) <= sram0(index);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(clk)
|
||||||
|
variable index : natural range 0 to depth-1;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) and ce = '1' then
|
||||||
|
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||||
|
if we(1) = '1' then
|
||||||
|
sram1(index)<= din(15 downto 8);
|
||||||
|
end if;
|
||||||
|
dout(15 downto 8) <= sram1(index);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(clk)
|
||||||
|
variable index : natural range 0 to depth-1;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) and ce = '1' then
|
||||||
|
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||||
|
if we(2) = '1' then
|
||||||
|
sram2(index)<= din(23 downto 16);
|
||||||
|
end if;
|
||||||
|
dout(23 downto 16) <= sram2(index);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(clk)
|
||||||
|
variable index : natural range 0 to depth-1;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) and ce = '1' then
|
||||||
|
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||||
|
if we(3) = '1' then
|
||||||
|
sram3(index)<= din(31 downto 24);
|
||||||
|
end if;
|
||||||
|
dout(31 downto 24) <= sram3(index);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end behavior;
|
||||||
@@ -0,0 +1,177 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VComponents.all;
|
||||||
|
|
||||||
|
ENTITY ram IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
word_addr_width : integer := 6
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
ce : in STD_LOGIC;
|
||||||
|
we : in unsigned(3 downto 0);
|
||||||
|
addr : in unsigned(31 downto 0);
|
||||||
|
din : in unsigned(31 downto 0);
|
||||||
|
dout : out unsigned(31 downto 0)
|
||||||
|
);
|
||||||
|
END ram;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF ram IS
|
||||||
|
|
||||||
|
COMPONENT dpram_2w2r
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
addr_width : integer;
|
||||||
|
data_width : integer
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk_a : in STD_LOGIC;
|
||||||
|
clk_b : in STD_LOGIC;
|
||||||
|
en_a : in STD_LOGIC;
|
||||||
|
en_b : in STD_LOGIC;
|
||||||
|
we_a : in STD_LOGIC;
|
||||||
|
we_b : in STD_LOGIC;
|
||||||
|
addr_a : in unsigned (addr_width-1 downto 0);
|
||||||
|
addr_b : in unsigned (addr_width-1 downto 0);
|
||||||
|
din_a : in unsigned (data_width-1 downto 0);
|
||||||
|
din_b : in unsigned (data_width-1 downto 0);
|
||||||
|
dout_a : out unsigned (data_width-1 downto 0);
|
||||||
|
dout_b : out unsigned (data_width-1 downto 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
signal jtag_clk : STD_LOGIC;
|
||||||
|
signal jtag_we : unsigned(3 downto 0);
|
||||||
|
signal jtag_addr : unsigned (15 downto 0);
|
||||||
|
signal jtag_dout : unsigned (31 downto 0);
|
||||||
|
signal jtag_din : unsigned (31 downto 0);
|
||||||
|
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||||
|
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||||
|
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
gen_sram:
|
||||||
|
for i in 0 to 3 generate
|
||||||
|
begin
|
||||||
|
inst_dpram_2w2r : dpram_2w2r
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
addr_width => word_addr_width,
|
||||||
|
data_width => 8
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
clk_a => clk,
|
||||||
|
en_a => ce,
|
||||||
|
we_a => we(i),
|
||||||
|
addr_a => addr(word_addr_width+1 downto 2),
|
||||||
|
din_a => din((i+1)*8-1 downto i*8),
|
||||||
|
dout_a => dout((i+1)*8-1 downto i*8),
|
||||||
|
|
||||||
|
clk_b => jtag_clk,
|
||||||
|
en_b => jtag_we(i),
|
||||||
|
we_b => jtag_we(i),
|
||||||
|
addr_b => jtag_addr(word_addr_width-1 downto 0),
|
||||||
|
din_b => jtag_din((i+1)*8-1 downto i*8),
|
||||||
|
dout_b => jtag_dout((i+1)*8-1 downto i*8)
|
||||||
|
);
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
-- Virtex-4: JTAG Loader
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
i00_BUFG : BUFG
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
O => bs_clk1,
|
||||||
|
I => bs_clk0
|
||||||
|
);
|
||||||
|
|
||||||
|
i01_BUFG : BUFG
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
O => bs_update1,
|
||||||
|
I => bs_update0
|
||||||
|
);
|
||||||
|
|
||||||
|
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||||
|
generic map
|
||||||
|
(
|
||||||
|
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||||
|
)
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||||
|
DRCK => bs_clk0, -- Data register output for USER functions
|
||||||
|
RESET => bs_rst, -- Reset output from TAP controller
|
||||||
|
SEL => bs_sel, -- USER active output
|
||||||
|
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||||
|
TDI => bs_tdi, -- TDI output from TAP controller
|
||||||
|
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||||
|
TDO => bs_tdo -- Data input for USER function
|
||||||
|
);
|
||||||
|
|
||||||
|
jtag_addr <= user_regi(user_regi'left downto jtag_dout'length);
|
||||||
|
jtag_din <= user_regi(jtag_dout'length-1 downto 0);
|
||||||
|
jtag_clk <= bs_update1;
|
||||||
|
jtag_we <= (3 downto 0 => bs_sel);
|
||||||
|
|
||||||
|
sipo:
|
||||||
|
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||||
|
begin
|
||||||
|
if bs_rst = '1' then
|
||||||
|
user_regi <= (others => '0');
|
||||||
|
elsif rising_edge(bs_clk1) then
|
||||||
|
if bs_shift = '1' then
|
||||||
|
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
piso:
|
||||||
|
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||||
|
begin
|
||||||
|
bs_tdo <= user_rego(0);
|
||||||
|
if bs_rst = '1' then
|
||||||
|
user_rego <= (others => '0');
|
||||||
|
elsif rising_edge(bs_clk1) then
|
||||||
|
if bs_shift = '1' then
|
||||||
|
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||||
|
else
|
||||||
|
user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
end behavior;
|
||||||
@@ -0,0 +1,88 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
-- This file: The ROM file for use in your VHDL design
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY ram IS
|
||||||
|
Generic
|
||||||
|
(
|
||||||
|
word_addr_width : integer := 6
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
ce : in STD_LOGIC;
|
||||||
|
we : in unsigned(3 downto 0);
|
||||||
|
addr : in unsigned(31 downto 0);
|
||||||
|
din : in unsigned(31 downto 0);
|
||||||
|
dout : out unsigned(31 downto 0)
|
||||||
|
);
|
||||||
|
END ram;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF ram IS
|
||||||
|
|
||||||
|
constant depth : natural := 2**word_addr_width;
|
||||||
|
|
||||||
|
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
|
||||||
|
|
||||||
|
function sram_clear return sram_t is
|
||||||
|
|
||||||
|
variable result : sram_t;
|
||||||
|
begin
|
||||||
|
for i in 0 to sram_t'length-1 loop
|
||||||
|
result(i) := (others => '0');
|
||||||
|
end loop;
|
||||||
|
return result;
|
||||||
|
end sram_clear;
|
||||||
|
|
||||||
|
signal sram : sram_t := sram_clear;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
|
||||||
|
SRAM_RW:
|
||||||
|
process(clk)
|
||||||
|
variable index : natural range 0 to depth-1;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) and ce = '1' then
|
||||||
|
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||||
|
if we(0) = '1' then
|
||||||
|
sram(index)(7 downto 0) <= din(7 downto 0);
|
||||||
|
end if;
|
||||||
|
if we(1) = '1' then
|
||||||
|
sram(index)(15 downto 8) <= din(15 downto 8);
|
||||||
|
end if;
|
||||||
|
if we(2) = '1' then
|
||||||
|
sram(index)(23 downto 16) <= din(23 downto 16);
|
||||||
|
end if;
|
||||||
|
if we(3) = '1' then
|
||||||
|
sram(index)(31 downto 24) <= din(31 downto 24);
|
||||||
|
end if;
|
||||||
|
dout <= sram(index);
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end behavior;
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,156 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: Testbench for JCPU
|
||||||
|
-- also writes 'opc.lst' for JASM-assembler
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
use std.textio.all; -- Imports the standard textio package.
|
||||||
|
|
||||||
|
library work;
|
||||||
|
use work.mips_types.all;
|
||||||
|
use work.mips_instr.all;
|
||||||
|
|
||||||
|
ENTITY tb_eval_muldiv IS
|
||||||
|
END tb_eval_muldiv;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF tb_eval_muldiv IS
|
||||||
|
|
||||||
|
constant CLK_PERIOD : time := 10 ns;
|
||||||
|
signal rst : std_logic := '1';
|
||||||
|
signal clk : std_logic := '1';
|
||||||
|
signal ce : std_logic := '0';
|
||||||
|
signal mul_divn : std_logic := '1';
|
||||||
|
signal op_valid : std_logic := '0';
|
||||||
|
signal op1_in : word_t := (others => '-');
|
||||||
|
signal op2_in : word_t := (others => '-');
|
||||||
|
signal result : unsigned (2*word_t'length-1 downto 0);
|
||||||
|
signal res_valid : std_logic;
|
||||||
|
signal busy : std_logic;
|
||||||
|
signal result_reg : unsigned (2*word_t'length-1 downto 0);
|
||||||
|
subtype pp_t is unsigned (39 downto 0);
|
||||||
|
|
||||||
|
signal pp0, pp1, pp2, pp3 : pp_t;
|
||||||
|
|
||||||
|
signal signed_mul : std_logic := '1';
|
||||||
|
signal sign1 : std_logic;
|
||||||
|
signal sign2 : std_logic;
|
||||||
|
signal cy : std_logic;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
sign1 <= signed_mul and op1_in(op1_in'left);
|
||||||
|
sign2 <= signed_mul and op2_in(op1_in'left);
|
||||||
|
cy <= sign1;
|
||||||
|
|
||||||
|
pp0 <= op1_in * op2_in(7 downto 0);
|
||||||
|
pp1 <= op1_in * op2_in(15 downto 8);
|
||||||
|
pp2 <= op1_in * op2_in(23 downto 16);
|
||||||
|
pp3 <= op1_in * op2_in(31 downto 24);
|
||||||
|
|
||||||
|
result <= ((63 downto 40 => '0') & pp0)
|
||||||
|
+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
|
||||||
|
+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
|
||||||
|
+ (pp3 & (23 downto 0 => '0'));
|
||||||
|
|
||||||
|
result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
|
||||||
|
|
||||||
|
CLK_GEN: process
|
||||||
|
begin
|
||||||
|
wait for CLK_PERIOD/2;
|
||||||
|
clk <= not clk;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
STIMULUS: process
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
wait for 3*CLK_PERIOD;
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
rst <= '0';
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
ce <= '1';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"FFFF_FFFA"; -- (-6)
|
||||||
|
op2_in <= X"0000_0005"; -- (+5)
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"0000_0006"; -- (+6)
|
||||||
|
op2_in <= X"FFFF_FFFB"; -- (-5)
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"1234_5678";
|
||||||
|
op2_in <= X"8765_4321";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"8765_4321";
|
||||||
|
op2_in <= X"1234_5678";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"1234_5678";
|
||||||
|
op2_in <= X"1234_5678";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"8765_4321";
|
||||||
|
op2_in <= X"8765_4321";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"789A_BCDE";
|
||||||
|
op2_in <= X"8765_4321";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait for 10*CLK_PERIOD;
|
||||||
|
op1_in <= X"8765_4321";
|
||||||
|
op2_in <= X"789A_BCDE";
|
||||||
|
op_valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
op_valid <= '0';
|
||||||
|
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
END;
|
||||||
@@ -0,0 +1,82 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: Testbench for JCPU
|
||||||
|
-- also writes 'opc.lst' for JASM-assembler
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
use std.textio.all; -- Imports the standard textio package.
|
||||||
|
|
||||||
|
library work;
|
||||||
|
use work.mips_types.all;
|
||||||
|
|
||||||
|
ENTITY tb_mips_embedded IS
|
||||||
|
END tb_mips_embedded;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF tb_mips_embedded IS
|
||||||
|
|
||||||
|
COMPONENT mips_embedded
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
rst : in STD_LOGIC;
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
halt : in STD_LOGIC;
|
||||||
|
dout : out word_t
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
constant CLK_PERIOD : time := 10 ns;
|
||||||
|
|
||||||
|
signal rst : std_logic := '1';
|
||||||
|
signal clk : std_logic := '1';
|
||||||
|
signal halt : std_logic := '0';
|
||||||
|
signal dout : word_t;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
uut: mips_embedded
|
||||||
|
PORT MAP(
|
||||||
|
rst => rst,
|
||||||
|
clk => clk,
|
||||||
|
halt => halt,
|
||||||
|
dout => dout
|
||||||
|
);
|
||||||
|
|
||||||
|
CLK_GEN: process
|
||||||
|
begin
|
||||||
|
wait for CLK_PERIOD/2;
|
||||||
|
clk <= not clk;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
STIMULUS: process
|
||||||
|
begin
|
||||||
|
|
||||||
|
wait for 3*CLK_PERIOD;
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
rst <= '0';
|
||||||
|
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
END;
|
||||||
@@ -0,0 +1,123 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: Testbench for JCPU
|
||||||
|
-- also writes 'opc.lst' for JASM-assembler
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
use std.textio.all; -- Imports the standard textio package.
|
||||||
|
|
||||||
|
ENTITY tb_mips_embedded_syn IS
|
||||||
|
END tb_mips_embedded_syn;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF tb_mips_embedded_syn IS
|
||||||
|
|
||||||
|
COMPONENT mips_embedded_syn
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
sys_rst_n_in : in STD_LOGIC;
|
||||||
|
sys_clk_in : in STD_LOGIC;
|
||||||
|
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
|
||||||
|
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
sys_rx : in STD_LOGIC;
|
||||||
|
sys_tx : out STD_LOGIC;
|
||||||
|
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
constant CLK_PERIOD : time := 10.0 ns;
|
||||||
|
|
||||||
|
signal sys_rst_n_in : std_logic := '0';
|
||||||
|
signal sys_clk_in : std_logic := '1';
|
||||||
|
signal sys_led : STD_LOGIC_VECTOR (7 downto 0);
|
||||||
|
signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
|
||||||
|
signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001";
|
||||||
|
signal sys_error : STD_LOGIC_VECTOR (1 downto 0);
|
||||||
|
signal sys_rx : std_logic := '1';
|
||||||
|
signal sys_tx : std_logic;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
uut: mips_embedded_syn
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
sys_rst_n_in => sys_rst_n_in,
|
||||||
|
sys_clk_in => sys_clk_in,
|
||||||
|
sys_btn => sys_btn,
|
||||||
|
sys_dip => sys_dip,
|
||||||
|
sys_led => sys_led,
|
||||||
|
sys_rx => sys_rx,
|
||||||
|
sys_tx => sys_tx,
|
||||||
|
sys_error => sys_error
|
||||||
|
);
|
||||||
|
|
||||||
|
CLK_GEN: process
|
||||||
|
begin
|
||||||
|
wait for CLK_PERIOD/2;
|
||||||
|
sys_clk_in <= not sys_clk_in;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
STIMULUS1: process
|
||||||
|
begin
|
||||||
|
|
||||||
|
wait for 3*CLK_PERIOD;
|
||||||
|
wait until rising_edge(sys_clk_in);
|
||||||
|
sys_rst_n_in <= '1';
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
-- wait for 9994999*CLK_PERIOD;
|
||||||
|
-- for i in 1 to 10000 loop
|
||||||
|
-- wait for 100*CLK_PERIOD;
|
||||||
|
-- sys_btn(3) <= '1';
|
||||||
|
-- wait for 10*CLK_PERIOD;
|
||||||
|
-- sys_btn(3) <= '0';
|
||||||
|
-- end loop;
|
||||||
|
|
||||||
|
wait until rising_edge(sys_clk_in) and now = 38980 ns;
|
||||||
|
sys_btn <= "000001000";
|
||||||
|
wait until rising_edge(sys_clk_in);
|
||||||
|
sys_btn <= "000000000";
|
||||||
|
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
STIMULUS2: process
|
||||||
|
begin
|
||||||
|
|
||||||
|
|
||||||
|
wait for 9999999*CLK_PERIOD;
|
||||||
|
for i in 1 to 10000 loop
|
||||||
|
wait for 137*CLK_PERIOD;
|
||||||
|
sys_btn(4) <= '1';
|
||||||
|
wait for 21*CLK_PERIOD;
|
||||||
|
sys_btn(4) <= '0';
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
END;
|
||||||
@@ -63,14 +63,12 @@ ARCHITECTURE behavior OF tb_mips_muldiv IS
|
|||||||
signal start : std_logic := '0';
|
signal start : std_logic := '0';
|
||||||
signal din_hi : word_t := (others => '-');
|
signal din_hi : word_t := (others => '-');
|
||||||
signal din_lo : word_t := (others => '-');
|
signal din_lo : word_t := (others => '-');
|
||||||
|
signal ref_hi : word_t := (others => '-');
|
||||||
|
signal ref_lo : word_t := (others => '-');
|
||||||
signal dout : word_t;
|
signal dout : word_t;
|
||||||
signal hilo_sel : std_logic := '0';
|
signal hilo_sel : std_logic := '0';
|
||||||
signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
|
signal result : unsigned (2*word_t'length-1 downto 0);
|
||||||
signal ref_result : unsigned (2*word_t'length-1 downto 0);
|
signal ref_result : unsigned (2*word_t'length-1 downto 0);
|
||||||
signal ref_hi : unsigned (word_t'length-1 downto 0);
|
|
||||||
signal rtmp : unsigned (2*word_t'length-1 downto 0);
|
|
||||||
signal tmp2 : unsigned (word_t'length-1 downto 0);
|
|
||||||
signal check : std_logic;
|
|
||||||
|
|
||||||
type word_array_t is array (natural range <>) of word_t;
|
type word_array_t is array (natural range <>) of word_t;
|
||||||
|
|
||||||
@@ -166,31 +164,35 @@ CLK_GEN: process
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
REF_GEN: process
|
REF_GEN: process
|
||||||
|
variable tmp : unsigned (2*word_t'length-1 downto 0);
|
||||||
|
variable tmp2 : unsigned (word_t'length-1 downto 0);
|
||||||
begin
|
begin
|
||||||
if mul_divn = '0' then
|
if mul_divn = '0' then
|
||||||
wait until rising_edge(clk) and check = '1';
|
wait until rising_edge(clk) and start = '1';
|
||||||
|
ref_lo <= din_lo;
|
||||||
|
ref_hi <= din_hi;
|
||||||
|
wait until rising_edge(clk) and busy = '0';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
wait until rising_edge(clk);
|
||||||
if s_un = '1' then
|
if s_un = '1' then
|
||||||
rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
|
tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo));
|
||||||
wait until rising_edge(clk);
|
tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32)));
|
||||||
tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
|
ref_result <= X"00000000" & tmp2(31 downto 0);
|
||||||
wait until rising_edge(clk);
|
|
||||||
ref_hi <= tmp2(31 downto 0);
|
|
||||||
else
|
else
|
||||||
rtmp <= md_result(31 downto 0) * din_lo;
|
tmp := result(31 downto 0) * ref_lo;
|
||||||
wait until rising_edge(clk);
|
tmp2 := tmp(31 downto 0) + result(63 downto 32);
|
||||||
tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
|
ref_result <= X"00000000" & tmp2(31 downto 0);
|
||||||
wait until rising_edge(clk);
|
|
||||||
ref_hi <= tmp2(31 downto 0);
|
|
||||||
end if;
|
end if;
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
|
|
||||||
if din_lo /= X"00000000" then
|
if ref_lo /= X"00000000" then
|
||||||
if ENABLE_FAIL_REPORT then
|
if ENABLE_FAIL_REPORT then
|
||||||
assert din_hi = ref_hi report "Error on divison" severity failure;
|
assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
else
|
else
|
||||||
wait until rising_edge(clk) and check = '1';
|
wait until rising_edge(clk) and start = '1';
|
||||||
|
wait until rising_edge(clk) and busy = '0';
|
||||||
if s_un = '1' then
|
if s_un = '1' then
|
||||||
ref_result <= unsigned(signed(din_hi) * signed(din_lo));
|
ref_result <= unsigned(signed(din_hi) * signed(din_lo));
|
||||||
else
|
else
|
||||||
@@ -200,7 +202,7 @@ REF_GEN: process
|
|||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
if ENABLE_FAIL_REPORT then
|
if ENABLE_FAIL_REPORT then
|
||||||
assert ref_result = md_result report "Error on multiplication" severity failure;
|
assert ref_result = result report "Error on multiplication" severity failure;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
@@ -219,7 +221,6 @@ STIMULUS: process
|
|||||||
s_un <= '0';
|
s_un <= '0';
|
||||||
for i in 0 to operands'length-1 loop
|
for i in 0 to operands'length-1 loop
|
||||||
for j in 0 to operands'length-1 loop
|
for j in 0 to operands'length-1 loop
|
||||||
check <= '0';
|
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
din_hi <= operands(i);
|
din_hi <= operands(i);
|
||||||
din_lo <= operands(j);
|
din_lo <= operands(j);
|
||||||
@@ -230,23 +231,17 @@ STIMULUS: process
|
|||||||
|
|
||||||
-- Read result
|
-- Read result
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
wait until rising_edge(clk);
|
result(31 downto 0) <= dout;
|
||||||
md_result(31 downto 0) <= dout;
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
hilo_sel <= '1';
|
hilo_sel <= '1';
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
md_result(63 downto 32) <= dout;
|
result(63 downto 32) <= dout;
|
||||||
check <= '1';
|
wait for 2*CLK_PERIOD;
|
||||||
wait until rising_edge(clk);
|
|
||||||
check <= '0';
|
|
||||||
wait for 8*CLK_PERIOD;
|
|
||||||
end loop;
|
end loop;
|
||||||
end loop;
|
end loop;
|
||||||
|
|
||||||
s_un <= '1';
|
s_un <= '1';
|
||||||
for i in 0 to operands'length-1 loop
|
for i in 0 to operands'length-1 loop
|
||||||
for j in 0 to operands'length-1 loop
|
for j in 0 to operands'length-1 loop
|
||||||
check <= '0';
|
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
din_hi <= operands(i);
|
din_hi <= operands(i);
|
||||||
din_lo <= operands(j);
|
din_lo <= operands(j);
|
||||||
@@ -257,16 +252,11 @@ STIMULUS: process
|
|||||||
|
|
||||||
-- Read result
|
-- Read result
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
wait until rising_edge(clk);
|
result(31 downto 0) <= dout;
|
||||||
md_result(31 downto 0) <= dout;
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
hilo_sel <= '1';
|
hilo_sel <= '1';
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
md_result(63 downto 32) <= dout;
|
result(63 downto 32) <= dout;
|
||||||
check <= '1';
|
wait for 2*CLK_PERIOD;
|
||||||
wait until rising_edge(clk);
|
|
||||||
check <= '0';
|
|
||||||
wait for 8*CLK_PERIOD;
|
|
||||||
end loop;
|
end loop;
|
||||||
end loop;
|
end loop;
|
||||||
|
|
||||||
@@ -274,7 +264,6 @@ STIMULUS: process
|
|||||||
s_un <= '0';
|
s_un <= '0';
|
||||||
for i in 0 to operands'length-1 loop
|
for i in 0 to operands'length-1 loop
|
||||||
for j in 0 to operands'length-1 loop
|
for j in 0 to operands'length-1 loop
|
||||||
check <= '0';
|
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
din_hi <= operands(i);
|
din_hi <= operands(i);
|
||||||
din_lo <= operands(j);
|
din_lo <= operands(j);
|
||||||
@@ -285,23 +274,16 @@ STIMULUS: process
|
|||||||
|
|
||||||
-- Read result
|
-- Read result
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
wait until rising_edge(clk);
|
result(31 downto 0) <= dout;
|
||||||
md_result(31 downto 0) <= dout;
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
hilo_sel <= '1';
|
hilo_sel <= '1';
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
md_result(63 downto 32) <= dout;
|
result(63 downto 32) <= dout;
|
||||||
check <= '1';
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
check <= '0';
|
|
||||||
wait for 8*CLK_PERIOD;
|
|
||||||
end loop;
|
end loop;
|
||||||
end loop;
|
end loop;
|
||||||
|
|
||||||
s_un <= '1';
|
s_un <= '1';
|
||||||
for i in 0 to operands'length-1 loop
|
for i in 0 to operands'length-1 loop
|
||||||
for j in 0 to operands'length-1 loop
|
for j in 0 to operands'length-1 loop
|
||||||
check <= '0';
|
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
din_hi <= operands(i);
|
din_hi <= operands(i);
|
||||||
din_lo <= operands(j);
|
din_lo <= operands(j);
|
||||||
@@ -312,16 +294,10 @@ STIMULUS: process
|
|||||||
|
|
||||||
-- Read result
|
-- Read result
|
||||||
wait until rising_edge(clk) and busy = '0';
|
wait until rising_edge(clk) and busy = '0';
|
||||||
wait until rising_edge(clk);
|
result(31 downto 0) <= dout;
|
||||||
md_result(31 downto 0) <= dout;
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
hilo_sel <= '1';
|
hilo_sel <= '1';
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
md_result(63 downto 32) <= dout;
|
result(63 downto 32) <= dout;
|
||||||
check <= '1';
|
|
||||||
wait until rising_edge(clk);
|
|
||||||
check <= '0';
|
|
||||||
wait for 8*CLK_PERIOD;
|
|
||||||
end loop;
|
end loop;
|
||||||
end loop;
|
end loop;
|
||||||
|
|
||||||
|
|||||||
+106
-337
@@ -25,379 +25,148 @@
|
|||||||
LIBRARY ieee;
|
LIBRARY ieee;
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
USE ieee.numeric_std.ALL;
|
USE ieee.numeric_std.ALL;
|
||||||
|
use std.textio.all; -- Imports the standard textio package.
|
||||||
|
|
||||||
library work;
|
library work;
|
||||||
use work.mips_types.all;
|
use work.mips_types.all;
|
||||||
use work.mips_instr.all;
|
use work.mips_instr.all;
|
||||||
use work.async_types.all;
|
|
||||||
use work.async_defs.all;
|
|
||||||
|
|
||||||
ENTITY tb_mips_top IS
|
ENTITY tb_mips_top IS
|
||||||
END tb_mips_top;
|
END tb_mips_top;
|
||||||
|
|
||||||
ARCHITECTURE behavior OF tb_mips_top IS
|
ARCHITECTURE behavior OF tb_mips_top IS
|
||||||
|
|
||||||
constant CLK_PERIOD : time := 10 ns;
|
COMPONENT mips_top
|
||||||
constant SRAM_ADDR_WIDTH : integer := 14; -- bits
|
Port
|
||||||
constant FLASH_ADDR_WIDTH : integer := 14; -- bits
|
(
|
||||||
|
rst : in STD_LOGIC;
|
||||||
signal debug : unsigned(1 downto 0);
|
clk : in STD_LOGIC;
|
||||||
|
halt : in STD_LOGIC;
|
||||||
|
imem_din : in unsigned (WORD_WIDTH-1 downto 0);
|
||||||
|
imem_addr : out unsigned (WORD_WIDTH-1 downto 0);
|
||||||
|
dmem_we : out STD_LOGIC;
|
||||||
|
dmem_re : out STD_LOGIC;
|
||||||
|
dmem_din : in unsigned (WORD_WIDTH-1 downto 0);
|
||||||
|
dmem_dout : out unsigned (WORD_WIDTH-1 downto 0);
|
||||||
|
dmem_addr : out unsigned (WORD_WIDTH-1 downto 0)
|
||||||
|
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
-- Master
|
COMPONENT rom
|
||||||
signal rst : STD_LOGIC := '1';
|
Port
|
||||||
signal clk : STD_LOGIC := '0';
|
(
|
||||||
signal ACK_I : STD_LOGIC := '0';
|
clk : in STD_LOGIC;
|
||||||
signal SRDY_I : STD_LOGIC := '0';
|
addr : in word_t;
|
||||||
signal ADDR_O : word_t;
|
dout : out word_t
|
||||||
signal DAT_I : word_t := (others => '0');
|
);
|
||||||
signal DAT_O : word_t;
|
END COMPONENT;
|
||||||
signal WE_O : STD_LOGIC;
|
|
||||||
signal SEL_O : unsigned(3 downto 0);
|
|
||||||
signal CYC_O : STD_LOGIC;
|
|
||||||
signal STB_O : STD_LOGIC;
|
|
||||||
signal MRDY_O : STD_LOGIC;
|
|
||||||
signal INT : unsigned (5 downto 0) := (others => '0');
|
|
||||||
|
|
||||||
-- Slaves
|
|
||||||
signal CYC_I_rom : std_logic;
|
|
||||||
signal ACK_O_rom : std_logic;
|
|
||||||
signal SRDY_O_rom : std_logic;
|
|
||||||
signal DAT_O_rom : unsigned(31 downto 0);
|
|
||||||
|
|
||||||
signal CYC_I_flash : std_logic;
|
COMPONENT ram
|
||||||
signal ACK_O_flash : std_logic;
|
Generic
|
||||||
signal SRDY_O_flash : std_logic;
|
(
|
||||||
signal DAT_O_flash : unsigned(31 downto 0);
|
word_addr_width : integer
|
||||||
|
);
|
||||||
|
Port
|
||||||
|
(
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
we : in STD_LOGIC;
|
||||||
|
addr : in word_t;
|
||||||
|
din : in word_t;
|
||||||
|
dout : out word_t
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
signal CYC_I_sram : std_logic;
|
constant CLK_PERIOD : time := 10 ns;
|
||||||
signal ACK_O_sram : std_logic;
|
|
||||||
signal SRDY_O_sram : std_logic;
|
|
||||||
signal DAT_O_sram : unsigned(31 downto 0);
|
|
||||||
|
|
||||||
signal CYC_I_gpio : std_logic;
|
signal rst : std_logic := '1';
|
||||||
signal ACK_O_gpio : std_logic;
|
signal clk : std_logic := '1';
|
||||||
signal SRDY_O_gpio : std_logic;
|
signal cpu_halt : std_logic;
|
||||||
signal DAT_O_gpio : unsigned(31 downto 0);
|
signal irom_data : word_t := (others => '-');
|
||||||
|
signal irom_addr : word_t;
|
||||||
signal CYC_I_uart : std_logic;
|
signal dmem_din : word_t := (others => '-');
|
||||||
signal ACK_O_uart : std_logic;
|
signal dmem_dout : word_t;
|
||||||
signal SRDY_O_uart : std_logic;
|
signal dmem_addr : word_t;
|
||||||
signal DAT_O_uart : unsigned(31 downto 0);
|
signal dmem_we : std_logic;
|
||||||
|
signal dmem_re : std_logic;
|
||||||
signal flash_cs_n : std_logic;
|
|
||||||
signal flash_oe_n : std_logic;
|
|
||||||
signal sram_cs_n : std_logic;
|
|
||||||
signal sram_wr_n : unsigned(3 downto 0);
|
|
||||||
signal sram_oe_n : std_logic;
|
|
||||||
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
|
||||||
signal sram_d : unsigned(31 downto 0);
|
|
||||||
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
|
|
||||||
signal flash_d : unsigned(31 downto 0);
|
|
||||||
|
|
||||||
signal gpo0 : unsigned(31 downto 0);
|
|
||||||
signal gpo1 : unsigned(31 downto 0);
|
|
||||||
signal gpi0 : unsigned(31 downto 0) := (others => '0');
|
|
||||||
signal gpi1 : unsigned(31 downto 0) := (others => '0');
|
|
||||||
|
|
||||||
signal int_uart_rx : std_logic;
|
|
||||||
signal rx : std_logic := '1';
|
|
||||||
signal tx : std_logic;
|
|
||||||
|
|
||||||
type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
|
|
||||||
signal mem_area : mem_area_t;
|
|
||||||
|
|
||||||
type word_array_t is array (natural range <>) of word_t;
|
|
||||||
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
|
|
||||||
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
|
|
||||||
------------------------------------------------------------------
|
uut: mips_top
|
||||||
|
PORT MAP(
|
||||||
|
rst => rst,
|
||||||
|
clk => clk,
|
||||||
|
halt => cpu_halt,
|
||||||
|
imem_din => irom_data,
|
||||||
|
imem_addr => irom_addr,
|
||||||
|
dmem_we => dmem_we,
|
||||||
|
dmem_re => dmem_re,
|
||||||
|
dmem_din => dmem_din,
|
||||||
|
dmem_dout => dmem_dout,
|
||||||
|
dmem_addr => dmem_addr
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_rom: rom
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
clk => clk,
|
||||||
|
addr => irom_addr,
|
||||||
|
dout => irom_data
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_ram: ram
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
word_addr_width => 6
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
clk => clk,
|
||||||
|
we => dmem_we,
|
||||||
|
addr => dmem_addr,
|
||||||
|
din => dmem_dout,
|
||||||
|
dout => dmem_din
|
||||||
|
);
|
||||||
|
|
||||||
CLK_GEN: process
|
CLK_GEN: process
|
||||||
begin
|
begin
|
||||||
wait for CLK_PERIOD/2;
|
wait for CLK_PERIOD/2;
|
||||||
clk <= not clk;
|
clk <= not clk;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
HLT_GEN:
|
||||||
-- Memory mux
|
process(rst, clk)
|
||||||
------------------------------------------------------------------
|
subtype cnt_t is natural range 0 to 2;
|
||||||
mem_mux:
|
variable cnt : cnt_t;
|
||||||
process(ADDR_O)
|
|
||||||
begin
|
|
||||||
mem_area <= mem_dead;
|
|
||||||
if ADDR_O(31 downto 28) = X"0" then
|
|
||||||
mem_area <= mem_flash;
|
|
||||||
elsif ADDR_O(31 downto 28) = X"A" then
|
|
||||||
if ADDR_O(27 downto 26) = "00" then
|
|
||||||
if ADDR_O(18 downto 16) = "000" then
|
|
||||||
mem_area <= mem_gpio;
|
|
||||||
elsif ADDR_O(18 downto 16) = "001" then
|
|
||||||
mem_area <= mem_uart;
|
|
||||||
end if;
|
|
||||||
elsif ADDR_O(27 downto 26) = "01" then
|
|
||||||
mem_area <= mem_flash;
|
|
||||||
end if;
|
|
||||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
|
||||||
mem_area <= mem_rom;
|
|
||||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
|
||||||
mem_area <= mem_sram;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
signal_mux:
|
|
||||||
process(mem_area, CYC_O)
|
|
||||||
begin
|
|
||||||
|
|
||||||
CYC_I_uart <= '0';
|
|
||||||
CYC_I_gpio <= '0';
|
|
||||||
CYC_I_flash <= '0';
|
|
||||||
CYC_I_rom <= '0';
|
|
||||||
CYC_I_sram <= '0';
|
|
||||||
|
|
||||||
case mem_area is
|
|
||||||
|
|
||||||
when mem_gpio =>
|
|
||||||
CYC_I_gpio <= CYC_O;
|
|
||||||
|
|
||||||
when mem_uart =>
|
|
||||||
CYC_I_uart <= CYC_O;
|
|
||||||
|
|
||||||
when mem_flash =>
|
|
||||||
CYC_I_flash <= CYC_O;
|
|
||||||
|
|
||||||
when mem_rom =>
|
|
||||||
CYC_I_rom <= CYC_O;
|
|
||||||
|
|
||||||
when mem_sram =>
|
|
||||||
CYC_I_sram <= CYC_O;
|
|
||||||
|
|
||||||
when others => null;
|
|
||||||
|
|
||||||
end case;
|
|
||||||
|
|
||||||
end process;
|
|
||||||
|
|
||||||
SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
|
|
||||||
ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
|
|
||||||
DAT_I <= DAT_O_sram when CYC_I_sram = '1' else
|
|
||||||
DAT_O_rom when CYC_I_rom = '1' else
|
|
||||||
DAT_O_flash when CYC_I_flash = '1' else
|
|
||||||
DAT_O_uart when CYC_I_uart = '1' else
|
|
||||||
DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
|
|
||||||
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
|
||||||
uut: entity work.mips_top
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
debug => debug,
|
|
||||||
RST_I => rst,
|
|
||||||
CLK_I => clk,
|
|
||||||
ACK_I => ACK_I,
|
|
||||||
SRDY_I => SRDY_I,
|
|
||||||
ADDR_O => ADDR_O,
|
|
||||||
DAT_I => DAT_I,
|
|
||||||
DAT_O => DAT_O,
|
|
||||||
WE_O => WE_O,
|
|
||||||
SEL_O => SEL_O,
|
|
||||||
CYC_O => CYC_O,
|
|
||||||
STB_O => STB_O,
|
|
||||||
MRDY_O => MRDY_O,
|
|
||||||
INT => INT
|
|
||||||
);
|
|
||||||
INT(1) <= int_uart_rx;
|
|
||||||
|
|
||||||
inst_rom : entity work.rom_wb
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
CLK_I => clk,
|
|
||||||
RST_I => rst,
|
|
||||||
CYC_I => CYC_I_rom,
|
|
||||||
STB_I => STB_O,
|
|
||||||
ACK_O => ACK_O_rom,
|
|
||||||
MRDY_I => MRDY_O,
|
|
||||||
SRDY_O => SRDY_O_rom,
|
|
||||||
ADDR_I => ADDR_O,
|
|
||||||
DAT_O => DAT_O_rom
|
|
||||||
);
|
|
||||||
|
|
||||||
inst_gpio : entity work.gpio_wb
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
CLK_I => clk,
|
|
||||||
RST_I => rst,
|
|
||||||
CYC_I => CYC_I_gpio,
|
|
||||||
STB_I => STB_O,
|
|
||||||
SEL_I => SEL_O,
|
|
||||||
WE_I => WE_O,
|
|
||||||
ACK_O => ACK_O_gpio,
|
|
||||||
SRDY_O => SRDY_O_gpio,
|
|
||||||
MRDY_I => MRDY_O,
|
|
||||||
ADDR_I => ADDR_O,
|
|
||||||
DAT_I => DAT_O,
|
|
||||||
DAT_O => DAT_O_gpio,
|
|
||||||
|
|
||||||
sys_gpo0 => gpo0,
|
|
||||||
sys_gpo1 => gpo1,
|
|
||||||
sys_gpi0 => gpi0,
|
|
||||||
sys_gpi1 => gpi1
|
|
||||||
);
|
|
||||||
|
|
||||||
inst_flash_port : entity work.async_port_wb
|
|
||||||
GENERIC MAP
|
|
||||||
(
|
|
||||||
addr_width => FLASH_ADDR_WIDTH,
|
|
||||||
data_width => 32,
|
|
||||||
byte_sel_width => 1,
|
|
||||||
async_timespec => ts_flash
|
|
||||||
)
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
CLK_I => clk,
|
|
||||||
RST_I => rst,
|
|
||||||
CYC_I => CYC_I_flash,
|
|
||||||
STB_I => STB_O,
|
|
||||||
WE_I => WE_O,
|
|
||||||
ACK_O => ACK_O_flash,
|
|
||||||
SRDY_O => SRDY_O_flash,
|
|
||||||
MRDY_I => MRDY_O,
|
|
||||||
SEL_I => SEL_O,
|
|
||||||
ADDR_I => ADDR_O,
|
|
||||||
DAT_I => DAT_O,
|
|
||||||
DAT_O => DAT_O_flash,
|
|
||||||
async_a => flash_a,
|
|
||||||
async_d => flash_d,
|
|
||||||
async_cs => flash_cs_n,
|
|
||||||
async_wr => open,
|
|
||||||
async_rd => flash_oe_n,
|
|
||||||
async_rst => open
|
|
||||||
);
|
|
||||||
|
|
||||||
inst_sram_port : entity work.async_port_wb
|
|
||||||
GENERIC MAP
|
|
||||||
(
|
|
||||||
addr_width => SRAM_ADDR_WIDTH,
|
|
||||||
data_width => 32,
|
|
||||||
byte_sel_width => 4,
|
|
||||||
async_timespec => ts_sram
|
|
||||||
)
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
CLK_I => clk,
|
|
||||||
RST_I => rst,
|
|
||||||
CYC_I => CYC_I_sram,
|
|
||||||
STB_I => STB_O,
|
|
||||||
WE_I => WE_O,
|
|
||||||
ACK_O => ACK_O_sram,
|
|
||||||
SRDY_O => SRDY_O_sram,
|
|
||||||
MRDY_I => MRDY_O,
|
|
||||||
SEL_I => SEL_O,
|
|
||||||
ADDR_I => ADDR_O,
|
|
||||||
DAT_I => DAT_O,
|
|
||||||
DAT_O => DAT_O_sram,
|
|
||||||
async_a => sram_a,
|
|
||||||
async_d => sram_d,
|
|
||||||
async_cs => sram_cs_n,
|
|
||||||
async_wr => sram_wr_n,
|
|
||||||
async_rd => sram_oe_n,
|
|
||||||
async_rst => open
|
|
||||||
);
|
|
||||||
|
|
||||||
inst_uart : entity work.uart_wb
|
|
||||||
PORT MAP
|
|
||||||
(
|
|
||||||
CLK_I => clk,
|
|
||||||
RST_I => rst,
|
|
||||||
CYC_I => CYC_I_uart,
|
|
||||||
STB_I => STB_O,
|
|
||||||
SEL_I => SEL_O,
|
|
||||||
WE_I => WE_O,
|
|
||||||
ACK_O => ACK_O_uart,
|
|
||||||
SRDY_O => SRDY_O_uart,
|
|
||||||
MRDY_I => MRDY_O,
|
|
||||||
ADDR_I => ADDR_O,
|
|
||||||
DAT_I => DAT_O,
|
|
||||||
DAT_O => DAT_O_uart,
|
|
||||||
INT_RX_O => int_uart_rx,
|
|
||||||
INT_TX_O => open,
|
|
||||||
ser_rx => rx,
|
|
||||||
ser_tx => tx
|
|
||||||
);
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
|
||||||
SRAM_READ:
|
|
||||||
process(sram_a, sram_cs_n, sram_oe_n)
|
|
||||||
begin
|
|
||||||
sram_d <= (others => 'Z');
|
|
||||||
if sram_oe_n = '0' then
|
|
||||||
if sram_cs_n = '0' then
|
|
||||||
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
SRAM_WRITE:
|
|
||||||
process(sram_a, sram_cs_n, sram_wr_n)
|
|
||||||
begin
|
|
||||||
if rising_edge(sram_wr_n(0)) then
|
|
||||||
if sram_cs_n = '0' then
|
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
if rising_edge(sram_wr_n(1)) then
|
|
||||||
if sram_cs_n = '0' then
|
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
if rising_edge(sram_wr_n(2)) then
|
|
||||||
if sram_cs_n = '0' then
|
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
if rising_edge(sram_wr_n(3)) then
|
|
||||||
if sram_cs_n = '0' then
|
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
|
||||||
FLASH_READ:
|
|
||||||
process(rst, flash_cs_n, flash_oe_n, flash_a)
|
|
||||||
type file_t is file of integer;
|
|
||||||
file load_flash : file_t open read_mode is "hello.flash.bin";
|
|
||||||
variable instr : integer;
|
|
||||||
variable index : natural;
|
|
||||||
variable temp : signed(31 downto 0);
|
|
||||||
begin
|
begin
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
index := 0;
|
cnt := cnt_t'high;
|
||||||
while not endfile(load_flash) loop
|
cpu_halt <= '0';
|
||||||
read(load_flash, instr);
|
elsif rising_edge(clk) then
|
||||||
temp := to_signed(instr, word_t'length);
|
cpu_halt <= '0';
|
||||||
flash_data(index) <= unsigned(temp);
|
if cnt /= 0 then
|
||||||
index := index + 1;
|
cnt := cnt - 1;
|
||||||
end loop;
|
else
|
||||||
else
|
cnt := cnt_t'high;
|
||||||
flash_d <= (others => 'Z') after 10 ns;
|
cpu_halt <= '1';
|
||||||
if flash_oe_n = '0' and flash_cs_n = '0' then
|
|
||||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
|
||||||
flash_d <= flash_data(index) after 10 ns;
|
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
|
||||||
STIMULUS: process
|
STIMULUS: process
|
||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
|
-- for i in 0 to instr_name_array'length-1 loop
|
||||||
|
-- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
|
||||||
|
-- end loop;
|
||||||
|
|
||||||
wait for 3*CLK_PERIOD;
|
wait for 3*CLK_PERIOD;
|
||||||
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
||||||
rst <= '0';
|
rst <= '0';
|
||||||
|
wait for 2*CLK_PERIOD;
|
||||||
|
|
||||||
|
-- assert false report "Test finished" severity error;
|
||||||
wait;
|
wait;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@@ -1,20 +0,0 @@
|
|||||||
vhdl work "../../src/core/mips_types.vhd"
|
|
||||||
vhdl work "../../../../misc/dpram_2w2r.vhd"
|
|
||||||
vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
|
|
||||||
vhdl work "../../../../misc/dpram_1w1r.vhd"
|
|
||||||
vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
|
|
||||||
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
|
||||||
vhdl work "../../src/core/mips_instr.vhd"
|
|
||||||
vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
|
|
||||||
vhdl work "../../src/core/mips_shifter.vhd"
|
|
||||||
vhdl work "../../src/core/mips_reg.vhd"
|
|
||||||
vhdl work "../../src/core/mips_muldiv.vhd"
|
|
||||||
vhdl work "../../src/core/mips_idecode_rom.vhd"
|
|
||||||
vhdl work "../../src/core/mips_icache.vhd"
|
|
||||||
vhdl work "../../src/core/mips_dcache.vhd"
|
|
||||||
vhdl work "../../src/core/mips_cop.vhd"
|
|
||||||
vhdl work "../../src/core/mips_bcu.vhd"
|
|
||||||
vhdl work "../../src/core/mips_alu.vhd"
|
|
||||||
vhdl work "../../src/core/mips_pipeline.vhd"
|
|
||||||
vhdl work "../../src/core/mips_biu.vhd"
|
|
||||||
vhdl work "../../src/core/mips_top.vhd"
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
|
|
||||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
|
|
||||||
@@ -1,5 +0,0 @@
|
|||||||
2008-10-26
|
|
||||||
- Optimierung: MUL32x32 primitive für Virtex-4
|
|
||||||
- External COP 1..3 interface
|
|
||||||
- FPU (COP1)
|
|
||||||
- MMU
|
|
||||||
@@ -1,17 +1,8 @@
|
|||||||
CFLAGS=-O2
|
all: ramgen romgen
|
||||||
|
|
||||||
CC=gcc
|
ramgen: src/ramgen.c
|
||||||
|
gcc -o ./ramgen.exe src/ramgen.c
|
||||||
all: romgen ramgen flashgen
|
|
||||||
|
romgen: src/romgen.c
|
||||||
romgen: ./src/romgen.c
|
gcc -o ./romgen.exe src/romgen.c
|
||||||
$(CC) $(CFLAGS) ./src/romgen.c -o ./romgen
|
|
||||||
|
|
||||||
ramgen: ./src/ramgen.c
|
|
||||||
$(CC) $(CFLAGS) ./src/ramgen.c -o ./ramgen
|
|
||||||
|
|
||||||
flashgen: ./src/flashgen.c
|
|
||||||
$(CC) $(CFLAGS) ./src/flashgen.c -o ./flashgen
|
|
||||||
|
|
||||||
clean:
|
|
||||||
rm -rf romgen* ramgen* flashgen*
|
|
||||||
@@ -0,0 +1,46 @@
|
|||||||
|
#!/usr/bin/env ruby
|
||||||
|
|
||||||
|
# ----------------------------------------------------------------------
|
||||||
|
# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
# This file: Insertion of code fragments into templates
|
||||||
|
#
|
||||||
|
# Copyright (C) 2008 J. Ahrensfeld
|
||||||
|
#
|
||||||
|
# This program is free software: you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation, either version 3 of the License, or
|
||||||
|
# (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
#
|
||||||
|
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
#
|
||||||
|
# ---------------------------------------------------------------------
|
||||||
|
|
||||||
|
arg = $*
|
||||||
|
rom_filename = arg[0].to_s
|
||||||
|
tpl_filename = arg[1].to_s
|
||||||
|
|
||||||
|
subst_pattern = "ROM_INSERT_HERE"
|
||||||
|
|
||||||
|
# --------------------------------------------------------
|
||||||
|
# Open file
|
||||||
|
# --------------------------------------------------------
|
||||||
|
romfile = File.open(rom_filename, "r")
|
||||||
|
tplfile = File.open(tpl_filename, "r")
|
||||||
|
re = Regexp.new(subst_pattern)
|
||||||
|
|
||||||
|
while (line = tplfile.gets)
|
||||||
|
puts line
|
||||||
|
line.scan(re).each do |word|
|
||||||
|
romfile.each do |raw_line|
|
||||||
|
puts raw_line
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
@@ -1,6 +1,6 @@
|
|||||||
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
||||||
-- Project: MIPS System controller
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
-- This file:
|
-- This file: The ROM file for use in your VHDL design
|
||||||
--
|
--
|
||||||
-- Copyright (C) 2008 J. Ahrensfeld
|
-- Copyright (C) 2008 J. Ahrensfeld
|
||||||
--
|
--
|
||||||
@@ -21,40 +21,9 @@
|
|||||||
--
|
--
|
||||||
--------------------------------------------------------------------------
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
library IEEE;
|
LIBRARY ieee;
|
||||||
USE IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
USE IEEE.NUMERIC_STD.ALL;
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
use work.async_types.all;
|
-- ROM_INSERT_HERE
|
||||||
|
|
||||||
package async_defs is
|
|
||||||
|
|
||||||
constant ts_flash : async_timespec_t :=
|
|
||||||
(
|
|
||||||
ncyc_access => 1,
|
|
||||||
ncyc_pulse_rd => 12,
|
|
||||||
ncyc_pulse_wr => 7,
|
|
||||||
ncyc_cs_hold => 1,
|
|
||||||
ncyc_release => 1,
|
|
||||||
ncyc_pulse_rst => 8,
|
|
||||||
pol_cs => '0',
|
|
||||||
pol_oe => '0',
|
|
||||||
pol_we => '0',
|
|
||||||
pol_rst => '0'
|
|
||||||
);
|
|
||||||
|
|
||||||
constant ts_sram : async_timespec_t :=
|
|
||||||
(
|
|
||||||
ncyc_access => 1,
|
|
||||||
ncyc_pulse_rd => 12,
|
|
||||||
ncyc_pulse_wr => 7,
|
|
||||||
ncyc_cs_hold => 1,
|
|
||||||
ncyc_release => 1,
|
|
||||||
ncyc_pulse_rst => 8,
|
|
||||||
pol_cs => '0',
|
|
||||||
pol_oe => '0',
|
|
||||||
pol_we => '0',
|
|
||||||
pol_rst => '0'
|
|
||||||
);
|
|
||||||
|
|
||||||
end async_defs;
|
|
||||||
@@ -0,0 +1,147 @@
|
|||||||
|
-------------------------------------------------------------------------
|
||||||
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||||
|
-- This file: loadable ROM
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2008 J. Ahrensfeld
|
||||||
|
--
|
||||||
|
-- This program is free software: you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation, either version 3 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
-- You should have received a copy of the GNU General Public License
|
||||||
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
--
|
||||||
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
--
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VComponents.all;
|
||||||
|
|
||||||
|
ENTITY irom IS
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
addr : in inst_addr_t;
|
||||||
|
dout : out inst_t
|
||||||
|
);
|
||||||
|
|
||||||
|
END irom;
|
||||||
|
|
||||||
|
ARCHITECTURE loadable OF irom IS
|
||||||
|
|
||||||
|
-- JASM_ROM_INSERT_HERE
|
||||||
|
|
||||||
|
signal jtag_ld_clk : STD_LOGIC;
|
||||||
|
signal jtag_ld_we : STD_LOGIC;
|
||||||
|
signal jtag_ld_addr : unsigned (15 downto 0);
|
||||||
|
signal jtag_ld_dout : unsigned (31 downto 0);
|
||||||
|
signal jtag_ld_din : unsigned (31 downto 0);
|
||||||
|
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||||
|
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||||
|
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||||
|
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
-- Virtex-4: JTAG Loader
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
i00_BUFG : BUFG
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
O => bs_clk1,
|
||||||
|
I => bs_clk0
|
||||||
|
);
|
||||||
|
|
||||||
|
i01_BUFG : BUFG
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
O => bs_update1,
|
||||||
|
I => bs_update0
|
||||||
|
);
|
||||||
|
|
||||||
|
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
||||||
|
generic map
|
||||||
|
(
|
||||||
|
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||||
|
)
|
||||||
|
port map
|
||||||
|
(
|
||||||
|
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||||
|
DRCK => bs_clk0, -- Data register output for USER functions
|
||||||
|
RESET => bs_rst, -- Reset output from TAP controller
|
||||||
|
SEL => bs_sel, -- USER active output
|
||||||
|
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||||
|
TDI => bs_tdi, -- TDI output from TAP controller
|
||||||
|
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||||
|
TDO => bs_tdo -- Data input for USER function
|
||||||
|
);
|
||||||
|
|
||||||
|
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
|
||||||
|
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
|
||||||
|
jtag_ld_clk <= bs_update1;
|
||||||
|
jtag_ld_we <= bs_sel;
|
||||||
|
|
||||||
|
sipo:
|
||||||
|
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||||
|
begin
|
||||||
|
if bs_rst = '1' then
|
||||||
|
user_regi <= (others => '0');
|
||||||
|
elsif rising_edge(bs_clk1) then
|
||||||
|
if bs_shift = '1' then
|
||||||
|
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
piso:
|
||||||
|
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||||
|
begin
|
||||||
|
bs_tdo <= user_rego(0);
|
||||||
|
if bs_rst = '1' then
|
||||||
|
user_rego <= (others => '0');
|
||||||
|
elsif rising_edge(bs_clk1) then
|
||||||
|
if bs_shift = '1' then
|
||||||
|
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||||
|
else
|
||||||
|
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
|
||||||
|
-- user_rego <= id;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
PROM_WRITE:
|
||||||
|
process(jtag_ld_clk, jtag_ld_we)
|
||||||
|
begin
|
||||||
|
if rising_edge(jtag_ld_clk) then
|
||||||
|
if jtag_ld_we = '1' then
|
||||||
|
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||||
|
else
|
||||||
|
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
-- ROM Read/Write
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
PROM_READ:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
dout <= imem_rom(to_integer(addr));
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--------------------------------------------------------------------------
|
||||||
|
end loadable;
|
||||||
@@ -0,0 +1,51 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
# ----------------------------------------------------------------------
|
||||||
|
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
# This file: rom-file generation for cpu_core
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
#
|
||||||
|
# This program is free software: you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation, either version 3 of the License, or
|
||||||
|
# (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
#
|
||||||
|
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
#
|
||||||
|
# ---------------------------------------------------------------------
|
||||||
|
# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make.sh,v 1.1 2008-08-25 08:29:55 Jens Exp $
|
||||||
|
# ----------------------------------------------------------------------
|
||||||
|
TARGET=$2
|
||||||
|
DSTDIR=$1
|
||||||
|
|
||||||
|
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||||
|
|
||||||
|
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||||
|
|
||||||
|
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||||
|
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||||
|
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||||
|
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||||
|
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||||
|
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||||
|
|
||||||
|
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||||
|
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||||
|
|
||||||
|
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||||
|
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||||
|
|
||||||
|
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||||
|
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||||
|
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||||
|
|
||||||
|
rm -f *.snip
|
||||||
@@ -0,0 +1,61 @@
|
|||||||
|
# ----------------------------------------------------------------------
|
||||||
|
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||||
|
# This file: The ROM file for upload to target over JTAG
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007 J. Ahrensfeld
|
||||||
|
#
|
||||||
|
# This program is free software: you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation, either version 3 of the License, or
|
||||||
|
# (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
#
|
||||||
|
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||||
|
#
|
||||||
|
# ---------------------------------------------------------------------
|
||||||
|
|
||||||
|
# ---------------------------------------------------------------------
|
||||||
|
# For Chipscope 9.1
|
||||||
|
# ---------------------------------------------------------------------
|
||||||
|
# Source JTAG/TCL frame work
|
||||||
|
cd $env(CHIPSCOPE)\\bin\\nt
|
||||||
|
source csejtag.tcl
|
||||||
|
|
||||||
|
namespace import ::chipscope::*
|
||||||
|
|
||||||
|
# Platform USB Cable
|
||||||
|
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||||
|
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||||
|
|
||||||
|
# Create session
|
||||||
|
set handle [::chipscope::csejtag_session create 0]
|
||||||
|
|
||||||
|
# Open JTAG and lock
|
||||||
|
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||||
|
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||||
|
|
||||||
|
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||||
|
|
||||||
|
# Get Device ID
|
||||||
|
set devtype "Virtex-4SX"
|
||||||
|
set devid 2
|
||||||
|
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||||
|
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||||
|
|
||||||
|
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||||
|
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||||
|
|
||||||
|
# Write Program
|
||||||
|
# JASM_ROM_INSERT_HERE
|
||||||
|
|
||||||
|
::chipscope::csejtag_target unlock $handle
|
||||||
|
::chipscope::csejtag_target close $handle
|
||||||
|
::chipscope::csejtag_session destroy $handle
|
||||||
|
exit
|
||||||
@@ -1,117 +0,0 @@
|
|||||||
#include <stdio.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <math.h>
|
|
||||||
|
|
||||||
#define INT8 char
|
|
||||||
#define INT16 short
|
|
||||||
#define INT32 long
|
|
||||||
#define UINT8 unsigned char
|
|
||||||
#define UINT16 unsigned short
|
|
||||||
#define UINT32 unsigned long
|
|
||||||
#define INT int
|
|
||||||
#define UINT unsigned int
|
|
||||||
#define FLOAT32 float
|
|
||||||
#define FLOAT64 double
|
|
||||||
|
|
||||||
#define SDRAM_BASE 0x40000000
|
|
||||||
#define FLASH_OFFSET 0x00000000
|
|
||||||
|
|
||||||
// --------------------------------------------------------------
|
|
||||||
typedef struct _sflash_img_hdr_t
|
|
||||||
{
|
|
||||||
UINT8 magic[4];
|
|
||||||
UINT32 target_addr;
|
|
||||||
UINT32 img_offset;
|
|
||||||
UINT32 img_size;
|
|
||||||
UINT32 hdr_next;
|
|
||||||
UINT8 img_name[128];
|
|
||||||
UINT8 res[108];
|
|
||||||
|
|
||||||
} flash_img_hdr_t;
|
|
||||||
|
|
||||||
// --------------------------------------------------------------
|
|
||||||
void basename(char *pSrc, char *pDst)
|
|
||||||
{
|
|
||||||
int i, size;
|
|
||||||
|
|
||||||
size = strlen(pSrc);
|
|
||||||
|
|
||||||
while(pSrc[size] != '.')
|
|
||||||
size--;
|
|
||||||
|
|
||||||
for (i=0; i < size; i++)
|
|
||||||
pDst[i] = pSrc[i];
|
|
||||||
|
|
||||||
pDst[i] = 0;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
// --------------------------------------------------------------
|
|
||||||
int main(int argc, char *argv[])
|
|
||||||
{
|
|
||||||
char *pFilenameIn;
|
|
||||||
char name_flash[1024];
|
|
||||||
char name_prj[1024];
|
|
||||||
char *pBuf;
|
|
||||||
flash_img_hdr_t img_hdr = {0};
|
|
||||||
|
|
||||||
FILE *pFile;
|
|
||||||
int filesize;
|
|
||||||
long start, end;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (argc < 2)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Usage: flashgen <input file>\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
pFilenameIn = argv[1];
|
|
||||||
pFile = fopen(pFilenameIn, "rb");
|
|
||||||
if (!pFile)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
basename(pFilenameIn, name_prj);
|
|
||||||
sprintf(name_flash, "%s.flash.bin", name_prj);
|
|
||||||
|
|
||||||
// determine filesize
|
|
||||||
fseek(pFile, 0, SEEK_SET);
|
|
||||||
start = ftell(pFile);
|
|
||||||
fseek(pFile, 0, SEEK_END);
|
|
||||||
end = ftell(pFile);
|
|
||||||
fseek(pFile, 0, SEEK_SET);
|
|
||||||
filesize = (end-start);
|
|
||||||
|
|
||||||
pBuf = (char*)malloc(filesize);
|
|
||||||
fread(pBuf, 1, filesize, pFile);
|
|
||||||
|
|
||||||
fclose(pFile);
|
|
||||||
|
|
||||||
pFile = fopen(name_flash, "wb");
|
|
||||||
if (!pFile)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", name_flash);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
img_hdr.magic[0] = 'J';
|
|
||||||
img_hdr.magic[1] = 'F';
|
|
||||||
img_hdr.magic[2] = 'I';
|
|
||||||
img_hdr.magic[3] = '1';
|
|
||||||
img_hdr.target_addr = SDRAM_BASE;
|
|
||||||
img_hdr.img_size = filesize;
|
|
||||||
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
|
|
||||||
img_hdr.hdr_next = FLASH_OFFSET;
|
|
||||||
|
|
||||||
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
|
|
||||||
fwrite(pBuf, 1, filesize, pFile);
|
|
||||||
|
|
||||||
fclose(pFile);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -24,260 +24,6 @@ void basename(char *pSrc, char *pDst)
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
|
||||||
{
|
|
||||||
FILE *pFileIn, *pFileOut;
|
|
||||||
long start, end;
|
|
||||||
int i, word, filesize, romsize;
|
|
||||||
|
|
||||||
pFileIn = fopen(pFilenameIn, "rb");
|
|
||||||
if (!pFileIn)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
pFileOut = fopen(pFilenameOut, "wb");
|
|
||||||
if (!pFileOut)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
fseek(pFileIn, 0, SEEK_SET);
|
|
||||||
start = ftell(pFileIn);
|
|
||||||
fseek(pFileIn, 0, SEEK_END);
|
|
||||||
end = ftell(pFileIn);
|
|
||||||
fseek(pFileIn, 0, SEEK_SET);
|
|
||||||
|
|
||||||
filesize = (end-start);
|
|
||||||
romsize = (int)pow(2, nbits_addr+2);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Header
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
|
||||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
|
||||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\tPort\n");
|
|
||||||
fprintf(pFileOut, "\t(\n");
|
|
||||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
|
|
||||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\t);\n");
|
|
||||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
|
|
||||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
|
|
||||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
|
|
||||||
fprintf(pFileOut, "\t(\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// ROM part
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
for (i=0; i < filesize; i += sizeof(int))
|
|
||||||
{
|
|
||||||
fread(&word, 1, sizeof(int), pFileIn);
|
|
||||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
|
||||||
if (i < (romsize-sizeof(int)))
|
|
||||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
|
||||||
else
|
|
||||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
|
||||||
}
|
|
||||||
word = 0;
|
|
||||||
for (; i < romsize; i += sizeof(int))
|
|
||||||
{
|
|
||||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
|
||||||
if (i < (romsize-sizeof(int)))
|
|
||||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
|
||||||
else
|
|
||||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
|
||||||
}
|
|
||||||
fprintf(pFileOut, "\t);\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Trailer
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
|
|
||||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
|
||||||
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
|
|
||||||
fprintf(pFileOut, "\tbegin\n");
|
|
||||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
|
|
||||||
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
|
|
||||||
fprintf(pFileOut, "\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\tend process;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
|
||||||
{
|
|
||||||
FILE *pFileIn, *pFileOut;
|
|
||||||
long start, end;
|
|
||||||
int i, word, filesize, romsize;
|
|
||||||
|
|
||||||
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
|
|
||||||
|
|
||||||
pFileIn = fopen(pFilenameIn, "rb");
|
|
||||||
if (!pFileIn)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
pFileOut = fopen(pFilenameOut, "wb");
|
|
||||||
if (!pFileOut)
|
|
||||||
{
|
|
||||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
fseek(pFileIn, 0, SEEK_SET);
|
|
||||||
start = ftell(pFileIn);
|
|
||||||
fseek(pFileIn, 0, SEEK_END);
|
|
||||||
end = ftell(pFileIn);
|
|
||||||
fseek(pFileIn, 0, SEEK_SET);
|
|
||||||
|
|
||||||
filesize = (end-start);
|
|
||||||
romsize = (int)pow(2, nbits_addr+2);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Header
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
|
||||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
|
||||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "library UNISIM;\n");
|
|
||||||
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\tPort\n");
|
|
||||||
fprintf(pFileOut, "\t(\n");
|
|
||||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\t);\n");
|
|
||||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
|
|
||||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
|
|
||||||
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
|
|
||||||
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
|
||||||
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
|
|
||||||
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
|
|
||||||
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
|
|
||||||
fprintf(pFileOut, "\t(\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// ROM part
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
for (i=0; i < filesize; i += sizeof(int))
|
|
||||||
{
|
|
||||||
fread(&word, 1, sizeof(int), pFileIn);
|
|
||||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
|
||||||
if (i < (romsize-sizeof(int)))
|
|
||||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
|
||||||
else
|
|
||||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
|
||||||
}
|
|
||||||
word = 0;
|
|
||||||
for (; i < romsize; i += sizeof(int))
|
|
||||||
{
|
|
||||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
|
||||||
if (i < (romsize-sizeof(int)))
|
|
||||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
|
||||||
else
|
|
||||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
|
||||||
}
|
|
||||||
fprintf(pFileOut, "\t);\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
|
||||||
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
|
||||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
|
||||||
fprintf(pFileOut, "\tbegin\n");
|
|
||||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
|
||||||
fprintf(pFileOut, "\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\tend process;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Trailer
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
fputs(tpl, pFileOut);
|
|
||||||
|
|
||||||
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
|
|
||||||
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
|
|
||||||
fprintf(pFileOut, "\tbegin\n");
|
|
||||||
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
|
|
||||||
fprintf(pFileOut, "\t\t\telse\n");
|
|
||||||
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
|
|
||||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\t\tend if;\n");
|
|
||||||
fprintf(pFileOut, "\tend process;\n");
|
|
||||||
fprintf(pFileOut, "\n");
|
|
||||||
|
|
||||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||||
{
|
{
|
||||||
FILE *pFileIn, *pFileOut;
|
FILE *pFileIn, *pFileOut;
|
||||||
@@ -351,8 +97,6 @@ int main(int argc, char *argv[])
|
|||||||
char *pFilenameIn;
|
char *pFilenameIn;
|
||||||
char name_prj[1024];
|
char name_prj[1024];
|
||||||
char name_rom_tcl[1024];
|
char name_rom_tcl[1024];
|
||||||
char name_rom[1024];
|
|
||||||
char name_rom_v4ld[1024];
|
|
||||||
|
|
||||||
FILE *pFileIn;
|
FILE *pFileIn;
|
||||||
int filesize, romsize, nbits_addr, nbits_data;
|
int filesize, romsize, nbits_addr, nbits_data;
|
||||||
@@ -361,7 +105,7 @@ int main(int argc, char *argv[])
|
|||||||
|
|
||||||
if (argc < 2)
|
if (argc < 2)
|
||||||
{
|
{
|
||||||
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
|
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -371,12 +115,8 @@ int main(int argc, char *argv[])
|
|||||||
|
|
||||||
|
|
||||||
basename(pFilenameIn, name_prj);
|
basename(pFilenameIn, name_prj);
|
||||||
sprintf(name_rom, "%s.vhd", name_prj);
|
|
||||||
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
|
|
||||||
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
||||||
|
|
||||||
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
|
||||||
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
|
||||||
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -4,7 +4,7 @@
|
|||||||
#include <math.h>
|
#include <math.h>
|
||||||
|
|
||||||
#define ARCH_NAME "data"
|
#define ARCH_NAME "data"
|
||||||
#define ENT_NAME "rom"
|
#define ENT_NAME "icache"
|
||||||
#define JTAG_ADDR_WIDTH 16
|
#define JTAG_ADDR_WIDTH 16
|
||||||
|
|
||||||
// --------------------------------------------------------------
|
// --------------------------------------------------------------
|
||||||
|
|||||||
Reference in New Issue
Block a user