jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: jens/vhdl:EMAC_R01
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
..
compare: jens/vhdl:EMAC_R2
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
1 Commits
EMAC_R01 .. EMAC_R2
Author SHA1 Message Date
jens 23afdea302 This commit was manufactured by cvs2svn to create tag 'EMAC_R2'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R2@874 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-07 18:44:43 +00:00
26 changed files with 2331 additions and 1564 deletions
Expand all files Collapse all files
lib/FIFO/src/.directory_history
-8
View File
@@ -1,8 +0,0 @@
VHDL/lib/FIFO/src/async_fifo_ctrl.vhd
VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd
VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
lib/FIFO/src/async_fifo_ctrl.vhd
-248
View File
@@ -1,248 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
LIBRARY WORK;
USE WORK.FIFO_CTRL_PKG.ALL;
entity fifo_async_ctrl is
Generic
(
addr_width : integer := 3;
almost_full_thresh : integer := 6;
almost_empty_thresh : integer := 2
);
Port
(
rst : in STD_LOGIC;
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
winc : in STD_LOGIC;
rinc : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
fifo_pre_empty : out STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC
);
end fifo_async_ctrl;
architecture Behavioral of fifo_async_ctrl is
signal gcnt_w : unsigned (addr_width downto 0);
signal gcnt2_w : unsigned (addr_width downto 0);
signal bcnt2_aw : unsigned (addr_width downto 0);
signal bcnt_w : unsigned (addr_width downto 0);
signal gnxt_w : unsigned (addr_width downto 0);
signal bnxt_w : unsigned (addr_width downto 0);
signal gcnt_r : unsigned (addr_width downto 0);
signal gcnt2_r : unsigned (addr_width downto 0);
signal bcnt2_ar : unsigned (addr_width downto 0);
signal bcnt_r : unsigned (addr_width downto 0);
signal gnxt_r : unsigned (addr_width downto 0);
signal bnxt_r : unsigned (addr_width downto 0);
signal pre_empty, pre_full : std_logic;
signal full, empty : std_logic;
-- synthesis translate_off
signal diffw : signed (addr_width downto 0);
signal diffr : signed (addr_width downto 0);
-- synthesis translate_on
begin
ptr_w <= bcnt_w(addr_width-1 downto 0);
ptr_r <= bnxt_r(addr_width-1 downto 0);
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
fifo_pre_empty <= pre_empty;
proc_write_inhibit:
process(rst, clk_w)
begin
if rst = '1' then
full <= '0';
elsif rising_edge(clk_w) then
full <= pre_full;
end if;
end process;
proc_read_inhibit:
process(rst, clk_r)
begin
if rst = '1' then
empty <= '1';
elsif rising_edge(clk_r) then
empty <= pre_empty;
end if;
end process;
proc_sync_grptr:
process(clk_w)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_w) then
gcnt2_r <= p2;
p2 := p1;
p1 := gcnt_r;
end if;
end process;
proc_ptr_gwptr:
process(clk_r)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_r) then
gcnt2_w <= p2;
p2 := p1;
p1 := gcnt_w;
end if;
end process;
proc_status_full:
process(gnxt_w, gcnt2_r)
begin
if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
pre_full <= '1';
else
pre_full <= '0';
end if;
end process;
proc_status_empty:
process(gnxt_r, gcnt2_w)
begin
if (gnxt_r = gcnt2_w) then
pre_empty <= '1';
else
pre_empty <= '0';
end if;
end process;
proc_sync_arptr:
process(clk_w)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_w) then
bcnt2_ar <= p2;
p2 := p1;
p1 := bcnt_r;
end if;
end process;
proc_ptr_awptr:
process(clk_r)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_r) then
bcnt2_aw <= p2;
p2 := p1;
p1 := bcnt_w;
end if;
end process;
proc_status_almost_full:
process(rst, clk_w)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffw <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_afull <= '0';
diff := (others => '0');
elsif rising_edge(clk_w) then
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
end if;
end process;
proc_status_almost_empty:
process(rst, clk_r)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffr <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_aempty <= '1';
diff := (others => '0');
elsif rising_edge(clk_r) then
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
end if;
end process;
inst_gray_counter_w : entity work.gray_counter
generic map
(
width => addr_width+1,
init_value => 0
)
port map
(
rst => rst,
clk => clk_w,
ce => winc,
bcnt => bcnt_w,
bnxt => bnxt_w,
gcnt => gcnt_w,
gnxt => gnxt_w
);
inst_gray_counter_r : entity work.gray_counter
generic map
(
width => addr_width+1,
init_value => 0
)
port map
(
rst => rst,
clk => clk_r,
ce => rinc,
bcnt => bcnt_r,
bnxt => bnxt_r,
gcnt => gcnt_r,
gnxt => gnxt_r
);
end Behavioral;
lib/FIFO/src/fifo_async.vhd
-124
View File
@@ -1,124 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_async is
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
(
rst : in STD_LOGIC;
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
end fifo_async;
architecture Behavioral of fifo_async is
signal mem_wr_en : STD_LOGIC;
signal mem_rd_en : STD_LOGIC;
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : std_logic;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
begin
fifo_full <= full;
fifo_empty <= empty;
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
rinc <= (re and not empty) when allow_empty_reads = false else re;
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
inst_fifo_async_ctrl: entity work.fifo_async_ctrl
GENERIC MAP
(
addr_width => addr_width,
almost_full_thresh => almost_full_thresh,
almost_empty_thresh => almost_empty_thresh
)
PORT MAP
(
rst => rst,
clk_w => clk_w,
clk_r => clk_r,
winc => mem_wr_en,
rinc => rinc,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
fifo_aempty => fifo_aempty
);
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk_w,
clkb => clk_r,
en_a => '1',
en_b => mem_rd_en,
we_a => mem_wr_en,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/FIFO/src/fifo_ctrl_pkg.vhd
-67
View File
@@ -1,67 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
package fifo_ctrl_pkg is
-- Constants
-- Types
-- Functions
function bin2gray(xb : unsigned) return unsigned;
function gray2bin(xg : unsigned) return unsigned;
end fifo_ctrl_pkg;
package body fifo_ctrl_pkg is
function bin2gray(xb : unsigned) return unsigned is
variable xg : unsigned(xb'left downto xb'right);
begin
xg(xg'left) := xb(xb'left);
for i in 1 to xb'left loop
xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
end loop;
return xg;
end bin2gray;
function gray2bin(xg : unsigned) return unsigned is
variable xb : unsigned(xg'left downto xg'right);
begin
xb(xb'left) := xg(xg'left);
for i in 1 to xg'left loop
xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
end loop;
return xb;
end gray2bin;
end fifo_ctrl_pkg;
lib/FIFO/src/fifo_sync.vhd
-123
View File
@@ -1,123 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_sync is
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4;
allow_full_writes : boolean := false;
allow_empty_reads : boolean := false;
do_last_read_update : boolean := true
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
end fifo_sync;
architecture Behavioral of fifo_sync is
signal mem_wr_en : STD_LOGIC;
signal mem_rd_en : STD_LOGIC;
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : std_logic;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
signal rinc : std_logic;
begin
fifo_full <= full;
fifo_empty <= empty;
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
rinc <= (re and not empty) when allow_empty_reads = false else re;
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
GENERIC MAP
(
addr_width => addr_width,
almost_full_thresh => almost_full_thresh,
almost_empty_thresh => almost_empty_thresh
)
PORT MAP
(
rst => rst,
clk => clk,
winc => mem_wr_en,
rinc => rinc,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => fifo_afull,
fifo_aempty => fifo_aempty
);
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk,
clkb => clk,
en_a => '1',
en_b => mem_rd_en,
we_a => mem_wr_en,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/FIFO/src/gray_counter.vhd
-84
View File
@@ -1,84 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
LIBRARY WORK;
USE WORK.FIFO_CTRL_PKG.ALL;
entity gray_counter is
Generic (
width : natural := 3;
init_value : natural := 0
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
bcnt : out unsigned (width-1 downto 0);
bnxt : out unsigned (width-1 downto 0);
gcnt : out unsigned (width-1 downto 0);
gnxt : out unsigned (width-1 downto 0)
);
end gray_counter;
architecture Behavioral of gray_counter is
signal cntg : unsigned (width-1 downto 0);
signal cntb : unsigned (width-1 downto 0);
signal nxtb : unsigned (width-1 downto 0);
signal nxtg : unsigned (width-1 downto 0);
begin
bnxt <= nxtb;
gnxt <= nxtg;
bcnt <= cntb;
gcnt <= cntg;
process(rst, clk, ce, cntb, nxtb)
begin
if rst = '1' then
cntb <= to_unsigned(init_value, width);
nxtb <= to_unsigned(init_value, width);
nxtg <= to_unsigned(init_value, width);
cntg <= to_unsigned(init_value, width);
else
if rising_edge(clk) then
cntg <= nxtg;
cntb <= nxtb;
end if;
nxtg <= bin2gray(nxtb);
nxtb <= cntb;
if ce = '1' then
nxtb <= cntb + 1;
end if;
end if;
end process;
end Behavioral;
lib/FIFO/src/sync_fifo_ctrl.vhd
-198
View File
@@ -1,198 +0,0 @@
-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity fifo_sync_ctrl is
Generic
(
addr_width : integer := 3;
almost_full_thresh : integer := 6;
almost_empty_thresh : integer := 2
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
winc : in STD_LOGIC;
rinc : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
fifo_pre_empty : out STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC
);
end fifo_sync_ctrl;
architecture Behavioral of fifo_sync_ctrl is
signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
signal empty, full : std_logic;
signal pre_empty, pre_full : std_logic;
signal was_write : std_logic;
signal diff : unsigned (addr_width downto 0);
begin
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
fifo_pre_empty <= pre_empty;
proc_diff_gen:
process(rst, clk)
begin
if rst = '1' then
diff <= (others => '0');
elsif rising_edge(clk) then
if winc = '1' and rinc = '0' then
diff <= diff + 1;
elsif winc = '0' and rinc = '1' then
diff <= diff - 1;
end if;
end if;
end process;
proc_status_almost_full:
process(rst, clk)
begin
if rst = '1' then
fifo_afull <= '0';
elsif rising_edge(clk) then
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
end if;
end process;
proc_status_almost_empty:
process(rst, clk)
begin
if rst = '1' then
fifo_aempty <= '1';
elsif rising_edge(clk) then
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
end if;
end process;
proc_full_reg:
process(rst, clk)
begin
if rst = '1' then
full <= '0';
elsif rising_edge(clk) then
full <= pre_full;
end if;
end process;
proc_empty_reg:
process(rst, clk)
begin
if rst = '1' then
empty <= '1';
elsif rising_edge(clk) then
empty <= pre_empty;
end if;
end process;
proc_status_w:
process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
begin
if (pW_next = pR) and (winc = '1' or was_write = '1') then
pre_full <= '1';
else
pre_full <= '0';
end if;
if (pR_next = pW) and (rinc = '1' or was_write = '0') then
pre_empty <= '1';
else
pre_empty <= '0';
end if;
end process;
proc_flag_write:
process(rst, clk)
begin
if rst = '1' then
was_write <= '0';
elsif rising_edge(clk) then
if winc = '1' then
was_write <= '1';
elsif rinc = '1' then
was_write <= '0';
end if;
end if;
end process;
proc_ptr_w:
process(rst, clk, pW, winc)
begin
if rst = '1' then
pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if winc = '1' then
pW <= pW_next;
end if;
end if;
pW_next <= pW;
if winc = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process;
proc_ptr_r:
process(rst, clk, pR_next, pR, rinc)
begin
if rst = '1' then
pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if rinc = '1' then
pR <= pR_next;
end if;
end if;
pR_next <= pR;
if rinc = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;
end process;
end Behavioral;
lib/emac/emac_jb.vhd
+657
View File
@@ -0,0 +1,657 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all;
ENTITY emac_jb IS
Generic
(
f_sysclk : real := 100.0;
TX_RAM_SIZE : natural := 2048
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
INT_O : out STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
mii_rx_clk : in STD_LOGIC;
mii_rx_dv : in STD_LOGIC;
mii_rx_er : in STD_LOGIC;
mii_rx : in unsigned(7 downto 0);
mii_tx_clk : in STD_LOGIC;
mii_tx_en : out STD_LOGIC;
mii_tx_er : out STD_LOGIC;
mii_tx : out unsigned(7 downto 0);
mii_gtx_clk : out STD_LOGIC;
mii_crs : in STD_LOGIC;
mii_col : in STD_LOGIC
);
END emac_jb;
ARCHITECTURE behavior OF emac_jb IS
constant TX_RAM_ADDR_WIDTH : natural := NextExpBaseTwo(TX_RAM_SIZE);
subtype word_ptr_t is unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
-- Signals for EMAC connections
signal tx_fifo_din : unsigned(35 downto 0);
signal tx_fifo_dout : unsigned(35 downto 0);
signal tx_fifo_we : std_logic;
signal tx_fifo_re : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_full : std_logic;
signal rx_int_en : std_logic;
signal tx_int_en : std_logic;
signal irq_rx : std_logic;
signal irq_tx : std_logic;
signal tx_err : std_logic;
signal tx_flush_en : std_logic;
signal tx_flush_rdy : std_logic;
signal tx_flush_ptr_set : std_logic;
signal tx_commit_en : std_logic;
signal tx_flush_ptr : word_ptr_t;
signal host_data_we : std_logic;
signal host_data_reg : unsigned(31 downto 0);
signal host_tx_size : unsigned(15 downto 0);
signal tx_fill_size : word_ptr_t;
signal tx_fill_cnt : word_ptr_t;
signal tx_fill_ptr : word_ptr_t;
signal tx_fill_rdy : std_logic;
signal tx_fill_cnt_set : std_logic;
signal tx_fill_cnt_adv : std_logic;
signal tx_fill_ptr_set : std_logic;
signal tx_fill_ptr_adv : std_logic;
signal tx_alloc_OK : std_logic;
signal tx_alloc_req_en : std_logic;
signal tx_alloc_req : std_logic;
signal tx_alloc_ack : std_logic;
signal tx_nwords_free : word_ptr_t;
signal tx_alloc_base : word_ptr_t;
signal tx_alloc_size : word_ptr_t;
signal tx_alloc_en : std_logic;
signal tx_free_en : std_logic;
signal tx_uncommit_en : std_logic;
signal tx_fill_remain : unsigned(1 downto 0);
signal tx_xfer_size : word_ptr_t;
signal tx_xfer_ptr : word_ptr_t;
signal tx_xfer_cnt : word_ptr_t;
signal tx_xfer_en : std_logic;
signal tx_xfer_ptr_set : std_logic;
signal tx_xfer_ptr_adv : std_logic;
signal tx_xfer_cnt_set : std_logic;
signal tx_xfer_cnt_adv : std_logic;
signal tx_xfer_rdy : std_logic;
signal xfer_tag : unsigned(3 downto 0);
signal xfer_remain : unsigned(1 downto 0);
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal tx_ram_en_a : std_logic;
signal tx_ram_we_a : std_logic;
signal tx_ram_addr_a : unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
signal tx_ram_din_a : unsigned(35 downto 0);
signal tx_ram_dout_a : unsigned(35 downto 0);
signal tx_ram_en_b : std_logic;
signal tx_ram_we_b : std_logic;
signal tx_ram_addr_b : unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
signal tx_ram_din_b : unsigned(35 downto 0);
signal tx_ram_dout_b : unsigned(35 downto 0);
signal piso_din_be : unsigned(3 downto 0);
signal piso_din_rdy : std_logic;
signal tx_data_vld : std_logic;
subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
signal inter_frame_gap_rdy : std_logic;
alias tx_ram_data_in_a is tx_ram_din_a(31 downto 0);
alias tx_ram_tag_in_a is tx_ram_din_a(35 downto 32);
alias tx_ram_data_out_a is tx_ram_dout_a(31 downto 0);
alias tx_ram_tag_out_a is tx_ram_dout_a(35 downto 32);
alias tx_ram_data_in_b is tx_ram_din_b(31 downto 0);
alias tx_ram_tag_in_b is tx_ram_din_b(35 downto 32);
alias tx_ram_data_out_b is tx_ram_dout_b(31 downto 0);
alias tx_ram_tag_out_b is tx_ram_dout_b(35 downto 32);
type host_tx_state_t is (host_tx_init, host_tx_flush, host_tx_idle, host_tx_alloc, host_tx_setup, host_tx_arm, host_tx_fill, host_tx_commit);
signal host_tx_s, host_tx_sn : host_tx_state_t;
type xfer_tx_state_t is (xfer_tx_init, xfer_tx_idle, xfer_tx_setup, xfer_wait, xfer_tx_active, xfer_tx_free);
signal xfer_tx_s, xfer_tx_sn : xfer_tx_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
(
"1111",
"0001",
"0011",
"0111"
);
begin
SRDY_O <= CYC_I;
INT_O <= irq_rx or irq_tx;
mii_gtx_clk <= '0';
mii_tx_er <= tx_err;
tx_ram_tag_in_b <= "0000";
tx_ram_en_b <= '1';
tx_ram_we_b <= tx_uncommit_en or tx_flush_en;
tx_ram_addr_b <= tx_flush_ptr when (tx_flush_en = '1' or tx_uncommit_en = '1') else tx_xfer_ptr;
xfer_tag <= tx_ram_tag_out_b;
tx_ram_en_a <= '1';
tx_ram_we_a <= tx_commit_en or tx_fill_cnt_adv;
tx_ram_tag_in_a <= tx_fill_remain & "01" when tx_commit_en = '1' else "0000";
tx_ram_data_in_a <= resize(tx_fill_size, 16) & resize(tx_alloc_base, 16) when tx_commit_en = '1' else host_data_reg;
tx_ram_addr_a <= tx_alloc_base when tx_commit_en = '1' else tx_fill_ptr;
piso_din_be <= (others => '1');
tx_fifo_re <= piso_din_rdy;
tx_data_vld <= not tx_fifo_empty;
tx_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
tx_fifo_din(31 downto 0) <= tx_ram_data_out_b;
------------------------------------------------------------------
host_tx_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
host_tx_s <= host_tx_init;
else
host_tx_s <= host_tx_sn;
end if;
end if;
end process;
host_tx_state:
process(host_tx_s, tx_flush_rdy, tx_alloc_req, tx_alloc_OK, tx_fill_rdy, host_data_we)
begin
tx_flush_en <= '0';
tx_flush_ptr_set <= '0';
tx_alloc_ack <= '0';
tx_fill_cnt_set <= '0';
tx_fill_cnt_adv <= '0';
tx_fill_ptr_set <= '0';
tx_fill_ptr_adv <= '0';
tx_commit_en <= '0';
tx_alloc_en <= '0';
host_tx_sn <= host_tx_s;
case host_tx_s is
when host_tx_init =>
tx_flush_ptr_set <= '1';
host_tx_sn <= host_tx_flush;
when host_tx_flush =>
tx_flush_en <= '1';
if tx_flush_rdy = '1' then
tx_flush_en <= '0';
host_tx_sn <= host_tx_idle;
end if;
when host_tx_idle =>
if tx_alloc_req = '1' then
host_tx_sn <= host_tx_alloc;
end if;
when host_tx_alloc =>
if tx_alloc_OK = '1' then
host_tx_sn <= host_tx_setup;
tx_alloc_ack <= '1';
end if;
when host_tx_setup =>
tx_fill_cnt_set <= '1';
tx_fill_ptr_set <= '1';
host_tx_sn <= host_tx_arm;
when host_tx_arm =>
tx_fill_ptr_adv <= '1';
tx_fill_cnt_adv <= '1';
host_tx_sn <= host_tx_fill;
when host_tx_fill =>
tx_fill_cnt_adv <= host_data_we;
tx_fill_ptr_adv <= not tx_fill_rdy and host_data_we;
if tx_alloc_req = '1' then
host_tx_sn <= host_tx_alloc;
elsif tx_fill_rdy = '1' then
host_tx_sn <= host_tx_commit;
end if;
when host_tx_commit =>
tx_commit_en <= '1';
tx_alloc_en <= '1';
host_tx_sn <= host_tx_idle;
when others =>
host_tx_sn <= host_tx_idle;
end case;
end process;
------------------------------------------------------------------
-- Allocation stuff
------------------------------------------------------------------
alloc_request_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
tx_alloc_req <= '0';
elsif tx_alloc_req_en = '1' and tx_alloc_req = '0' then
tx_alloc_req <= '1';
tx_fill_remain <= host_tx_size(1 downto 0);
tx_fill_size <= host_tx_size(word_ptr_t'left+2 downto 2);
if host_tx_size(1 downto 0) /= "00" then
tx_fill_size <= host_tx_size(word_ptr_t'left+2 downto 2) + 1;
end if;
elsif tx_alloc_ack = '1' then
tx_alloc_req <= '0';
tx_alloc_size <= tx_fill_size;
end if;
end if;
end process;
------------------------------------------------------------------
alloc_base_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
tx_alloc_base <= (others => '0');
elsif tx_commit_en = '1' then
tx_alloc_base <= tx_fill_ptr;
end if;
end if;
end process;
------------------------------------------------------------------
alloc_eval_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
tx_alloc_OK <= '0';
if tx_alloc_req = '1' then
if tx_fill_size < tx_nwords_free then
tx_alloc_OK <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------
tx_nwords_free_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
tx_nwords_free <= (others => '1');
elsif tx_alloc_en = '1' then
tx_nwords_free <= tx_nwords_free - tx_fill_size;
elsif tx_free_en = '1' then
tx_nwords_free <= tx_nwords_free + tx_xfer_size;
end if;
end if;
end process;
------------------------------------------------------------------
tx_flush_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '0' then
tx_flush_rdy <= '0';
if tx_flush_ptr_set = '1' then
tx_flush_ptr <= (others => '1');
elsif tx_xfer_ptr_set = '1' then
tx_flush_ptr <= tx_ram_data_out_b(tx_flush_ptr'left downto 0);
end if;
elsif tx_flush_ptr /= 0 then
tx_flush_ptr <= tx_flush_ptr - 1;
else
tx_flush_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
-- Fill stuff
------------------------------------------------------------------
tx_fill_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_fill_cnt_set = '1' then
tx_fill_rdy <= '0';
tx_fill_cnt <= tx_alloc_size;
elsif tx_fill_cnt_adv = '1' then
if tx_fill_cnt /= 0 then
tx_fill_cnt <= tx_fill_cnt - 1;
else
tx_fill_rdy <= '1';
end if;
end if;
end if;
end process;
tx_fill_pointer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_fill_ptr_set = '1' then
tx_fill_ptr <= tx_alloc_base;
elsif tx_fill_ptr_adv = '1' then
tx_fill_ptr <= tx_fill_ptr + 1;
end if;
end if;
end process;
------------------------------------------------------------------
-- Transfer stuff
------------------------------------------------------------------
xfer_tx_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
xfer_tx_s <= xfer_tx_init;
else
xfer_tx_s <= xfer_tx_sn;
end if;
end if;
end process;
xfer_tx_state:
process(xfer_tx_s, xfer_tag, xfer_odd, tx_xfer_rdy, inter_frame_gap_rdy, tx_alloc_en, tx_fifo_full)
begin
tx_xfer_cnt_set <= '0';
tx_xfer_cnt_adv <= '0';
tx_xfer_ptr_set <= '0';
tx_xfer_ptr_adv <= '0';
tx_xfer_en <= '0';
xfer_remain_en <= '0';
tx_free_en <= '0';
tx_uncommit_en <= '0';
xfer_tx_sn <= xfer_tx_s;
case xfer_tx_s is
when xfer_tx_init =>
xfer_tx_sn <= xfer_tx_idle;
when xfer_tx_idle =>
if xfer_tag(0) = '1' then
tx_xfer_ptr_set <= '1';
tx_xfer_cnt_set <= '1';
xfer_tx_sn <= xfer_wait;
end if;
when xfer_wait =>
if inter_frame_gap_rdy = '1' then
xfer_tx_sn <= xfer_tx_setup;
end if;
when xfer_tx_setup =>
tx_uncommit_en <= '1';
tx_xfer_ptr_adv <= '1';
tx_xfer_cnt_adv <= '1';
xfer_tx_sn <= xfer_tx_active;
when xfer_tx_active =>
tx_xfer_en <= '1';
tx_xfer_cnt_adv <= not tx_fifo_full;
tx_xfer_ptr_adv <= not tx_fifo_full;
if tx_xfer_rdy = '1' then
xfer_remain_en <= xfer_odd;
tx_xfer_en <= '0';
tx_xfer_cnt_adv <= '0';
tx_xfer_ptr_adv <= '0';
xfer_tx_sn <= xfer_tx_free;
end if;
when xfer_tx_free =>
tx_free_en <= not tx_alloc_en;
if tx_alloc_en = '0' then
xfer_tx_sn <= xfer_tx_idle;
end if;
when others =>
xfer_tx_sn <= xfer_tx_idle;
end case;
end process;
------------------------------------------------------------------
interframe_gap_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
inter_frame_gap_rdy <= '1';
elsif tx_fifo_empty = '0' then
inter_frame_gap_rdy <= '0';
inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
elsif inter_frame_gap_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
else
inter_frame_gap_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
tx_xfer_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_xfer_cnt_set = '1' then
tx_xfer_size <= (others => '0');
tx_xfer_rdy <= '0';
tx_xfer_cnt <= tx_ram_data_out_b(tx_xfer_ptr'left+16 downto 16);
elsif tx_xfer_cnt_adv = '1' then
if tx_xfer_cnt /= 0 then
tx_xfer_cnt <= tx_xfer_cnt - 1;
tx_xfer_size <= tx_xfer_size + 1;
else
tx_xfer_rdy <= '1';
end if;
end if;
end if;
end process;
tx_xfer_pointer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
tx_fifo_we <= tx_xfer_en;
if tx_xfer_ptr_set = '1' then
tx_xfer_ptr <= tx_ram_data_out_b(tx_xfer_ptr'left downto 0);
xfer_remain <= xfer_tag(3 downto 2);
xfer_odd <= '0';
if xfer_tag(3 downto 2) /= "00" then
xfer_odd <= '1';
end if;
elsif tx_xfer_ptr_adv = '1' then
tx_xfer_ptr <= tx_xfer_ptr + 1;
end if;
end if;
end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
host_data_we <= '0';
tx_alloc_req_en <= '0';
if RST_I = '1' then
rx_int_en <= '0';
tx_int_en <= '0';
tx_err <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
when "0000" =>
tx_err <= DAT_I(31);
tx_alloc_req_en <= DAT_I(16);
tx_int_en <= DAT_I(5);
rx_int_en <= DAT_I(4);
when "0001" =>
if tx_alloc_req = '0' then
host_tx_size <= DAT_I(31 downto 16);
end if;
when "0010" =>
host_data_we <= '1';
host_data_reg <= DAT_I;
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
when "0000" =>
DAT_O(31) <= tx_err;
DAT_O(30) <= mii_rx_er;
DAT_O(29) <= mii_col;
DAT_O(28) <= mii_crs;
DAT_O(16) <= tx_alloc_req;
DAT_O(5) <= tx_int_en;
DAT_O(4) <= rx_int_en;
when "0001" =>
DAT_O(31 downto 16) <= host_tx_size;
when "0010" =>
when others => null;
end case;
end if;
end if;
end process;
inst_tx_ram : entity work.dpram_2w2r
GENERIC MAP
(
addr_width => TX_RAM_ADDR_WIDTH,
data_width => 36
)
PORT MAP
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => tx_ram_en_a,
en_b => tx_ram_en_b,
we_a => tx_ram_we_a,
we_b => tx_ram_we_b,
addr_a => tx_ram_addr_a,
addr_b => tx_ram_addr_b,
din_a => tx_ram_din_a,
din_b => tx_ram_din_b,
dout_a => tx_ram_dout_a,
dout_b => tx_ram_dout_b
);
-- Instantiate synchronous FIFO
inst_tx_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => 5,
data_width => 36,
do_last_read_update => true
)
PORT MAP
(
rst => RST_I,
clk_w => CLK_I,
clk_r => mii_tx_clk,
we => tx_fifo_we,
re => tx_fifo_re,
fifo_full => tx_fifo_full,
fifo_empty => tx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => tx_fifo_din,
data_r => tx_fifo_dout
);
inst_piso : entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => 8,
msb_first => false
)
PORT MAP
(
rst => RST_I,
clk => mii_tx_clk,
din_vld => tx_data_vld,
din_rdy => piso_din_rdy,
din_be => tx_fifo_dout(35 downto 32),
din => tx_fifo_dout(31 downto 0),
dout_en => mii_tx_en,
dout => mii_tx
);
irq_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
irq_tx <= tx_int_en;
irq_rx <= rx_int_en;
end if;
end process;
end behavior;
lib/emac/sim/tb_emac_jb.fdo
+23
View File
@@ -0,0 +1,23 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/sipo.vhd"
vcom -explicit -93 "../src/shifter.vhd"
vcom -explicit -93 "../src/emac_jb.vhd"
vcom -explicit -93 "../src/tb_emac_jb.vhd"
vsim -t 1ps -lib work tb_emac_jb
view wave
do {tb_emac_jb.wdo}
view structure
view signals
run 20 us
lib/emac/sim/tb_emac_jb.wdo
+169
View File
@@ -0,0 +1,169 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_emac_jb/rst
add wave -noupdate -format Logic /tb_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_emac_jb/stb_i
add wave -noupdate -format Logic /tb_emac_jb/we_i
add wave -noupdate -format Literal /tb_emac_jb/sel_i
add wave -noupdate -format Logic /tb_emac_jb/ack_o
add wave -noupdate -format Logic /tb_emac_jb/int_o
add wave -noupdate -format Logic /tb_emac_jb/mrdy_i
add wave -noupdate -format Logic /tb_emac_jb/srdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
add wave -noupdate -format Logic /tb_emac_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_jb/mii_col
add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/emac_action
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_err
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Literal -radix unsigned /tb_emac_jb/inst_emac_jb/tx_nwords_free
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_flush_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ok
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_commit_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ack
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_b
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/host_tx_s
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_b
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_ptr
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_data_vld
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tag
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_remain
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_odd
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_remain_en
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tx_s
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/piso_din_be
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/piso_din_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_we
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_din
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_empty
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_tx_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/host_data_we
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_data_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/inter_frame_gap_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/inter_frame_gap_rdy
add wave -noupdate -divider Shifter
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/shift_sa
add wave -noupdate -format Logic /tb_emac_jb/shift_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_din
add wave -noupdate -format Logic /tb_emac_jb/shift_dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_dout
add wave -noupdate -divider PiSo
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_emac_jb/piso_din_vld
add wave -noupdate -format Logic /tb_emac_jb/piso_din_rdy
add wave -noupdate -format Literal /tb_emac_jb/piso_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_din
add wave -noupdate -format Logic /tb_emac_jb/piso_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_dout
add wave -noupdate -format Logic /tb_emac_jb/inst_piso/pre_fin
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/din_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/din_be_reg
add wave -noupdate -format Logic /tb_emac_jb/inst_piso/din_vld_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/vld_pipe
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_vld
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_rdy
add wave -noupdate -format Literal /tb_emac_jb/piso2_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_din
add wave -noupdate -format Logic /tb_emac_jb/piso2_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_dout
add wave -noupdate -format Logic /tb_emac_jb/piso2_enable
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/pre_fin
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/rdy
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso2/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/vld_pipe
add wave -noupdate -divider SiPo
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/clk
add wave -noupdate -format Logic /tb_emac_jb/sipo_enable
add wave -noupdate -format Logic /tb_emac_jb/sipo_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_din
add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_en
add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_vld
add wave -noupdate -format Literal /tb_emac_jb/sipo_dout_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_dout
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/pre_fin
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/abort
add wave -noupdate -format Literal /tb_emac_jb/inst_sipo/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo/shift_pipe
add wave -noupdate -format Logic /tb_emac_jb/sipo2_enable
add wave -noupdate -format Logic /tb_emac_jb/sipo2_rst
add wave -noupdate -format Logic /tb_emac_jb/sipo2_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_din
add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_en
add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_vld
add wave -noupdate -format Literal /tb_emac_jb/sipo2_dout_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_dout
add wave -noupdate -format Literal /tb_emac_jb/inst_sipo2/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo2/shift_pipe
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {19622640 ps} 0} {{Cursor 2} {121551751 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {21 us}
lib/emac/sim/tb_emac_top_jb.fdo
+29
View File
@@ -0,0 +1,29 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/sipo.vhd"
vcom -explicit -93 "../src/shifter.vhd"
vcom -explicit -93 "../src/emac_types.vhd"
vcom -explicit -93 "../src/emac_rx.vhd"
vcom -explicit -93 "../src/emac_tx.vhd"
vcom -explicit -93 "../src/emac_top_jb.vhd"
vcom -explicit -93 "../src/pkt_gen.vhd"
vcom -explicit -93 "../src/tb_emac_top_jb.vhd"
vsim -t 1ps -lib work tb_emac_top_jb
view wave
do {tb_emac_top_jb.wdo}
view structure
view signals
run 50000 us
lib/emac/sim/tb_emac_top_jb.wdo
+198
View File
@@ -0,0 +1,198 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/sel_i
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/we_i
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/ack_o
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/srdy_o
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_rx
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
add wave -noupdate -divider {Packet generator}
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
add wave -noupdate -divider RX
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
add wave -noupdate -divider TX
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {47057926829 ps} 0} {{Cursor 2} {50099085366 ps} 0} {{Cursor 3} {18156000484 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {24865002750 ps}
lib/emac/src/crc32.vhd
-64
View File
@@ -1,64 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all; -- Imports the standard textio package.
ENTITY crc32 IS
Generic
(
crc32_init : unsigned(31 downto 0) := X"00000000"
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
din_vld : in STD_LOGIC;
din : in unsigned(7 downto 0);
crc32_vld : out STD_LOGIC;
crc32_out : out unsigned(31 downto 0)
);
END crc32;
ARCHITECTURE behavior OF crc32 IS
type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
constant crc_table : crc_table_t :=
(
X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
);
signal crc0 : unsigned(31 downto 0);
signal crc1 : unsigned(31 downto 0);
signal crc2 : unsigned(31 downto 0);
--------------------------------------------------------------------------
begin
crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
crc32_out <= crc0;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
crc0 <= crc32_init;
crc32_vld <= '0';
elsif din_vld = '1' then
crc0 <= crc2;
crc32_vld <= '1';
end if;
end if;
end process;
--------------------------------------------------------------------------
end behavior;
lib/emac/src/emac_rx.vhd
+3 -47
View File
@@ -104,15 +104,8 @@ ARCHITECTURE behavior OF emac_rx IS
signal mac_chk_addr : mac_addr_t; signal mac_chk_addr : mac_addr_t;
signal Gbps_en : std_logic; signal Gbps_en : std_logic;
signal fcs_chk_en : std_logic;
signal rx_en : std_logic; signal rx_en : std_logic;
signal fcs_vld : std_logic;
signal fcs_din_vld : std_logic;
signal fcs_din : unsigned(7 downto 0);
signal fcs : unsigned(31 downto 0);
signal fcs_chk_OK : std_logic;
type host_state_t is (host_init, host_flush, host_idle); type host_state_t is (host_init, host_flush, host_idle);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
@@ -150,11 +143,11 @@ begin
ram_addr_a <= xfer_ptr; ram_addr_a <= xfer_ptr;
ram_we_a <= xfer_en and sipo32_dout_vld; ram_we_a <= xfer_en and sipo32_dout_vld;
xfer_vld <= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK); xfer_vld <= mac_chk_OK or mac_chk_BC or xfer_promiscious;
cmd_fifo_we <= commit_en and xfer_vld; cmd_fifo_we <= commit_en and xfer_vld;
cmd_fifo_re <= ctrl_in.pkt_free_en; cmd_fifo_re <= ctrl_in.pkt_free_en;
cmd_pkt_valid_in <= fcs_chk_OK; cmd_pkt_valid_in <= '1';
cmd_mac_ok_in <= mac_chk_OK; cmd_mac_ok_in <= mac_chk_OK;
cmd_bcast_in <= mac_chk_BC; cmd_bcast_in <= mac_chk_BC;
cmd_nbytes_in <= byte_count; cmd_nbytes_in <= byte_count;
@@ -201,7 +194,6 @@ host2xfer_sync_register:
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
xfer_promiscious <= ctrl_in.promiscious; xfer_promiscious <= ctrl_in.promiscious;
Gbps_en <= ctrl_in.Gbps_en; Gbps_en <= ctrl_in.Gbps_en;
fcs_chk_en <= ctrl_in.fcs_chk_en;
mac_addr <= ctrl_in.mac_addr; mac_addr <= ctrl_in.mac_addr;
xfer_ram_limit <= host_ram_limit; xfer_ram_limit <= host_ram_limit;
end if; end if;
@@ -267,11 +259,7 @@ byte_counter:
begin begin
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
if byte_count_rst = '1' then if byte_count_rst = '1' then
if fcs_chk_en = '0' then byte_count <= (others => '0');
byte_count <= to_unsigned(0, RAM_ADDR_WIDTH);
else
byte_count <= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
end if;
elsif sipo32_en = '1' and sipo32_din_vld = '1' then elsif sipo32_en = '1' and sipo32_din_vld = '1' then
byte_count <= byte_count + 1; byte_count <= byte_count + 1;
end if; end if;
@@ -484,38 +472,6 @@ inst_sipo32 : entity work.sipo
); );
inst_fcs: entity work.crc32
GENERIC MAP
(
crc32_init => X"00000000"
)
PORT MAP
(
rst => byte_count_rst,
clk => mii_rx_clk,
din_vld => fcs_din_vld,
din => fcs_din,
crc32_vld => fcs_vld,
crc32_out => fcs
);
fcs_din <= sipo32_din;
fcs_din_vld <= sipo32_en and sipo32_din_vld;
fcs_chk_register:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if fcs_vld = '1' then
fcs_chk_OK <= '0';
if fcs = X"2144DF1C" then
fcs_chk_OK <= '1';
end if;
end if;
end if;
end process;
mii_input_register: mii_input_register:
process(mii_rx_clk) process(mii_rx_clk)
begin begin
lib/emac/src/emac_top_jb.vhd
+27 -62
View File
@@ -64,40 +64,19 @@ ARCHITECTURE behavior OF emac_top_jb IS
signal ready : std_logic; signal ready : std_logic;
signal read : std_logic;
signal write : std_logic;
signal data_read : std_logic;
signal data_write : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_addr : unsigned(3 downto 0);
begin begin
mii_gtx_clk <= '0'; SRDY_O <= CYC_I and ready;
mii_gtx_clk <= '0';
SRDY_O <= CYC_I and ready; ready <= not tx_ctrl_in.pkt_alloc_en;
read <= STB_I and CYC_I and not WE_I;
write <= STB_I and CYC_I and WE_I;
data_read <= read and ADDR_I(15);
data_write <= write and ADDR_I(15);
reg_read <= read and not ADDR_I(15);
reg_write <= write and not ADDR_I(15);
reg_addr <= ADDR_I(5 downto 2);
ready <= not tx_ctrl_in.pkt_alloc_en;
tx_din_vld <= data_write;
tx_din <= DAT_I;
rx_ctrl_in.pkt_read_en <= data_read;
------------------------------------------------------------------ ------------------------------------------------------------------
registers_write: registers_write:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
tx_din_vld <= '0';
tx_ctrl_in.pkt_alloc_en <= '0'; tx_ctrl_in.pkt_alloc_en <= '0';
tx_ctrl_in.pkt_commit_en <= '0'; tx_ctrl_in.pkt_commit_en <= '0';
tx_ctrl_in.reset <= '0'; tx_ctrl_in.reset <= '0';
@@ -112,42 +91,38 @@ registers_write:
rx_ctrl_in.promiscious <= '0'; rx_ctrl_in.promiscious <= '0';
tx_ctrl_in.Gbps_en <= '0'; tx_ctrl_in.Gbps_en <= '0';
rx_ctrl_in.Gbps_en <= '0'; rx_ctrl_in.Gbps_en <= '0';
tx_ctrl_in.fcs_gen_en <= '0'; elsif (STB_I and CYC_I and WE_I) = '1' then
rx_ctrl_in.fcs_chk_en <= '0'; case ADDR_I(5 downto 2) is
elsif reg_write = '1' then
-- 0x0000 .. 0x003C
case reg_addr is
-- 0x0000 -- 0x0000
when "0000" => when "0000" =>
rx_ctrl_in.reset <= DAT_I(31); rx_ctrl_in.reset <= DAT_I(31);
rx_ctrl_in.Gbps_en <= DAT_I(30); rx_ctrl_in.Gbps_en <= DAT_I(30);
rx_ctrl_in.fcs_chk_en <= DAT_I(29);
rx_ctrl_in.promiscious <= DAT_I(23); rx_ctrl_in.promiscious <= DAT_I(23);
rx_ctrl_in.pkt_req_en <= DAT_I(17); rx_ctrl_in.pkt_req_en <= DAT_I(17);
rx_ctrl_in.pkt_free_en <= DAT_I(16); rx_ctrl_in.pkt_free_en <= DAT_I(16);
rx_int_en <= DAT_I(4); rx_int_en <= DAT_I(4);
-- 0x0004 -- 0x0004
-- rx_size R/O -- rx_size R/O
-- 0x0008 -- 0x0008
when "0010" => when "0010" =>
tx_ctrl_in.reset <= DAT_I(31); tx_ctrl_in.reset <= DAT_I(31);
tx_ctrl_in.Gbps_en <= DAT_I(30); tx_ctrl_in.Gbps_en <= DAT_I(30);
tx_ctrl_in.fcs_gen_en <= DAT_I(29);
tx_ctrl_in.pkt_alloc_en <= DAT_I(17); tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
tx_ctrl_in.pkt_commit_en <= DAT_I(16); tx_ctrl_in.pkt_commit_en <= DAT_I(16);
tx_int_en <= DAT_I(4); tx_int_en <= DAT_I(4);
-- 0x000C -- 0x000C
when "0011" => when "0011" =>
tx_ctrl_in.tx_size <= DAT_I(15 downto 0); tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
-- 0x0010 -- 0x0010
-- Gap when "0100" =>
tx_din_vld <= '1';
tx_din <= DAT_I;
-- 0x0014 -- 0x0014
-- Gap -- Gap
@@ -157,18 +132,14 @@ registers_write:
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16); rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8); rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0); rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
-- 0x001C -- 0x001C
when "0111" => when "0111" =>
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24); rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16); rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
-- 0x0020 .. 0x003C
-- Gap
when others => null; when others => null;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
@@ -177,12 +148,11 @@ registers_read:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
ACK_O <= rx_dout_vld; rx_ctrl_in.pkt_read_en <= '0';
ACK_O <= rx_dout_vld and CYC_I and not WE_I;
DAT_O <= rx_dout; DAT_O <= rx_dout;
if reg_read = '1' then if (STB_I and CYC_I) = '1' and WE_I = '0' then
case ADDR_I(5 downto 2) is
-- 0x0000 .. 0x003C
case reg_addr is
-- 0x0000 -- 0x0000
when "0000" => when "0000" =>
@@ -190,14 +160,13 @@ registers_read:
DAT_O <= (others => '0'); DAT_O <= (others => '0');
DAT_O(31) <= rx_ctrl_out.reset_busy; DAT_O(31) <= rx_ctrl_out.reset_busy;
DAT_O(30) <= rx_ctrl_in.Gbps_en; DAT_O(30) <= rx_ctrl_in.Gbps_en;
DAT_O(29) <= rx_ctrl_in.fcs_chk_en;
DAT_O(23) <= rx_ctrl_in.promiscious; DAT_O(23) <= rx_ctrl_in.promiscious;
DAT_O(19) <= rx_ctrl_out.pkt_bcast; DAT_O(19) <= rx_ctrl_out.pkt_bcast;
DAT_O(18) <= rx_ctrl_out.pkt_mac_match; DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
DAT_O(17) <= rx_ctrl_out.pkt_valid; DAT_O(17) <= rx_ctrl_out.pkt_valid;
DAT_O(16) <= rx_ctrl_out.pkt_avail; DAT_O(16) <= rx_ctrl_out.pkt_avail;
DAT_O(4) <= rx_int_en; DAT_O(4) <= rx_int_en;
-- 0x0004 -- 0x0004
when "0001" => when "0001" =>
ACK_O <= '1'; ACK_O <= '1';
@@ -209,20 +178,20 @@ registers_read:
DAT_O <= (others => '0'); DAT_O <= (others => '0');
DAT_O(31) <= tx_ctrl_out.reset_busy; DAT_O(31) <= tx_ctrl_out.reset_busy;
DAT_O(30) <= tx_ctrl_in.Gbps_en; DAT_O(30) <= tx_ctrl_in.Gbps_en;
DAT_O(29) <= tx_ctrl_in.fcs_gen_en;
DAT_O(24) <= tx_ctrl_out.pkt_done; DAT_O(24) <= tx_ctrl_out.pkt_done;
DAT_O(17) <= tx_ctrl_out.pkt_alloc_req; DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
DAT_O(16) <= tx_ctrl_out.pkt_armed; DAT_O(16) <= tx_ctrl_out.pkt_armed;
DAT_O(4) <= tx_int_en; DAT_O(4) <= tx_int_en;
-- 0x000C -- 0x000C
when "0011" => when "0011" =>
ACK_O <= '1'; ACK_O <= '1';
DAT_O <= X"0000" & tx_ctrl_out.tx_size; DAT_O <= X"0000" & tx_ctrl_out.tx_size;
-- 0x0010 -- 0x0010
-- Gap when "0100" =>
rx_ctrl_in.pkt_read_en <= '1';
-- 0x0014 -- 0x0014
-- Gap -- Gap
@@ -230,18 +199,14 @@ registers_read:
when "0110" => when "0110" =>
ACK_O <= '1'; ACK_O <= '1';
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3); DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
-- 0x001C -- 0x001C
when "0111" => when "0111" =>
ACK_O <= '1'; ACK_O <= '1';
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000"; DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
-- 0x0020 .. 0x003C
-- Gap
when others => null; when others => null;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
lib/emac/src/emac_tx.vhd
+45 -144
View File
@@ -96,29 +96,16 @@ ARCHITECTURE behavior OF emac_tx IS
signal piso8_dout_vld : std_logic; signal piso8_dout_vld : std_logic;
signal piso8_din_rdy : std_logic; signal piso8_din_rdy : std_logic;
signal piso8_din_vld : std_logic;
signal piso8_dout : unsigned(3 downto 0); signal piso8_dout : unsigned(3 downto 0);
signal piso8_din : unsigned(7 downto 0);
signal reset_pipe : unsigned(31 downto 0); signal reset_pipe : unsigned(31 downto 0);
signal Gbps_en : std_logic; signal Gbps_en : std_logic;
signal fcs_gen_en : std_logic;
signal fcs_inject_en : std_logic; subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
signal fcs_rst : std_logic; -- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
signal fcs_en : unsigned(7 downto 0);
signal fcs_vld : std_logic;
signal fcs_din_vld : std_logic;
signal fcs : unsigned(31 downto 0);
signal fcs_rev_endian : unsigned(31 downto 0);
signal mii_fifo_we : std_logic;
signal mii_fifo_re : std_logic;
signal mii_fifo_full : std_logic;
signal mii_fifo_empty : std_logic;
signal mii_fifo_re_dly : unsigned(23 downto 0);
signal mii_bsy : std_logic; signal ifg_cnt : ifg_cnt_t;
signal ifg_idle : std_logic;
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit); type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
@@ -157,8 +144,8 @@ begin
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111"; ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
piso32_din <= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0); piso32_din <= preamble(preamble_addr) when preamble_en = '1' else ram_dout_b(31 downto 0);
piso32_din_be <= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32); piso32_din_be <= "1111" when preamble_en = '1' else ram_dout_b(35 downto 32);
cmd_fifo_we <= commit_en; cmd_fifo_we <= commit_en;
cmd_fifo_re <= uncommit_en; cmd_fifo_re <= uncommit_en;
@@ -172,8 +159,6 @@ begin
fill_cnt_en <= fill_bsy and din_vld; fill_cnt_en <= fill_bsy and din_vld;
mem_free_en <= not mem_free_ack(0) and mem_free_ack(1); mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
fcs_rev_endian <= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
------------------------------------------------------------------ ------------------------------------------------------------------
reset_gen: reset_gen:
process(clk) process(clk)
@@ -336,7 +321,6 @@ mem_free_counter:
end if; end if;
end process; end process;
------------------------------------------------------------------
mem_free_mii: mem_free_mii:
process(mii_tx_clk) process(mii_tx_clk)
begin begin
@@ -353,7 +337,6 @@ mem_free_mii:
end if; end if;
end process; end process;
------------------------------------------------------------------
mem_free_host: mem_free_host:
process(clk) process(clk)
begin begin
@@ -371,6 +354,14 @@ mem_free_host:
end if; end if;
end process; end process;
host2xfer_sync_register:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
Gbps_en <= ctrl_in.Gbps_en;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
-- Fill stuff -- Fill stuff
------------------------------------------------------------------ ------------------------------------------------------------------
@@ -400,7 +391,6 @@ fill_counter:
end if; end if;
end process; end process;
------------------------------------------------------------------
fill_pointer: fill_pointer:
process(clk) process(clk)
begin begin
@@ -416,14 +406,21 @@ fill_pointer:
------------------------------------------------------------------ ------------------------------------------------------------------
-- Transfer stuff -- Transfer stuff
------------------------------------------------------------------ ------------------------------------------------------------------
host2xfer_sync_register: interframe_gap_counter:
process(mii_tx_clk) process(mii_tx_clk)
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
Gbps_en <= ctrl_in.Gbps_en; ifg_idle <= '0';
fcs_gen_en <= ctrl_in.fcs_gen_en; if reset_en = '1' or piso32_dout_vld = '1' then
end if; ifg_cnt <= ifg_cnt_t'high;
end process; ifg_idle <= '1';
elsif ifg_cnt /= 0 then
ifg_cnt <= ifg_cnt - 1;
else
ifg_idle <= '1';
end if;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
xfer_counter: xfer_counter:
@@ -449,7 +446,6 @@ xfer_counter:
end process; end process;
------------------------------------------------------------------
xfer_pointer: xfer_pointer:
process(mii_tx_clk) process(mii_tx_clk)
begin begin
@@ -479,7 +475,7 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en) process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy)
begin begin
piso32_din_vld <= '0'; piso32_din_vld <= '0';
@@ -488,8 +484,6 @@ xfer_state:
xfer_set <= '0'; xfer_set <= '0';
xfer_en <= '0'; xfer_en <= '0';
xfer_free_en <= '0'; xfer_free_en <= '0';
fcs_rst <= '0';
fcs_inject_en <= '0';
uncommit_en <= '0'; uncommit_en <= '0';
xfer_sn <= xfer_s; xfer_sn <= xfer_s;
@@ -500,18 +494,15 @@ xfer_state:
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
when xfer_idle => when xfer_idle =>
if cmd_fifo_empty = '0' and mii_bsy = '0' then if cmd_fifo_empty = '0' and piso32_din_rdy = '1' then
xfer_sn <= xfer_start; xfer_sn <= xfer_start;
end if; end if;
when xfer_start => when xfer_start =>
if cmd_fifo_empty = '0' then xfer_set <= '1';
xfer_sn <= xfer_preamble0; xfer_sn <= xfer_preamble0;
end if;
when xfer_preamble0 => when xfer_preamble0 =>
xfer_set <= '1';
fcs_rst <= '1';
preamble_addr <= 0; preamble_addr <= 0;
preamble_en <= '1'; preamble_en <= '1';
piso32_din_vld <= '1'; piso32_din_vld <= '1';
@@ -532,28 +523,23 @@ xfer_state:
piso32_din_vld <= xfer_bsy; piso32_din_vld <= xfer_bsy;
xfer_en <= '1'; xfer_en <= '1';
if xfer_bsy = '0' then if xfer_bsy = '0' then
xfer_sn <= xfer_stop; uncommit_en <= '1';
end if; xfer_free_en <= '1';
xfer_sn <= xfer_crc;
when xfer_stop =>
if piso32_dout_vld = '0' then
xfer_sn <= xfer_finish;
if fcs_gen_en = '1' then
xfer_sn <= xfer_crc;
end if;
end if; end if;
when xfer_crc => when xfer_crc =>
fcs_inject_en <= piso32_din_rdy; xfer_sn <= xfer_stop;
piso32_din_vld <= '1';
if piso32_din_rdy = '1' then when xfer_stop =>
if piso32_dout_vld = '0' then
xfer_sn <= xfer_finish; xfer_sn <= xfer_finish;
end if; end if;
when xfer_finish => when xfer_finish =>
uncommit_en <= '1'; if ifg_idle = '0' then
xfer_free_en <= '1'; xfer_sn <= xfer_idle;
xfer_sn <= xfer_idle; end if;
when others => when others =>
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
@@ -581,7 +567,6 @@ inst_ram : entity work.dpram_1w1r
dout_b => ram_dout_b dout_b => ram_dout_b
); );
------------------------------------------------------------------
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
inst_cmd_fifo: entity work.fifo_async inst_cmd_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
@@ -605,7 +590,6 @@ inst_cmd_fifo: entity work.fifo_async
data_r => cmd_fifo_dout data_r => cmd_fifo_dout
); );
------------------------------------------------------------------
inst_piso32 : entity work.piso inst_piso32 : entity work.piso
GENERIC MAP GENERIC MAP
( (
@@ -627,87 +611,8 @@ inst_piso32 : entity work.piso
); );
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy; piso32_dout_en <= '1' when Gbps_en = '1' else piso8_din_rdy;
------------------------------------------------------------------
fcs_enable_gen:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if fcs_rst = '1' then
fcs_en <= (others => '0');
elsif piso32_dout_vld = '1' then
fcs_en <= fcs_en(fcs_en'left-1 downto 0) & '1';
end if;
end if;
end process;
------------------------------------------------------------------
inst_fcs: entity work.crc32
GENERIC MAP
(
crc32_init => X"00000000"
)
PORT MAP
(
rst => fcs_rst,
clk => mii_tx_clk,
din_vld => fcs_din_vld,
din => piso32_dout,
crc32_vld => fcs_vld,
crc32_out => fcs
);
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
------------------------------------------------------------------
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
mii_fifo_re_dly_gen:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if mii_fifo_empty = '1' then
if Gbps_en = '0' then
mii_fifo_re_dly <= X"000000"; -- 100 mbps
else
mii_fifo_re_dly <= X"000FFF"; -- Gigabit
end if;
else
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
end if;
end if;
end process;
mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left);
------------------------------------------------------------------
-- Instantiate synchronous FIFO
inst_mii_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 4,
data_width => piso32_dout'length,
do_last_read_update => true
)
PORT MAP
(
rst => reset_en,
clk => mii_tx_clk,
we => mii_fifo_we,
re => mii_fifo_re,
fifo_full => mii_fifo_full,
fifo_empty => mii_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => piso32_dout,
data_r => piso8_din
);
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
mii_fifo_we <= piso32_dout_vld;
------------------------------------------------------------------
inst_piso8 : entity work.piso inst_piso8 : entity work.piso
GENERIC MAP GENERIC MAP
( (
@@ -719,27 +624,24 @@ inst_piso8 : entity work.piso
( (
rst => reset_en, rst => reset_en,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => piso8_din_vld, din_vld => piso32_dout_vld,
din_rdy => piso8_din_rdy, din_rdy => piso8_din_rdy,
din_be => "11", din_be => "11",
din => piso8_din, din => piso32_dout,
dout_vld => piso8_dout_vld, dout_vld => piso8_dout_vld,
dout_en => '1', dout_en => '1',
dout => piso8_dout dout => piso8_dout
); );
piso8_din_vld <= not mii_fifo_empty and mii_bsy;
------------------------------------------------------------------
mii_output_register: mii_output_register:
process(mii_tx_clk) process(mii_tx_clk)
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
mii_tx_er <= '0'; mii_tx_er <= '0';
if Gbps_en = '1' then if Gbps_en = '1' then
mii_tx_en <= piso8_din_vld; mii_tx_en <= piso32_dout_vld;
mii_tx <= piso8_din; mii_tx <= piso32_dout;
else else
mii_tx_en <= piso8_dout_vld; mii_tx_en <= piso8_dout_vld;
mii_tx <= "0000" & piso8_dout; mii_tx <= "0000" & piso8_dout;
@@ -747,5 +649,4 @@ mii_output_register:
end if; end if;
end process; end process;
------------------------------------------------------------------
end behavior; end behavior;
lib/emac/src/emac_types.vhd
-2
View File
@@ -18,7 +18,6 @@ package emac_types is
type tx_ctrl_in_t is record type tx_ctrl_in_t is record
Gbps_en : std_logic; Gbps_en : std_logic;
reset : std_logic; reset : std_logic;
fcs_gen_en : std_logic;
tx_size : unsigned(15 downto 0); tx_size : unsigned(15 downto 0);
pkt_commit_en : std_logic; pkt_commit_en : std_logic;
pkt_alloc_en : std_logic; pkt_alloc_en : std_logic;
@@ -35,7 +34,6 @@ package emac_types is
type rx_ctrl_in_t is record type rx_ctrl_in_t is record
Gbps_en : std_logic; Gbps_en : std_logic;
reset : std_logic; reset : std_logic;
fcs_chk_en : std_logic;
pkt_read_en : std_logic; pkt_read_en : std_logic;
pkt_req_en : std_logic; pkt_req_en : std_logic;
pkt_free_en : std_logic; pkt_free_en : std_logic;
lib/emac/src/piso.vhd
+42 -24
View File
@@ -31,18 +31,19 @@ ARCHITECTURE behavior OF piso IS
constant num_shifts : natural := data_width_in/data_width_out; constant num_shifts : natural := data_width_in/data_width_out;
signal pre_fin : STD_LOGIC; signal pre_fin : STD_LOGIC;
signal rdy : STD_LOGIC;
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0); signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
signal shift_pipe : unsigned(data_width_in-1 downto 0); signal shift_pipe : unsigned(data_width_in-1 downto 0);
signal vld_pipe : unsigned(num_shifts-1 downto 0); signal vld_pipe : unsigned(num_shifts-1 downto 0);
signal din_reg : unsigned(data_width_in-1 downto 0); signal din_reg : unsigned(data_width_in-1 downto 0);
signal din_be_reg : unsigned(num_shifts-1 downto 0); signal din_be_reg : unsigned(num_shifts-1 downto 0);
signal din_reg_empty : STD_LOGIC; signal din_vld_reg : STD_LOGIC;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1); pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
din_rdy <= din_reg_empty; din_rdy <= rdy;
dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0); dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
else shift_pipe(data_width_out-1 downto 0); else shift_pipe(data_width_out-1 downto 0);
@@ -52,13 +53,11 @@ process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
din_reg_empty <= '1'; rdy <= '0';
elsif din_reg_empty = '1' then elsif pre_fin = '1' and rdy = '0' then
if din_vld = '1' then rdy <= '1';
din_reg_empty <= '0'; elsif din_vld = '1' then
end if; rdy <= '0';
elsif pre_fin = '1' and dout_en = '1' then
din_reg_empty <= '1';
end if; end if;
end if; end if;
end process; end process;
@@ -66,7 +65,18 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if din_vld = '1' and din_reg_empty = '1' then if rst = '1' then
din_vld_reg <= '0';
elsif (pre_fin = '1' and dout_en = '1') or din_vld_reg = '0' then
din_vld_reg <= din_vld;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if din_vld = '1' and rdy = '1' then
din_reg <= din; din_reg <= din;
din_be_reg <= din_be; din_be_reg <= din_be;
end if; end if;
@@ -78,10 +88,14 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
shift_cnt_pipe <= (others => '1'); shift_cnt_pipe <= (others => '1');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then elsif (din_vld = '1' and din_vld_reg = '0') then
shift_cnt_pipe <= (others => '0'); shift_cnt_pipe <= (others => '0');
elsif dout_en = '1' then elsif dout_en = '1' then
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1'; if (pre_fin = '1' and din_vld_reg = '1') then
shift_cnt_pipe <= (others => '0');
else
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -90,13 +104,15 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then if dout_en = '1' then
shift_pipe <= din_reg; if pre_fin = '1' and din_vld_reg = '1' then
elsif dout_en = '1' then shift_pipe <= din_reg;
if (msb_first) then else
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0'); if (msb_first) then
else shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out); else
shift_pipe <= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
end if;
end if; end if;
end if; end if;
end if; end if;
@@ -108,13 +124,15 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
vld_pipe <= (others => '0'); vld_pipe <= (others => '0');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
vld_pipe <= din_be_reg;
elsif dout_en = '1' then elsif dout_en = '1' then
if (msb_first) then if pre_fin = '1' and din_vld_reg = '1' then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0'; vld_pipe <= din_be_reg;
else else
vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1); if (msb_first) then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
else
vld_pipe <= '0' & vld_pipe(vld_pipe'left downto 1);
end if;
end if; end if;
end if; end if;
end if; end if;
lib/emac/src/pkt_gen.vhd
+9 -5
View File
@@ -12,6 +12,8 @@ ENTITY pkt_gen IS
( (
f_sysclk : real := 100.0; f_sysclk : real := 100.0;
TX_RAM_SIZE : natural := 2048; TX_RAM_SIZE : natural := 2048;
PKT_DLY_MIN : real := 1.0E-6;
PKT_DLY_MAX : real := 100.0E-6;
PKT_SIZE_MIN : natural := 64; PKT_SIZE_MIN : natural := 64;
PKT_SIZE_MAX : natural := 1518 PKT_SIZE_MAX : natural := 1518
@@ -21,8 +23,6 @@ ENTITY pkt_gen IS
clk : in STD_LOGIC; clk : in STD_LOGIC;
rst : in STD_LOGIC; rst : in STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
gigabit_en : in STD_LOGIC;
fcs_gen_en : in STD_LOGIC;
mii_tx_clk : in STD_LOGIC; mii_tx_clk : in STD_LOGIC;
mii_tx_en : out STD_LOGIC; mii_tx_en : out STD_LOGIC;
mii_tx_er : out STD_LOGIC; mii_tx_er : out STD_LOGIC;
@@ -38,6 +38,7 @@ ARCHITECTURE behavior OF pkt_gen IS
signal pkt_data : unsigned(31 downto 0); signal pkt_data : unsigned(31 downto 0);
signal pkt_nbytes : word_ptr_t := X"0040"; signal pkt_nbytes : word_ptr_t := X"0040";
signal pkt_nwords : word_ptr_t := X"0010"; signal pkt_nwords : word_ptr_t := X"0010";
signal pkt_delay : natural := natural(1.0*f_sysclk);
signal fill_size : word_ptr_t; signal fill_size : word_ptr_t;
signal fill_cnt : word_ptr_t; signal fill_cnt : word_ptr_t;
@@ -72,14 +73,13 @@ host_state_next:
end process; end process;
host_state: host_state:
process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en, gigabit_en, fcs_gen_en) process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en)
begin begin
tx_ctrl_in.pkt_alloc_en <= '0'; tx_ctrl_in.pkt_alloc_en <= '0';
tx_ctrl_in.pkt_commit_en <= '0'; tx_ctrl_in.pkt_commit_en <= '0';
tx_ctrl_in.reset <= '0'; tx_ctrl_in.reset <= '0';
tx_ctrl_in.Gbps_en <= gigabit_en; tx_ctrl_in.Gbps_en <= '0';
tx_ctrl_in.fcs_gen_en <= fcs_gen_en;
tx_ctrl_in.tx_size <= pkt_nbytes; tx_ctrl_in.tx_size <= pkt_nbytes;
fill_set <= '0'; fill_set <= '0';
fill_en <= '0'; fill_en <= '0';
@@ -132,6 +132,7 @@ host_state:
pkt_generator: pkt_generator:
process(clk) process(clk)
variable size : word_ptr_t; variable size : word_ptr_t;
variable delay : natural;
variable krand : real; variable krand : real;
variable seed1 : integer; variable seed1 : integer;
variable seed2 : integer; variable seed2 : integer;
@@ -140,6 +141,7 @@ pkt_generator:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length); size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
delay := natural(1.0E6*PKT_DLY_MIN*f_sysclk);
seed1 := 31101970; seed1 := 31101970;
seed2 := 12586901; seed2 := 12586901;
tx_packets <= 0; tx_packets <= 0;
@@ -147,9 +149,11 @@ pkt_generator:
elsif tx_ctrl_in.pkt_commit_en = '1' then elsif tx_ctrl_in.pkt_commit_en = '1' then
uniform(seed1, seed2, krand); uniform(seed1, seed2, krand);
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length); size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
tx_packets <= tx_packets + 1; tx_packets <= tx_packets + 1;
tx_bytes <= tx_bytes + to_integer(pkt_nbytes); tx_bytes <= tx_bytes + to_integer(pkt_nbytes);
end if; end if;
pkt_delay <= delay;
pkt_nbytes <= size; pkt_nbytes <= size;
if size(1 downto 0) = 0 then if size(1 downto 0) = 0 then
pkt_nwords <= "00" & size(word_ptr_t'left downto 2); pkt_nwords <= "00" & size(word_ptr_t'left downto 2);
lib/emac/src/shifter.vhd
+111
View File
@@ -0,0 +1,111 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all; -- Imports the standard textio package.
ENTITY shifter IS
Generic
(
data_width : natural := 32;
aggregate_size : natural := 8;
do_pipelined : boolean := true
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
sa : in integer;
din_vld : in STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout_vld : out STD_LOGIC;
dout : out unsigned(data_width-1 downto 0)
);
END shifter;
ARCHITECTURE behavior OF shifter IS
constant num_rounds : natural := NextExpBaseTwo(data_width/aggregate_size);
subtype sa_rnd_t is signed(num_rounds-1 downto 0);
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to num_rounds) of word_t;
signal rot_data : word_array_t;
signal sa_rnd : sa_rnd_t;
type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
signal sa_rnd_pipe : sa_rnd_array_t;
signal dout_vld_pipe : unsigned(0 to num_rounds);
--------------------------------------------------------------------------
function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
variable result : unsigned(x'range);
constant sa : natural := (2**stage_num) * size;
begin
if en = '1' then
result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
else
result := x;
end if;
return result;
end rol_stage;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
gen_non_pipelined:
if do_pipelined = false generate
begin
rot_data(0) <= din;
gen_rotate_right:
for stage in 0 to num_rounds-1 generate
begin
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
end generate;
sa_rnd <= to_signed(sa, num_rounds);
dout <= rot_data(num_rounds);
dout_vld <= din_vld;
end generate;
--------------------------------------------------------------------------
gen_pipelined:
if do_pipelined = true generate
begin
rot_data(0) <= din;
sa_rnd_pipe(0) <= to_signed(sa, num_rounds);
dout_vld_pipe(0) <= din_vld;
gen_rotate_right:
for stage in 0 to num_rounds-1 generate
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
dout_vld_pipe(stage+1) <= '0';
else
dout_vld_pipe(stage+1) <= dout_vld_pipe(stage);
if dout_vld_pipe(stage) = '1' then
sa_rnd_pipe(stage+1) <= sa_rnd_pipe(stage);
rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
end if;
end if;
end if;
end process;
end generate;
dout <= rot_data(num_rounds);
dout_vld <= dout_vld_pipe(num_rounds);
end generate;
--------------------------------------------------------------------------
end behavior;
lib/emac/src/sipo.vhd
+1 -1
View File
@@ -104,7 +104,7 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if din_vld = '1' or abort = '1' then if (din_en and din_vld) = '1' or abort = '1' then
if (msb_first) then if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din; shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
else else
lib/emac/src/tb_emac_jb.vhd
+428
View File
@@ -0,0 +1,428 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_emac_jb IS
END tb_emac_jb;
ARCHITECTURE behavior OF tb_emac_jb IS
constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 8 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0);
signal ACK_O : std_logic;
signal INT_O : std_logic;
signal MRDY_I : std_logic;
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
-- MII signals
signal mii_rx_clk_board : std_logic := '1';
signal mii_tx_clk_board : std_logic := '1';
signal mii_rx_clk : std_logic := '1';
signal mii_tx_clk : std_logic := '1';
signal mii_rx : unsigned(7 downto 0) := (others => '-');
signal mii_tx : unsigned(7 downto 0);
signal mii_rx_dv : std_logic := '0';
signal mii_rx_er : std_logic := '0';
signal mii_tx_en : std_logic;
signal mii_tx_er : std_logic;
signal mii_crs : std_logic := '0';
signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic;
signal shift_sa : integer := 0;
signal shift_din_vld : std_logic := '0';
signal shift_din : unsigned(31 downto 0) := (others => '-');
signal shift_dout_vld : std_logic;
signal shift_dout : unsigned(31 downto 0);
signal piso_din_vld : std_logic := '0';
signal piso_din_rdy : std_logic;
signal piso_din_be : unsigned(7 downto 0) := (others => '0');
signal piso_din : unsigned(31 downto 0) := (others => '-');
signal piso_dout_en : std_logic;
signal piso_dout : unsigned(3 downto 0);
signal sipo_enable : std_logic := '0';
signal sipo_din_en : std_logic := '0';
signal sipo_din : unsigned(3 downto 0) := (others => '-');
signal sipo_dout_vld : std_logic;
signal sipo_dout_be : unsigned(7 downto 0);
signal sipo_dout : unsigned(31 downto 0);
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
signal emac_action : emac_action_t;
BEGIN
inst_emac_jb : entity work.emac_jb
GENERIC MAP
(
f_sysclk => 100.0,
TX_RAM_SIZE => 2048
)
PORT MAP
(
CLK_I => CLK,
RST_I => RST,
INT_O => INT_O,
CYC_I => CYC_I,
STB_I => STB_I,
SEL_I => SEL_I,
WE_I => WE_I,
ACK_O => ACK_O,
SRDY_O => SRDY_O,
MRDY_I => MRDY_I,
ADDR_I => ADDR_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
mii_rx_clk => mii_rx_clk_board,
mii_rx_dv => mii_rx_dv,
mii_rx_er => mii_rx_er,
mii_rx => mii_rx,
mii_tx_clk => mii_tx_clk_board,
mii_tx_en => mii_tx_en,
mii_tx_er => mii_tx_er,
mii_tx => mii_tx,
mii_gtx_clk => mii_gtx_clk,
mii_crs => mii_crs,
mii_col => mii_col
);
inst_shifter : entity work.shifter
GENERIC MAP
(
data_width => 32,
aggregate_size => 4,
do_pipelined => true
)
PORT MAP
(
rst => RST,
clk => CLK,
sa => shift_sa,
din_vld => shift_din_vld,
din => shift_din,
dout_vld => shift_dout_vld,
dout => shift_dout
);
inst_piso : entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => 4,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_vld => piso_din_vld,
din_rdy => piso_din_rdy,
din_be => piso_din_be,
din => piso_din,
dout_en => piso_dout_en,
dout => piso_dout
);
inst_sipo : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_out => 32,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
enable => sipo_enable,
din_en => sipo_din_en,
din => sipo_din,
dout_be => sipo_dout_be,
dout_vld => sipo_dout_vld,
dout => sipo_dout
);
sipo_din <= piso_dout;
sipo_din_en <= piso_dout_en;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK <= not CLK;
end process;
MII_CLK_GEN: process
begin
wait for MII_CLK_PERIOD/2;
mii_rx_clk <= not mii_rx_clk;
mii_tx_clk <= not mii_tx_clk;
end process;
mii_rx_clk_board <= mii_rx_clk;
mii_tx_clk_board <= mii_tx_clk;
DAT_O_register:
process(CLK)
begin
if rising_edge(CLK) then
if ACK_O = '1' then
DAT_O_reg <= DAT_O;
end if;
end if;
end process;
-- Master
STIMULUS: process
procedure emac_alloc (size : natural) is
begin
-- TX-ALLOCATION
-- set TX-size
emac_action <= emac_alloc;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= to_unsigned(size, 16) & X"55AA";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0004";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
-- set alloc request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0001_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
-- check alloc busy
check_bsy:
while (true) loop
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
wait until rising_edge(CLK);
if DAT_O_reg(16) = '0' then
exit check_bsy;
end if;
end loop;
emac_action <= emac_idle;
end procedure emac_alloc;
procedure emac_write (size : natural) is
variable data : unsigned (7 downto 0);
variable num_words : natural;
begin
-- FILL TX data
emac_action <= emac_write;
if (size mod 4) = 0 then
num_words := size/4;
else
num_words := size/4 + 1;
end if;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00";
ADDR_I <= X"0000_0008";
WE_I <= '1';
for i in 1 to num_words loop
STB_I <= '1';
DAT_I(7 downto 0) <= data;
data := data + 1;
DAT_I(15 downto 8) <= data;
data := data + 1;
DAT_I(23 downto 16) <= data;
data := data + 1;
DAT_I(31 downto 24) <= data;
data := data + 1;
wait until rising_edge(CLK) and SRDY_O = '1';
end loop;
STB_I <= '0';
wait until rising_edge(CLK) and SRDY_O = '1';
emac_action <= emac_idle;
end procedure emac_write;
begin
wait for 6*MII_CLK_PERIOD;
RST <= '0';
wait for 60*CLK_PERIOD;
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (64);
emac_write (64);
emac_alloc (512);
emac_write (512);
emac_alloc (1536);
emac_write (1536);
emac_alloc (65);
emac_write (65);
emac_alloc (66);
emac_write (66);
emac_alloc (67);
emac_write (67);
emac_alloc (512);
emac_write (512);
wait for 4000*CLK_PERIOD;
wait until rising_edge(CLK);
shift_din <= X"12345678";
shift_sa <= 0;
shift_din_vld <= '1';
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= 0;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_din_vld <= '0';
for i in 1 to 10 loop
wait until rising_edge(CLK);
sipo_enable <= '1';
piso_din_vld <= '1';
piso_din <= X"12345678";
piso_din_be <= "11111111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11100111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11111100";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "00111111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= (others => '-');
piso_din_vld <= '0';
wait until rising_edge(CLK) and sipo_dout_vld = '1';
wait until rising_edge(CLK);
wait until rising_edge(CLK) and sipo_dout_vld = '1';
sipo_enable <= '0';
wait for 33*CLK_PERIOD;
end loop;
wait;
end process;
END;
lib/emac/src/tb_emac_top_jb.vhd
+589
View File
@@ -0,0 +1,589 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_emac_top_jb IS
END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 38.7 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0) := (others => '1');
signal ACK_O : std_logic;
signal INT_O : std_logic;
signal MRDY_I : std_logic := '0';
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
signal status_reg : unsigned(31 downto 0) := (others => '0');
signal size_reg : unsigned(31 downto 0) := (others => '0');
-- MII signals
signal mii_rx_clk_board : std_logic := '1';
signal mii_tx_clk_board : std_logic := '1';
signal mii_rx_clk : std_logic := '1';
signal mii_tx_clk : std_logic := '1';
signal mii_rx : unsigned(7 downto 0) := (others => '-');
signal mii_tx : unsigned(7 downto 0);
signal mii_rx_dv : std_logic := '0';
signal mii_rx_er : std_logic := '0';
signal mii_tx_en : std_logic;
signal mii_tx_er : std_logic;
signal mii_crs : std_logic := '0';
signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic;
signal loop_back_en : std_logic := '0';
signal pktgen_tx : unsigned(7 downto 0);
signal pktgen_tx_en : std_logic;
signal pktgen_tx_er : std_logic;
signal pktgen_en : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1';
signal dat_o_cnt : natural;
signal pkt_count : natural;
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
signal emac_action : emac_action_t;
constant RX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0000";
constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010";
BEGIN
inst_emac_top_jb : entity work.emac_top_jb
GENERIC MAP
(
f_sysclk => 100.0,
RX_RAM_SIZE => 2048,
TX_RAM_SIZE => 2048
)
PORT MAP
(
CLK_I => CLK,
RST_I => RST,
INT_O => INT_O,
CYC_I => CYC_I,
STB_I => STB_I,
SEL_I => SEL_I,
WE_I => WE_I,
ACK_O => ACK_O,
SRDY_O => SRDY_O,
MRDY_I => MRDY_I,
ADDR_I => ADDR_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
mii_rx_clk => mii_rx_clk_board,
mii_rx_dv => mii_rx_dv,
mii_rx_er => mii_rx_er,
mii_rx => mii_rx,
mii_tx_clk => mii_tx_clk_board,
mii_tx_en => mii_tx_en,
mii_tx_er => mii_tx_er,
mii_tx => mii_tx,
mii_gtx_clk => mii_gtx_clk,
mii_crs => mii_crs,
mii_col => mii_col
);
inst_pkt_gen : entity work.pkt_gen
GENERIC MAP
(
f_sysclk => 100.0,
PKT_DLY_MIN => 1.0E-6,
PKT_DLY_MAX => 5.0E-6,
PKT_SIZE_MIN => 64,
PKT_SIZE_MAX => 1512
)
PORT MAP
(
clk => CLK,
rst => RST,
en => pktgen_en,
mii_tx_clk => mii_tx_clk_board,
mii_tx_en => pktgen_tx_en,
mii_tx_er => pktgen_tx_er,
mii_tx => pktgen_tx
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK <= not CLK;
end process;
MII_CLK_GEN: process
begin
wait for MII_CLK_PERIOD/2;
mii_rx_clk <= not mii_rx_clk;
mii_tx_clk <= not mii_tx_clk;
end process;
mii_rx_clk_board <= mii_rx_clk;
mii_tx_clk_board <= mii_tx_clk;
DAT_O_register:
process(CLK)
begin
if rising_edge(CLK) then
if ACK_O = '1' then
DAT_O_reg <= DAT_O;
end if;
end if;
end process;
DAT_O_count_register:
process(CLK)
begin
if rising_edge(CLK) then
if dat_o_cnt_rst = '1' then
dat_o_cnt <= 0;
elsif ACK_O = '1' and dat_o_cnt_en = '1' then
dat_o_cnt <= dat_o_cnt + 1;
end if;
end if;
end process;
mii_rx <= mii_tx when loop_back_en = '1' else pktgen_tx;
mii_rx_dv <= mii_tx_en when loop_back_en = '1' else pktgen_tx_en;
mii_rx_er <= mii_tx_er when loop_back_en = '1' else pktgen_tx_er;
mii_crs <= '0';
mii_col <= '0';
-- Master
STIMULUS: process
procedure emac_alloc (size : natural) is
begin
-- TX-ALLOCATION
-- set TX-size
emac_action <= emac_alloc;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= to_unsigned(size, 32);
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_SIZE_REG_ADDR;
check_alloc_ok:
while(true) loop
-- set alloc request
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
check_bsy:
while (true) loop
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK);
if status_reg(17) = '0' then
exit check_bsy;
end if;
end loop;
if status_reg(16) = '1' then
exit check_alloc_ok;
end if;
end loop;
CYC_I <= '0';
emac_action <= emac_idle;
end procedure emac_alloc;
procedure emac_commit is
begin
-- RX- DEALLOCATION
emac_action <= emac_commit;
-- set free request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
emac_action <= emac_idle;
end procedure emac_commit;
procedure emac_write (size : natural) is
variable data : unsigned (7 downto 0);
variable num_words : natural;
begin
-- FILL TX data
emac_action <= emac_write;
if (size mod 4) = 0 then
num_words := size/4;
else
num_words := size/4 + 1;
end if;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00";
ADDR_I <= DATA_REG_ADDR;
WE_I <= '1';
for i in 1 to num_words loop
STB_I <= '1';
DAT_I(7 downto 0) <= data;
data := data + 1;
DAT_I(15 downto 8) <= data;
data := data + 1;
DAT_I(23 downto 16) <= data;
data := data + 1;
DAT_I(31 downto 24) <= data;
data := data + 1;
wait until rising_edge(CLK) and SRDY_O = '1';
end loop;
STB_I <= '0';
wait until rising_edge(CLK) and SRDY_O = '1';
emac_commit;
emac_action <= emac_idle;
end procedure emac_write;
procedure emac_read (size_in : natural) is
variable data : unsigned (7 downto 0);
variable size, num_words : natural;
begin
emac_action <= emac_wait_data;
-- check if data available
check_data_avail:
while (true) loop
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK);
if status_reg(17) = '1' and status_reg(16) = '1' then
exit check_data_avail;
end if;
end loop;
read_size:
dat_o_cnt_rst <= '1';
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= RX_SIZE_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
size_reg <= DAT_O;
wait until rising_edge(CLK);
-- set packet request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
emac_action <= emac_read;
-- Read RX data
size := size_in;
if (size_in = 0) then
size := to_integer(size_reg(15 downto 0));
end if;
if (size mod 4) = 0 then
num_words := size/4;
else
num_words := size/4 + 1;
end if;
dat_o_cnt_rst <= '0';
dat_o_cnt_en <= '1';
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
ADDR_I <= DATA_REG_ADDR;
WE_I <= '0';
STB_I <= '1';
for i in 1 to num_words loop
wait until rising_edge(CLK) and SRDY_O = '1';
end loop;
STB_I <= '0';
wait until rising_edge(CLK) and dat_o_cnt = num_words;
dat_o_cnt_en <= '0';
emac_action <= emac_idle;
end procedure emac_read;
procedure emac_free is
begin
-- RX- DEALLOCATION
emac_action <= emac_free;
-- set free request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
status_reg <= DAT_O;
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
emac_action <= emac_idle;
end procedure emac_free;
begin
wait for 6*MII_CLK_PERIOD;
RST <= '0';
wait for 60*CLK_PERIOD;
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
for i in 1 to 10 loop
for j in 1 to 100 loop
emac_alloc (72);
emac_write (72);
end loop;
wait for 1 ms;
end loop;
wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
wait for 6000*CLK_PERIOD;
loop_back_en <= '1';
emac_alloc (74);
emac_write (74);
emac_alloc (105);
emac_write (105);
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_alloc (103);
emac_write (103);
emac_read (0);
emac_free;
emac_alloc (71);
emac_write (71);
emac_read (0);
emac_free;
emac_alloc (82);
emac_write (82);
emac_alloc (86);
emac_write (86);
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_alloc (77);
emac_write (77);
emac_alloc (99);
emac_write (99);
emac_alloc (65);
emac_write (65);
emac_alloc (321);
emac_write (321);
emac_read (0);
emac_free;
emac_alloc (1111);
emac_write (1111);
emac_read (0);
emac_free;
emac_alloc (73);
emac_write (73);
emac_alloc (107);
emac_write (107);
emac_alloc (83);
emac_write (83);
emac_read (0);
emac_free;
emac_alloc (72);
emac_write (72);
emac_alloc (1003);
emac_write (1003);
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_read (0);
emac_free;
emac_read (0);
emac_free;
wait for 6000*CLK_PERIOD;
loop_back_en <= '0';
pktgen_en <= '1';
pkt_count <= 0;
for i in 1 to 500 loop
wait for 50 us;
emac_read (0);
emac_free;
pkt_count <= pkt_count + 1;
end loop;
pktgen_en <= '0';
emac_read (0);
emac_free;
wait;
end process;
END;
lib/misc/dpram_1w1r.vhd
-79
View File
@@ -1,79 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r;
architecture Behavioral of dpram_1w1r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/dpram_2w2r.vhd
-88
View File
@@ -1,88 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r;
architecture Behavioral of dpram_2w2r is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/misc/utils_pkg.vhd
-196
View File
@@ -1,196 +0,0 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
package utils_pkg is
-- Constants
-- Functions
function MIN (X, Y: INTEGER) return INTEGER;
function MAX (X, Y: INTEGER) return INTEGER;
function NextPowerOfTwo(x : real) return real;
function NextExpBaseTwo(x : real) return real;
function NextPowerOfTwo(x : natural) return natural;
function NextExpBaseTwo(x : natural) return natural;
function GCD(a, b : natural) return natural;
function LCM(a, b : natural) return natural;
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
function f_correct(f : real) return natural;
end utils_pkg;
package body utils_pkg is
-------------------------------------------------------------
function MIN (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y < X then
res := Y;
end if;
return res;
end MIN;
-------------------------------------------------------------
function MAX (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y > X then
res := Y;
end if;
return res;
end MAX;
-------------------------------------------------------------
function NextExpBaseTwo(x : real) return real is
begin
return ceil(log2(x));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : real) return real is
begin
return 2.0**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function NextExpBaseTwo(x : natural) return natural is
begin
return natural(NextExpBaseTwo(real(x)));
end NextExpBaseTwo;
-------------------------------------------------------------
function NextPowerOfTwo(x : natural) return natural is
begin
return 2**NextExpBaseTwo(x);
end NextPowerOfTwo;
-------------------------------------------------------------
function GCD(a, b : natural) return natural is
variable aa : natural;
variable bb : natural;
begin
aa := a;
bb := b;
while bb /= 0 loop
if aa > bb then
aa := aa - bb;
else
bb := bb - aa;
end if;
end loop;
return aa;
end GCD;
-------------------------------------------------------------
function LCM(a, b : natural) return natural is
begin
return (a * b)/GCD(a, b);
end LCM;
-------------------------------------------------------------
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
begin
return 1.0E3/f_in_MHz;
end UTILS_PERIOD_NS;
-------------------------------------------------------------
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
M := 2;
end if;
return M;
end UTILS_FREQ_M;
-------------------------------------------------------------
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
variable f_in : natural;
variable f_out : natural;
variable C : natural;
variable M : natural;
variable D : natural;
begin
C := f_correct(f_out_MHz);
if C < 2 then
C := f_correct(f_in_MHz);
end if;
f_out := natural(ceil(real(C)*f_out_MHz));
f_in := natural(ceil(real(C)*f_in_MHz));
M := LCM(f_in, f_out)/f_in;
D := f_in/GCD(f_in, f_out);
assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
if M = 1 then
D := 2*D;
end if;
return D;
end UTILS_FREQ_D;
-------------------------------------------------------------
function f_correct(f : real) return natural is
constant MAX_ITER : positive := 100;
constant MAX_ERR : real := 0.01;
variable fpart : real;
variable err : real;
begin
for i in 1 to MAX_ITER loop
fpart := real(i)*f - ceil(real(i)*f);
err := abs(fpart);
if err < max_err then
return i;
end if;
end loop;
end f_correct;
-------------------------------------------------------------
end utils_pkg;