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BRANCH_MIPS_TLB
...
R4
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
9e28b9588c |
@@ -1,56 +0,0 @@
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; -------------------------------------------------
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; PROJECT "dctest"
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; -------------------------------------------------
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include "../../../jasm/cregs.inc.jsm"
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; -------------------------------------------------
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xmem
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org 4
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konst: dc 0x01, 0x12,"A"
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gap1: db 16
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mesg: dc "Hallo", 13,0x0A, 0
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name: dc "Jens",0
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msg1: dc "Welcome to JASM CPU",0
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msg2: dc "Ready",0
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msg3: dc "Testing",0
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msg4: dc "Passed",0
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msg5: dc "Error",0
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crlf: dc 0x0D, 0x0A
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org 0x00
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shit: db 4
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cmem 0
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org 8
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cram1: db 16
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cram2: db 6
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cram3: db 4
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cmem 1
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cram4: db 8
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cram5: db 8
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org 0x20
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cram6: db 8
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cram7: db 4
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reg_revision: equ 0x00
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reg_testid: equ 0x01
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; -------------------------------------------------
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code
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org 0x000
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reset: jmp start
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; -------------------------------------------------
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org 0x001
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int_vec: jmp isr
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; -------------------------------------------------
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org 0x010
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start: jmp start
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; -------------------------------------------------
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isr: reti
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@@ -1,212 +0,0 @@
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# ----------------------------------------------------------------------
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# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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# This file: The ROM file for upload to target over JTAG
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#
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# Copyright (C) 2007 J. Ahrensfeld
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# For questions and ideas, please contact the author at jens@jayfield.org
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#
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# ---------------------------------------------------------------------
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# ---------------------------------------------------------------------
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# For Chipscope 9.1
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# ---------------------------------------------------------------------
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# Source JTAG/TCL frame work
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cd $env(CHIPSCOPE)\\bin\\nt
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source csejtag.tcl
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namespace import ::chipscope::*
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# Platform USB Cable
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set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
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# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
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# Create session
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set handle [::chipscope::csejtag_session create 0]
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# Open JTAG and lock
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set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
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set lock_result [::chipscope::csejtag_target lock $handle 1000]
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set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
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# Get Device ID
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set devtype "Virtex-4SX"
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set devid 2
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set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
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set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
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set CSE_OP $CSEJTAG_SHIFT_READWRITE
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set CSE_ES $CSEJTAG_RUN_TEST_IDLE
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# Write Program
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# JASM_ROM_INSERT_HERE
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# Assembled from dctest.jsm
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# ---------------------------------------------------------------
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# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
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# User 1
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set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
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# 0x000: JMP 0x010
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
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# 0x001: JMP 0x011
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
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# 0x002:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
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# 0x003:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
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# 0x004:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
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# 0x005:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
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# 0x006:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
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# 0x007:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
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# 0x008:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
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# 0x009:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
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# 0x00A:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
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# 0x00B:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
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# 0x00C:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
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# 0x00D:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
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# 0x00E:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
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# 0x00F:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
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# 0x010: JMP 0x010
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
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# 0x011: RETI
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
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# Assembled from dctest.jsm
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# ---------------------------------------------------------------
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# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
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# User 2
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set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
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||||
exit
|
||||
@@ -1,858 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; PROJECT "itest"
|
||||
; -------------------------------------------------
|
||||
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
xmem
|
||||
msg: dc "Hallo", 0
|
||||
xram: db 256
|
||||
|
||||
cmem 0
|
||||
cram: db 256
|
||||
|
||||
reg_revision: equ 0x00
|
||||
reg_testid: equ 0x01
|
||||
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
int_vec: jmp isr
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x010
|
||||
|
||||
start: call init
|
||||
cin R0, (cpu_revision)
|
||||
xout (reg_revision), R0
|
||||
|
||||
; Test 0
|
||||
call test0
|
||||
|
||||
; Test 1
|
||||
mov R0, 1
|
||||
xout (reg_testid), R0
|
||||
call test1
|
||||
|
||||
; Test 2
|
||||
mov R0, 2
|
||||
xout (reg_testid), R0
|
||||
call test2
|
||||
|
||||
; Test 3
|
||||
mov R0, 3
|
||||
xout (reg_testid), R0
|
||||
call test3
|
||||
|
||||
; Test 4
|
||||
mov R0, 4
|
||||
xout (reg_testid), R0
|
||||
call test4
|
||||
|
||||
; Test 5
|
||||
mov R0, 5
|
||||
xout (reg_testid), R0
|
||||
call test5
|
||||
|
||||
; Test 6
|
||||
mov R0, 6
|
||||
xout (reg_testid), R0
|
||||
call test6
|
||||
|
||||
; Test 7
|
||||
mov R0, 7
|
||||
xout (reg_testid), R0
|
||||
call test7
|
||||
|
||||
; Test 8
|
||||
mov R0, 8
|
||||
xout (reg_testid), R0
|
||||
call test8
|
||||
|
||||
; Test 9
|
||||
mov R0, 9
|
||||
xout (reg_testid), R0
|
||||
call test9
|
||||
|
||||
; Test 10
|
||||
mov R0, 10
|
||||
xout (reg_testid), R0
|
||||
call test10
|
||||
|
||||
; Test 11
|
||||
mov R0, 11
|
||||
xout (reg_testid), R0
|
||||
call test11
|
||||
|
||||
; Test 12
|
||||
mov R0, 12
|
||||
xout (reg_testid), R0
|
||||
call test12
|
||||
|
||||
; End of test
|
||||
mov R0, 0xFF
|
||||
xout (reg_testid), R0
|
||||
|
||||
jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
mov R3, 0
|
||||
mov R4, 0
|
||||
mov R5, 0
|
||||
mov R6, 0
|
||||
mov R7, 0
|
||||
mov R8, 0
|
||||
mov R9, 0
|
||||
mov R10, 0
|
||||
mov R11, 0
|
||||
mov R12, 0
|
||||
mov R13, 0
|
||||
mov R14, 0
|
||||
mov R15, 0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOV|R|K
|
||||
; MOV|R|R
|
||||
test0: mov R0, 0x10
|
||||
cmp R0, 0x10
|
||||
jne error
|
||||
add R0, 1
|
||||
|
||||
mov R1, R0
|
||||
cmp R1, 0x11
|
||||
jne error
|
||||
add R1, 1
|
||||
|
||||
mov R2, R1
|
||||
cmp R2, 0x12
|
||||
jne error
|
||||
add R2, 1
|
||||
|
||||
mov R3, R2
|
||||
cmp R3, 0x13
|
||||
jne error
|
||||
add R3, 1
|
||||
|
||||
mov R4, R3
|
||||
cmp R4, 0x14
|
||||
jne error
|
||||
add R4, 1
|
||||
|
||||
mov R5, R4
|
||||
cmp R5, 0x15
|
||||
jne error
|
||||
add R5, 1
|
||||
|
||||
mov R6, R5
|
||||
cmp R6, 0x16
|
||||
jne error
|
||||
add R6, 1
|
||||
|
||||
mov R7, R6
|
||||
cmp R7, 0x17
|
||||
jne error
|
||||
add R7, 1
|
||||
|
||||
mov R8, R7
|
||||
cmp R8, 0x18
|
||||
jne error
|
||||
add R8, 1
|
||||
|
||||
mov R9, R8
|
||||
cmp R9, 0x19
|
||||
jne error
|
||||
add R9, 1
|
||||
|
||||
mov R10, R9
|
||||
cmp R10, 0x1A
|
||||
jne error
|
||||
add R10, 1
|
||||
|
||||
mov R11, R10
|
||||
cmp R11, 0x1B
|
||||
jne error
|
||||
add R11, 1
|
||||
|
||||
mov R12, R11
|
||||
cmp R12, 0x1C
|
||||
jne error
|
||||
add R12, 1
|
||||
|
||||
mov R13, R12
|
||||
cmp R13, 0x1D
|
||||
jne error
|
||||
add R13, 1
|
||||
|
||||
mov R14, R13
|
||||
cmp R14, 0x1E
|
||||
jne error
|
||||
add R14, 1
|
||||
|
||||
mov R15, R14
|
||||
cmp R15, 0x1F
|
||||
jne error
|
||||
add R15, 1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Instruction test
|
||||
; TST|R
|
||||
; CMP|R|K
|
||||
; JNZ|K
|
||||
; JC|K
|
||||
; JNE|K
|
||||
; JLT|K
|
||||
; JGT|K
|
||||
; JLE|K
|
||||
; JGE|K
|
||||
; JMP|K
|
||||
test1: mov R0, 0 ; R0 <= 0
|
||||
tst R0
|
||||
jnz error
|
||||
jc error
|
||||
cmp R0, 0
|
||||
jne error
|
||||
jlt error
|
||||
jgt error
|
||||
jle t1_ok10
|
||||
jmp error
|
||||
|
||||
t1_ok10: jeq t1_ok20
|
||||
jmp error
|
||||
|
||||
t1_ok20: jge t1_ok30
|
||||
jmp error
|
||||
|
||||
t1_ok30: cmp R0, 0x55
|
||||
jeq error
|
||||
jlt t1_ok40
|
||||
jmp error
|
||||
|
||||
t1_ok40: jle t1_ok50
|
||||
jmp error
|
||||
|
||||
t1_ok50: jge error
|
||||
jgt error
|
||||
|
||||
mov R0, 0x55 ; R0 <= 0xAA
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0xAA
|
||||
jeq error
|
||||
jne t1_ok60
|
||||
jmp error
|
||||
|
||||
t1_ok60: jlt t1_ok70
|
||||
jmp error
|
||||
|
||||
t1_ok70: jle t1_ok80
|
||||
jmp error
|
||||
|
||||
t1_ok80: jgt error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq t1_ok90
|
||||
jmp error
|
||||
|
||||
t1_ok90: jne error
|
||||
jlt error
|
||||
|
||||
jle t1_ok100
|
||||
jmp error
|
||||
|
||||
t1_ok100: jgt error
|
||||
jge t1_ok110
|
||||
jmp error
|
||||
|
||||
t1_ok110: mov R0, 0xAA ; R0 <= 0x55
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq error
|
||||
jne t1_ok120
|
||||
jmp error
|
||||
|
||||
t1_ok120: jgt t1_ok130
|
||||
jmp error
|
||||
|
||||
t1_ok130: jge t1_ok140
|
||||
jmp error
|
||||
|
||||
t1_ok140: jlt error
|
||||
jle error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; ADD|R|K
|
||||
; ADDC|R|K
|
||||
; ToDo: ADD|R|R
|
||||
; ToDo: ADDC|R|R
|
||||
; CMP|R|R
|
||||
test2: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t2_loop: add R0, 0x01
|
||||
addc R1, 0x00
|
||||
add R2, 1
|
||||
cmp R2, 0
|
||||
jne t2_L1
|
||||
add R3, 1
|
||||
cmp R3, 0x02
|
||||
t2_L1: jne t2_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; SUB|R|K
|
||||
; SUBC|R|K
|
||||
; ToDo: SUB|R|R
|
||||
; ToDo: SUBC|R|R
|
||||
; CMP|R|R
|
||||
test3: mov R0, 0x00
|
||||
mov R1, 0x03
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t3_loop: sub R0, 0x01
|
||||
subc R1, 0x00
|
||||
sub R2, 1
|
||||
cmp R2, 0xFF
|
||||
jne t3_L1
|
||||
sub R3, 1
|
||||
cmp R3, 0x00
|
||||
t3_L1: jne t3_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
; -------------------------------------------------
|
||||
; SUB|K|R
|
||||
; SUB|R|R
|
||||
; SUBC|R|R
|
||||
; SUBC|K|R
|
||||
; CMP|R|R
|
||||
test4: mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub 0x05, R0
|
||||
sub R1, 0x03
|
||||
cmp R0, R1
|
||||
jne error
|
||||
mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub R0, R1
|
||||
subc 0, R0
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
add R0, 0
|
||||
subc R1, R0
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVC|R|Ri
|
||||
; MOVC|R|Ki
|
||||
; MOVC|Ri|R
|
||||
; MOVC|Ri|K
|
||||
; MOVC|Ki|R
|
||||
test5: mov R0, 1
|
||||
movc (cram+0x5A), R0
|
||||
dec R0
|
||||
movc (cram+0), R0
|
||||
movc R1, (cram+0x5A)
|
||||
movc (R1), 0xA5
|
||||
movc R0, (R1)
|
||||
movc R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movc R0, (R1)
|
||||
t5_loop1: movc (R0), R0
|
||||
movc R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movc (R2), R1
|
||||
movc R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t5_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVX|R|Ri
|
||||
; MOVX|R|Ki
|
||||
; MOVX|Ri|R
|
||||
; MOVX|Ri|K
|
||||
; MOVX|Ki|R
|
||||
test6: mov R0, 1
|
||||
movx (xram+0x5A), R0
|
||||
dec R0
|
||||
movx (xram+0), R0
|
||||
movx R1, (xram+0x5A)
|
||||
movx (R1), 0xA5
|
||||
movx R0, (R1)
|
||||
movx R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movx R0, (R1)
|
||||
t6_loop1: movx (R0), R0
|
||||
movx R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movx (R2), R1
|
||||
movx R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t6_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PUSH|R
|
||||
; POP|R
|
||||
test7: mov R0, 0xAA
|
||||
mov R1, 0
|
||||
t7_loop1: push R0
|
||||
inc R0
|
||||
dec R1
|
||||
jnz t7_loop1
|
||||
t7_loop2: pop R0
|
||||
dec R1
|
||||
jnz t7_loop2
|
||||
cmp R0, 0xAA
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; JMP|K
|
||||
; CALL|K
|
||||
; RET
|
||||
test8: mov R0, 0x55
|
||||
push R0
|
||||
mov R0, 0
|
||||
mov R1, 0xFF
|
||||
call t8_rec
|
||||
pop R0
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
; Stack manipulations 1
|
||||
mov R0, return1'high
|
||||
mov R1, return1'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
ret
|
||||
|
||||
; Stack manipulations 2
|
||||
return1: mov R0, return2'high
|
||||
mov R1, return2'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
return2: ret
|
||||
|
||||
t8_rec: cmp R0, R1
|
||||
jeq ex_t8_rec
|
||||
inc R0
|
||||
jmp t8_rstub
|
||||
ex_t8_rec: dec R0
|
||||
dec R1
|
||||
ret
|
||||
|
||||
t8_rstub: call t8_rec
|
||||
jmp ex_t8_rec
|
||||
|
||||
; -------------------------------------------------
|
||||
; SWAP|R
|
||||
; SHL|R
|
||||
; SHR|R
|
||||
; ROL|R
|
||||
; ROR|R
|
||||
; ROLC|R
|
||||
; RORC|R
|
||||
test9: mov R0, 0xA5 ; SWAP test
|
||||
mov R1, 0x5A
|
||||
swap R0
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
swap R0
|
||||
cmp R0, 0xA5
|
||||
jne error
|
||||
mov R0, 0xD2
|
||||
swap R0
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
swap R1
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
cmp R1, 0xA5
|
||||
jne error
|
||||
|
||||
mov R0, 0x2D
|
||||
shl R0 ; SHL test
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xB4
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x68
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xD0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xA0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x40
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x80
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x00
|
||||
jne error
|
||||
|
||||
mov R1, 0x84
|
||||
shr R1 ; SHR test
|
||||
cmp R1, 0x42
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x21
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x10
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x08
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x02
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x01
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x00
|
||||
jne error
|
||||
|
||||
mov R0, 0xC5 ; ROL test
|
||||
rol R0
|
||||
cmp R0, 0x8B
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x17
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x2E
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x5C
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xB8
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x71
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xE2
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xC5
|
||||
jne error
|
||||
|
||||
mov R1, 0x63 ; ROR test
|
||||
ror R1
|
||||
cmp R1, 0xB1
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xD8
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x6C
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x36
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x1B
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x8D
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x63
|
||||
jne error
|
||||
|
||||
|
||||
xor R0, R0 ; ROLC generate
|
||||
mov R0, 0xC5
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
|
||||
cmp R0, 0xC5 ; ROLC verify
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x62
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xB1
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x58
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xAC
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x56
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x2B
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x15
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x8A
|
||||
jne error
|
||||
|
||||
xor R1, R1 ; RORC generate
|
||||
mov R1, 0x63
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
|
||||
cmp R1, 0x63 ; RORC verify
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x8C
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x19
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x33
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x66
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xCC
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x98
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x31
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; AND|R|R
|
||||
; AND|R|K
|
||||
; OR|R|R
|
||||
; OR|R|K
|
||||
; XOR|R|R
|
||||
; XOR|R|K
|
||||
test10: mov R0, 0xA5 ; AND
|
||||
swap R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
jne error
|
||||
pop R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
pop R1
|
||||
jne error
|
||||
swap R1
|
||||
mov R2, 0x0F
|
||||
and R1, R2
|
||||
cmp R1, 0x05
|
||||
jne error
|
||||
|
||||
mov R0, 0x05 ; OR
|
||||
mov R2, 0xA0
|
||||
swap R0
|
||||
or R2, R0
|
||||
cmp R2, 0xF0
|
||||
jne error
|
||||
swap R0
|
||||
or R0, 0x50
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
mov R1, 0x01
|
||||
mov R0, 0x01
|
||||
xor R0, 0x01
|
||||
jnz error
|
||||
xor R0, R1
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
test11:
|
||||
mov R0, 0x03
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
xin R0, (2)
|
||||
or R0, 1
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
xin R0, (2)
|
||||
and R0, 0xFE
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Tests clrc, setc
|
||||
test12: sub R0, 0
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
sub R0, 0
|
||||
jc error
|
||||
|
||||
mov R0, 0
|
||||
clrc
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
clrc
|
||||
jc error
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
isr: inc R14
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x3FF
|
||||
error: jmp error
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x2FF
|
||||
ok: jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,50 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -1,29 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp init
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x45
|
||||
mov R1, 0xF5
|
||||
|
||||
call mul8x8
|
||||
stop: jmp stop
|
||||
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../jasm/mul8x8.inc.jsm"
|
||||
|
||||
|
||||
|
||||
@@ -1,154 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x001
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
|
||||
|
||||
# 0x001: MOV R00, 0x45
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
|
||||
|
||||
# 0x002: MOV R01, 0xF5
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
|
||||
|
||||
# 0x003: CALL 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
|
||||
|
||||
# 0x004: JMP 0x004
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
|
||||
|
||||
# 0x005: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
|
||||
|
||||
# 0x006: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
|
||||
|
||||
# 0x007: PUSH R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
|
||||
|
||||
# 0x008: MOV R04, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
|
||||
|
||||
# 0x009: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
|
||||
|
||||
# 0x00A: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
|
||||
|
||||
# 0x00B: MOV R03, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
|
||||
|
||||
# 0x00C: CMP R04, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
|
||||
|
||||
# 0x00D: JEQ 0x015
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
|
||||
|
||||
# 0x00E: SHR R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
|
||||
|
||||
# 0x00F: JNC 0x012
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
|
||||
|
||||
# 0x010: ADD R02, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
|
||||
|
||||
# 0x011: ADDC R03, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
|
||||
|
||||
# 0x012: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
|
||||
|
||||
# 0x013: ROLC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
|
||||
|
||||
# 0x014: JMP 0x00C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
|
||||
|
||||
# 0x015: ADD R00, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
|
||||
|
||||
# 0x016: ADDC R01, R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
|
||||
|
||||
# 0x017: POP R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
|
||||
|
||||
# 0x01A: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
|
||||
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,50 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
cpu_revision: equ 0x00 ; RO
|
||||
cpu_control: equ 0x01 ; R/W
|
||||
cpu_status: equ 0x02 ; RO
|
||||
cpu_int_ctrl: equ 0x03 ; R/W
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
; nop
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x05
|
||||
cout (cpu_int_ctrl), R0
|
||||
mov R0, 0x00
|
||||
loop: nop
|
||||
inc R0
|
||||
nop
|
||||
call subr
|
||||
nop
|
||||
push R3
|
||||
nop
|
||||
push R2
|
||||
nop
|
||||
push R1
|
||||
nop
|
||||
push R0
|
||||
nop
|
||||
pop R0
|
||||
nop
|
||||
pop R1
|
||||
nop
|
||||
pop R2
|
||||
nop
|
||||
pop R3
|
||||
nop
|
||||
jmp loop
|
||||
|
||||
subr: ret
|
||||
@@ -1,157 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: MOV R00, 0x05
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
|
||||
|
||||
# 0x003: COUT (0x03), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
|
||||
|
||||
# 0x004: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
|
||||
|
||||
# 0x005: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
|
||||
|
||||
# 0x006: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
|
||||
|
||||
# 0x007: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
|
||||
|
||||
# 0x008: CALL 0x01B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
|
||||
|
||||
# 0x009: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
|
||||
|
||||
# 0x00A: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
|
||||
|
||||
# 0x00B: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
|
||||
|
||||
# 0x00C: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
|
||||
|
||||
# 0x00D: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
|
||||
|
||||
# 0x00E: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
|
||||
|
||||
# 0x00F: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
|
||||
|
||||
# 0x010: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
|
||||
|
||||
# 0x011: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
|
||||
|
||||
# 0x012: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
|
||||
|
||||
# 0x013: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
|
||||
|
||||
# 0x014: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
|
||||
|
||||
# 0x015: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
|
||||
|
||||
# 0x016: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
|
||||
|
||||
# 0x017: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
|
||||
|
||||
# 0x01A: JMP 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
|
||||
|
||||
# 0x01B: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
|
||||
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 7.8 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 3.5 KiB |
@@ -1,674 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
of the GPL, as needed to protect the freedom of users.
|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
software on general-purpose computers, but in those that do, we wish to
|
||||
avoid the special danger that patents applied to a free program could
|
||||
make it effectively proprietary. To prevent this, the GPL assures that
|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/test_irom.vhdl"
|
||||
vcom -explicit -93 "../src/core/tb_cpu.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 50us
|
||||
@@ -1,107 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/ce
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
|
||||
add wave -noupdate -format Logic /tb_cpu/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_we
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/io_sel
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -divider CPU
|
||||
add wave -noupdate -format Literal /tb_cpu/reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/status_reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/alu_status
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_we
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_save
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_restore
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
|
||||
add wave -noupdate -divider Stack
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -divider Chipram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -divider Sequencer
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
|
||||
add wave -noupdate -divider {Chip register}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
|
||||
configure wave -namecolwidth 166
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {93532 ps} {206468 ps}
|
||||
@@ -1,21 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/tb_cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/test_irom.vhdl"
|
||||
vsim -t 1ps -lib work tb_cpu_embedded
|
||||
do {tb_cpu_embedded.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -1,26 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/rst
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/clk
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
|
||||
configure wave -namecolwidth 143
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {10500 ns}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/itest_irom.vhdl"
|
||||
vcom -explicit -93 "../src/tb_cpu_itest.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu_itest.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 400us
|
||||
@@ -1,123 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/ce
|
||||
add wave -noupdate -format Logic /tb_cpu/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/int_ack
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_we
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_re
|
||||
add wave -noupdate -format Logic /tb_cpu/xmem_wait
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/io_sel
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
|
||||
add wave -noupdate -divider CPU
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/status_reg
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/alu_status
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_we
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_save
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/status_restore
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
|
||||
add wave -noupdate -divider Stack
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -divider Chipram
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -divider Sequencer
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
|
||||
add wave -noupdate -divider {Chip register}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/clk
|
||||
add wave -noupdate -divider {Interrup Ctrl.}
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
|
||||
add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {53866171 ps} 0}
|
||||
configure wave -namecolwidth 166
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {420 us}
|
||||
@@ -1,22 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/chipreg.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/irom_reti_issue.vhdl"
|
||||
vcom -explicit -93 "../src/core/tb_cpu.vhd"
|
||||
vsim -t 1ps -lib work tb_cpu
|
||||
do {tb_cpu_reti_issue.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 50us
|
||||
@@ -1,82 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
|
||||
add wave -noupdate -divider {Chip RAM}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
|
||||
add wave -noupdate -divider {Interrupt controller}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
|
||||
add wave -noupdate -divider PC
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
|
||||
add wave -noupdate -divider {Stack controller}
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/iphase
|
||||
add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {8115990 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {8048536 ps} {8340629 ps}
|
||||
@@ -1,21 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/core/cpu_pkg.vhd"
|
||||
vcom -explicit -93 "../src/core/stack_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/reg_dual.vhd"
|
||||
vcom -explicit -93 "../src/core/chipram.vhd"
|
||||
vcom -explicit -93 "../src/core/pc.vhd"
|
||||
vcom -explicit -93 "../src/core/dpath_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/int_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/core/alu.vhd"
|
||||
vcom -explicit -93 "../src/core/cpu.vhd"
|
||||
vcom -explicit -93 "../src/cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/tb_cpu_embedded.vhd"
|
||||
vcom -explicit -93 "../src/mul8x8_irom.vhdl"
|
||||
vsim -t 1ps -lib work tb_cpu_embedded
|
||||
do {tb_mul8x8.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
@@ -1,31 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
|
||||
add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
|
||||
add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
|
||||
configure wave -namecolwidth 143
|
||||
configure wave -valuecolwidth 101
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {9002500 ps} {10052500 ps}
|
||||
@@ -1,236 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The arithmetic logic unit
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity alu is
|
||||
Generic (
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
op_en : in STD_LOGIC;
|
||||
cy_in : in STD_LOGIC;
|
||||
op1_in : in unsigned (data_width-1 downto 0);
|
||||
op2_in : in unsigned (data_width-1 downto 0);
|
||||
opsel : in alu_op_t;
|
||||
res_out : out unsigned (data_width-1 downto 0);
|
||||
stat_load : in STD_LOGIC;
|
||||
stat_in : in alu_status_t;
|
||||
stat_out : out alu_status_t
|
||||
);
|
||||
end alu;
|
||||
|
||||
architecture Behavioral of alu is
|
||||
|
||||
signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
|
||||
signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
|
||||
signal status, stat_reg : alu_status_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function test_zero(arg : unsigned) return STD_LOGIC is
|
||||
variable result : STD_LOGIC;
|
||||
begin
|
||||
result := '0';
|
||||
for i in arg'range loop
|
||||
result := result or To_X01(arg(i));
|
||||
end loop;
|
||||
|
||||
return not result;
|
||||
end test_zero;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_logic_func:
|
||||
process (op1_in, op2_in, opsel)
|
||||
begin
|
||||
|
||||
case opsel is
|
||||
when op1_and_op2 =>
|
||||
lf_res <= op1_in and op2_in;
|
||||
when op1_or_op2 =>
|
||||
lf_res <= op1_in or op2_in;
|
||||
when op1_xor_op2 =>
|
||||
lf_res <= op1_in xor op2_in;
|
||||
when others =>
|
||||
lf_res <= (others => '-');
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_shift_func:
|
||||
process (op1_in, left_shift, sh_cy_in)
|
||||
begin
|
||||
if left_shift = '1' then
|
||||
sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
|
||||
sh_cy <= op1_in(op1_in'left);
|
||||
else
|
||||
sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
|
||||
sh_cy <= op1_in(op1_in'right);
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_alu_out:
|
||||
process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
|
||||
|
||||
begin
|
||||
|
||||
case opsel is
|
||||
|
||||
when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= sum_cy;
|
||||
result <= sum_res;
|
||||
when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= stat_reg.carry;
|
||||
result <= lf_res;
|
||||
when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
|
||||
status.zero <= test_zero(res_reg);
|
||||
status.carry <= sh_cy;
|
||||
result <= sh_res;
|
||||
when swap_op =>
|
||||
result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
|
||||
status <= stat_reg;
|
||||
when others =>
|
||||
result <= op2_in;
|
||||
status.zero <= stat_reg.zero;
|
||||
status.carry <= stat_reg.carry or cy_in;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_alu_in:
|
||||
process(opsel, op1_in, stat_reg)
|
||||
|
||||
begin
|
||||
|
||||
add_subn <= '-';
|
||||
sum_cy_in <= '-';
|
||||
sh_cy_in <= '-';
|
||||
left_shift <= '-';
|
||||
|
||||
case opsel is
|
||||
|
||||
when op1_add_op2 =>
|
||||
sum_cy_in <= '0';
|
||||
add_subn <= '1';
|
||||
|
||||
when op1_sub_op2 =>
|
||||
sum_cy_in <= '0';
|
||||
add_subn <= '0';
|
||||
|
||||
when op1_addc_op2 =>
|
||||
sum_cy_in <= stat_reg.carry;
|
||||
add_subn <= '1';
|
||||
|
||||
when op1_subc_op2 =>
|
||||
sum_cy_in <= stat_reg.carry;
|
||||
add_subn <= '0';
|
||||
|
||||
when shl_op =>
|
||||
sh_cy_in <= '0';
|
||||
left_shift <= '1';
|
||||
|
||||
when shr_op =>
|
||||
sh_cy_in <= '0';
|
||||
left_shift <= '0';
|
||||
|
||||
when rol_op =>
|
||||
sh_cy_in <= op1_in(op1_in'left);
|
||||
left_shift <= '1';
|
||||
|
||||
when ror_op =>
|
||||
sh_cy_in <= op1_in(op1_in'right);
|
||||
left_shift <= '0';
|
||||
|
||||
when rolc_op =>
|
||||
sh_cy_in <= stat_reg.carry;
|
||||
left_shift <= '1';
|
||||
|
||||
when rorc_op =>
|
||||
sh_cy_in <= stat_reg.carry;
|
||||
left_shift <= '0';
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
proc_res_reg:
|
||||
process(clk, rst, op_en, stat_load, res_reg, stat_reg)
|
||||
begin
|
||||
if rst = '1' then
|
||||
res_reg <= (others => '0');
|
||||
stat_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if op_en = '1' then
|
||||
res_reg <= result;
|
||||
stat_reg <= status;
|
||||
elsif stat_load = '1' then
|
||||
stat_reg <= stat_in;
|
||||
end if;
|
||||
end if;
|
||||
res_out <= res_reg;
|
||||
stat_out <= stat_reg;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
alu_addsub:
|
||||
process(op1_in, op2_in, sum_cy_in, add_subn)
|
||||
variable sum : unsigned(data_width+1 downto 0);
|
||||
variable op1, op2 : unsigned(data_width+1 downto 0);
|
||||
begin
|
||||
if add_subn = '1' then
|
||||
op1 := '0' & op1_in & '1';
|
||||
op2 := '0' & op2_in & sum_cy_in;
|
||||
sum := op1 + op2;
|
||||
else
|
||||
op1 := '0' & op1_in & not sum_cy_in;
|
||||
op2 := '0' & op2_in & '1';
|
||||
sum := op1 - op2;
|
||||
end if;
|
||||
|
||||
-- Form sum + carry
|
||||
sum_res <= sum(data_width downto 1);
|
||||
sum_cy <= sum(sum'left);
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,85 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: On-chip RAM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity chipram is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end chipram;
|
||||
|
||||
architecture Behavioral of chipram is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,123 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: On-Chip registers
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity chipreg is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
din : in dmem_data_t;
|
||||
dout : out dmem_data_t;
|
||||
ctrl_in : in creg_ctrl_in_t;
|
||||
ctrl_out : out creg_ctrl_out_t
|
||||
);
|
||||
end chipreg;
|
||||
|
||||
architecture Behavioral of chipreg is
|
||||
|
||||
signal reg_page_sel : page_sel_t;
|
||||
signal reg_int_ctrl : int_ctrl_in_t;
|
||||
signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
proc_assign_ctrl_lines:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
ctrl_out.page_sel <= reg_page_sel;
|
||||
ctrl_out.int_ctrl <= reg_int_ctrl;
|
||||
ctrl_out.stk_high <= reg_stk_high;
|
||||
ctrl_out.cmem_high <= reg_cmem_high;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_write:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
reg_stk_high <= (others => '0');
|
||||
reg_cmem_high <= (others => '0');
|
||||
reg_page_sel <= (others => '0');
|
||||
reg_int_ctrl.enable <= '0';
|
||||
reg_int_ctrl.polarity <= '1';
|
||||
reg_int_ctrl.edge_sens <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
reg_int_ctrl.request <= '0';
|
||||
if we = '1' then
|
||||
case addr is
|
||||
when X"01" =>
|
||||
reg_page_sel(page_sel_t'range) <= din(page_sel_t'range);
|
||||
when X"03" =>
|
||||
reg_int_ctrl.enable <= din(0);
|
||||
reg_int_ctrl.polarity <= din(1);
|
||||
reg_int_ctrl.edge_sens <= din(2);
|
||||
reg_int_ctrl.request <= din(7);
|
||||
when X"04" =>
|
||||
reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
when X"05" =>
|
||||
reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_reg_read:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
case addr is
|
||||
when X"00" => -- Revison
|
||||
dout <= to_unsigned(REVISION, dmem_data_t'length);
|
||||
when X"01" => -- Control 0
|
||||
dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
|
||||
when X"02" => -- CPU status
|
||||
dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
|
||||
when X"03" => -- Interrupt control
|
||||
dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
|
||||
when X"04" => -- Upper stack bits out
|
||||
dout <= "0000" & reg_cmem_high;
|
||||
when X"05" => -- Upper cmem bits out
|
||||
dout <= "0000" & reg_stk_high;
|
||||
when others =>
|
||||
if addr(0) = '0' then
|
||||
dout <= X"DE";
|
||||
else
|
||||
dout <= X"AD";
|
||||
end if;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,566 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: JCPU top file
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity cpu is
|
||||
Generic (
|
||||
use_instr_register : boolean := false;
|
||||
use_ctrl_rom : boolean := true
|
||||
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_wait : in STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out std_logic
|
||||
);
|
||||
end cpu;
|
||||
|
||||
architecture rtl of cpu is
|
||||
|
||||
COMPONENT stack_ctrl
|
||||
GENERIC (
|
||||
addr_width : integer
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
push : in STD_LOGIC;
|
||||
pop : in STD_LOGIC;
|
||||
din : in inst_addr_t;
|
||||
dout : out inst_addr_t;
|
||||
mem_we : out STD_LOGIC;
|
||||
ptr_out : out unsigned (addr_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pc
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
inc : in STD_LOGIC;
|
||||
load : in STD_LOGIC;
|
||||
pc_in : in inst_addr_t;
|
||||
pc_out : out inst_addr_t;
|
||||
pc_next : out inst_addr_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dpath_ctrl
|
||||
GENERIC (
|
||||
use_rom : boolean
|
||||
);
|
||||
Port (
|
||||
inst_in : in inst_t;
|
||||
iphase_in : in iphase_t;
|
||||
status_in : in cpu_status_t;
|
||||
ctrl_out : out dpath_ctrl_out_t;
|
||||
idout : out inst_addr_t;
|
||||
ddout : out dmem_data_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT int_ctrl
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ctrl_in : in int_ctrl_in_t;
|
||||
int_in : in STD_LOGIC;
|
||||
int_exit : in STD_LOGIC;
|
||||
iphase_in : in iphase_t;
|
||||
int_ack_out : out STD_LOGIC;
|
||||
stat_save_out : out STD_LOGIC;
|
||||
stat_rest_out : out STD_LOGIC;
|
||||
pc_addr_out : out inst_addr_t;
|
||||
pc_load_out : out STD_LOGIC;
|
||||
stk_push_out : out STD_LOGIC;
|
||||
stk_pop_out : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT reg_dual
|
||||
GENERIC (
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
ptr_a : in reg_ptr_t;
|
||||
ptr_b : in reg_ptr_t;
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT chipram
|
||||
GENERIC (
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT chipreg
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
din : in dmem_data_t;
|
||||
dout : out dmem_data_t;
|
||||
ctrl_in : in creg_ctrl_in_t;
|
||||
ctrl_out : out creg_ctrl_out_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT alu
|
||||
GENERIC (
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
op_en : in STD_LOGIC;
|
||||
cy_in : in STD_LOGIC;
|
||||
op1_in : in unsigned (data_width-1 downto 0);
|
||||
op2_in : in unsigned (data_width-1 downto 0);
|
||||
opsel : in alu_op_t;
|
||||
res_out : out unsigned (data_width-1 downto 0);
|
||||
stat_load : in STD_LOGIC;
|
||||
stat_in : in alu_status_t;
|
||||
stat_out : out alu_status_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
|
||||
signal ctrl : dpath_ctrl_out_t;
|
||||
signal stk_out : inst_addr_t;
|
||||
signal stk_in : inst_addr_t;
|
||||
signal stk_reg : inst_addr_t;
|
||||
signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
|
||||
signal iphase : iphase_t;
|
||||
signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
|
||||
signal reg_din : dmem_data_t;
|
||||
signal alu_op1, alu_op2, alu_result : dmem_data_t;
|
||||
signal alu_status : alu_status_t;
|
||||
signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
|
||||
signal ctrl_inst : inst_t;
|
||||
signal ctrl_iphase : iphase_t;
|
||||
signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
|
||||
signal status_save, status_restore : STD_LOGIC;
|
||||
signal creg_dout : dmem_data_t;
|
||||
signal cmem_din, cmem_dout : inst_addr_t;
|
||||
signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
|
||||
signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
|
||||
signal creg_ctrl_out : creg_ctrl_out_t;
|
||||
signal creg_ctrl_in : creg_ctrl_in_t;
|
||||
signal irq_out : std_logic;
|
||||
signal xio_sel, cio_sel : std_logic;
|
||||
signal mem_data : dmem_data_t;
|
||||
signal mem_addr : dmem_data_t;
|
||||
|
||||
begin
|
||||
io_sel <= xio_sel;
|
||||
instr_addr <= pc_out;
|
||||
pc_inc <= cpu_active and ctrl.lines.pc_inc;
|
||||
stk_addr <= '0' & stk_ptr;
|
||||
cpu_status.alu <= alu_status;
|
||||
cpu_status.xmem_wait <= xmem_wait;
|
||||
creg_ctrl_in.alu <= alu_status;
|
||||
|
||||
xmem_dout <= mem_data;
|
||||
xmem_addr <= mem_addr;
|
||||
cmem_din <= creg_ctrl_out.cmem_high & mem_data;
|
||||
cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0);
|
||||
|
||||
--------------------------------------------------------------------
|
||||
mem_ctrl_lines:
|
||||
process(ctrl.lines)
|
||||
begin
|
||||
xio_sel <= '0';
|
||||
xmem_re <= '0';
|
||||
xmem_we <= '0';
|
||||
cio_sel <= '0';
|
||||
cmem_we <= '0';
|
||||
creg_we <= '0';
|
||||
|
||||
case ctrl.lines.mem_access is
|
||||
when xmem_access =>
|
||||
xmem_re <= ctrl.lines.mem_read;
|
||||
xmem_we <= ctrl.lines.mem_write;
|
||||
when xio_access =>
|
||||
xio_sel <= '1';
|
||||
xmem_re <= ctrl.lines.mem_read;
|
||||
xmem_we <= ctrl.lines.mem_write;
|
||||
when cmem_access =>
|
||||
cmem_we <= ctrl.lines.mem_write;
|
||||
when cio_access =>
|
||||
cio_sel <= '1';
|
||||
creg_we <= ctrl.lines.mem_write;
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
iphase_counter:
|
||||
process(rst, clk, ce)
|
||||
variable pos : integer;
|
||||
begin
|
||||
if rst = '1' then
|
||||
iphase <= iphase_t'low;
|
||||
cpu_active <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
cpu_active <= '0';
|
||||
if ce = '1' then
|
||||
cpu_active <= '1';
|
||||
if iphase = iphase_t'high then
|
||||
iphase <= iphase_t'low;
|
||||
else
|
||||
iphase <= iphase + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gen_instr_reg:
|
||||
if use_instr_register = true generate
|
||||
|
||||
instr_reg:
|
||||
process (rst, clk, ce)
|
||||
begin
|
||||
if rst = '1' then
|
||||
ctrl_inst <= (others => '0');
|
||||
ctrl_iphase <= 0;
|
||||
elsif rising_edge(clk) and ce = '1' then
|
||||
ctrl_inst <= instr_din;
|
||||
ctrl_iphase <= iphase;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end generate;
|
||||
|
||||
gen_instr_direct:
|
||||
if use_instr_register = false generate
|
||||
|
||||
ctrl_inst <= instr_din;
|
||||
ctrl_iphase <= iphase;
|
||||
|
||||
end generate;
|
||||
|
||||
status_register:
|
||||
process(clk, status_save)
|
||||
begin
|
||||
if rising_edge(clk) and status_save = '1' then
|
||||
status_reg.alu <= alu_status;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pc_pushpop:
|
||||
process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
|
||||
begin
|
||||
pc_load <= ctrl.lines.pc_load or int_pc_load;
|
||||
stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc);
|
||||
stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load);
|
||||
end process;
|
||||
|
||||
lines_delay:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
was_pcld <= ctrl.lines.pc_load;
|
||||
was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
stk_mux:
|
||||
process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
|
||||
begin
|
||||
if was_pcld = '1' and int_stk_push = '1' then
|
||||
stk_in <= idata;
|
||||
elsif ctrl.lines.stk_pushd = '1' then
|
||||
stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
|
||||
else
|
||||
stk_in <= pc_next;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
pc_mux:
|
||||
process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
|
||||
begin
|
||||
|
||||
pc_in <= stk_out;
|
||||
if int_pc_load = '1' then
|
||||
if int_stk_pop = '0' then
|
||||
pc_in <= int_pc_addr;
|
||||
end if;
|
||||
elsif ctrl.lines.pc_load = '1' then
|
||||
if ctrl.lines.stk_pop = '0' then
|
||||
pc_in <= idata;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
mem_data_mux:
|
||||
process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
|
||||
begin
|
||||
case ctrl.lines.ddata_src_sel is
|
||||
when reg_a =>
|
||||
mem_data <= reg_a_dout;
|
||||
when reg_b =>
|
||||
mem_data <= reg_b_dout;
|
||||
when const =>
|
||||
mem_data <= const_data;
|
||||
when others =>
|
||||
mem_data <= const_data;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
mem_addr_mux:
|
||||
process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel)
|
||||
begin
|
||||
case ctrl.lines.daddr_src_sel is
|
||||
when reg_a =>
|
||||
mem_addr <= reg_a_dout;
|
||||
when reg_b =>
|
||||
mem_addr <= reg_b_dout;
|
||||
when const =>
|
||||
mem_addr <= const_data;
|
||||
when others =>
|
||||
mem_addr <= const_data;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
reg_in_mux:
|
||||
process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.reg_src_sel is
|
||||
when xmem_src =>
|
||||
data := xmem_din;
|
||||
when cmem_src =>
|
||||
if cio_sel = '0' then
|
||||
data := cmem_dout(dmem_data_t'range);
|
||||
else
|
||||
data := creg_dout(dmem_data_t'range);
|
||||
end if;
|
||||
when stk_src =>
|
||||
data := stk_out(dmem_data_t'range);
|
||||
when others =>
|
||||
data := alu_result;
|
||||
end case;
|
||||
|
||||
reg_din <= data;
|
||||
|
||||
end process;
|
||||
|
||||
alu_op1_mux:
|
||||
process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.alu_op1_src_sel is
|
||||
when reg_a =>
|
||||
data := reg_a_dout;
|
||||
when reg_b =>
|
||||
data := reg_b_dout;
|
||||
when others =>
|
||||
data := const_data;
|
||||
end case;
|
||||
|
||||
alu_op1 <= data;
|
||||
|
||||
end process;
|
||||
|
||||
alu_op2_mux:
|
||||
process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
|
||||
variable data : dmem_data_t;
|
||||
begin
|
||||
case ctrl.lines.alu_op2_src_sel is
|
||||
when reg_a =>
|
||||
data := reg_a_dout;
|
||||
when reg_b =>
|
||||
data := reg_b_dout;
|
||||
when others =>
|
||||
data := const_data;
|
||||
end case;
|
||||
|
||||
alu_op2 <= data;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------
|
||||
inst_stack_ctrl: stack_ctrl
|
||||
GENERIC MAP (
|
||||
addr_width => STACK_SIZE_BITS
|
||||
)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
push => stk_push,
|
||||
pop => stk_pop,
|
||||
dout => stk_reg,
|
||||
din => stk_in,
|
||||
ptr_out => stk_ptr,
|
||||
mem_we => stk_we
|
||||
);
|
||||
|
||||
inst_pc: pc
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
inc => pc_inc,
|
||||
load => pc_load,
|
||||
pc_in => pc_in,
|
||||
pc_out => pc_out,
|
||||
pc_next => pc_next
|
||||
);
|
||||
|
||||
inst_dpath_ctrl: dpath_ctrl
|
||||
GENERIC MAP (
|
||||
use_rom => use_ctrl_rom
|
||||
)
|
||||
PORT MAP(
|
||||
inst_in => ctrl_inst,
|
||||
iphase_in => ctrl_iphase,
|
||||
status_in => cpu_status,
|
||||
ctrl_out => ctrl,
|
||||
ddout => const_data,
|
||||
idout => idata
|
||||
);
|
||||
|
||||
inst_int_ctrl: int_ctrl
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ctrl_in => creg_ctrl_out.int_ctrl,
|
||||
int_in => int_in,
|
||||
int_ack_out => int_ack,
|
||||
int_exit => ctrl.lines.int_exit,
|
||||
iphase_in => ctrl_iphase,
|
||||
stat_save_out => status_save,
|
||||
stat_rest_out => status_restore,
|
||||
pc_addr_out => int_pc_addr,
|
||||
pc_load_out => int_pc_load,
|
||||
stk_push_out => int_stk_push,
|
||||
stk_pop_out => int_stk_pop
|
||||
|
||||
);
|
||||
|
||||
inst_reg_ab: reg_dual
|
||||
GENERIC MAP (
|
||||
addr_width => REG_SIZE_BITS,
|
||||
data_width => DMEM_DATA_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
we_a => ctrl.lines.reg_we,
|
||||
ptr_a => ctrl.reg_a_ptr,
|
||||
ptr_b => ctrl.reg_b_ptr,
|
||||
din_a => reg_din,
|
||||
dout_a => reg_a_dout,
|
||||
dout_b => reg_b_dout
|
||||
);
|
||||
|
||||
inst_chipram: chipram
|
||||
GENERIC MAP (
|
||||
addr_width => CHIPRAM_SIZE_BITS,
|
||||
data_width => IMEM_ADDR_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => cpu_active,
|
||||
en_b => cpu_active,
|
||||
we_a => stk_we,
|
||||
we_b => cmem_we,
|
||||
addr_a => stk_addr,
|
||||
addr_b => cmem_addr,
|
||||
din_a => stk_reg,
|
||||
din_b => cmem_din,
|
||||
dout_a => stk_out,
|
||||
dout_b => cmem_dout
|
||||
);
|
||||
|
||||
inst_chipreg: chipreg
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => creg_we,
|
||||
addr => mem_addr,
|
||||
din => mem_data,
|
||||
dout => creg_dout,
|
||||
ctrl_in => creg_ctrl_in,
|
||||
ctrl_out => creg_ctrl_out
|
||||
);
|
||||
|
||||
inst_alu: alu
|
||||
GENERIC MAP (
|
||||
data_width => DMEM_DATA_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
op_en => ctrl.lines.alu_load,
|
||||
cy_in => ctrl.lines.alu_cy_in,
|
||||
op1_in => alu_op1,
|
||||
op2_in => alu_op2,
|
||||
opsel => ctrl.lines.alu_opsel,
|
||||
res_out => alu_result,
|
||||
stat_load => status_restore,
|
||||
stat_in => status_reg.alu,
|
||||
stat_out => alu_status
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -1,904 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Types, constants and functions for JCPU
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
|
||||
package cpu_pkg is
|
||||
|
||||
-- Revision of the CPU
|
||||
constant REVISION : integer := 4;
|
||||
|
||||
-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
|
||||
constant CHIPRAM_SIZE_BITS : integer := 10;
|
||||
|
||||
-- Chipregister file depth
|
||||
constant CHIPREG_SIZE_BITS : integer := 8;
|
||||
|
||||
-- Number of registers (16 registers fixed)
|
||||
constant REG_SIZE_BITS : integer := 4;
|
||||
|
||||
-- Instruction memory
|
||||
constant IMEM_ADDR_WIDTH : integer := 12;
|
||||
|
||||
-- Data memory
|
||||
constant DMEM_DATA_WIDTH : integer := 8;
|
||||
constant DMEM_ADDR_WIDTH : integer := 8;
|
||||
|
||||
-- Instruction format
|
||||
constant INST_OPCODE_WIDTH : integer := 6;
|
||||
constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
|
||||
|
||||
-- Microcode ROM
|
||||
constant MUCODE_ADDR_WIDTH : integer := 10;
|
||||
|
||||
-- Stack depth (uses lower half of CHIPRAM)
|
||||
constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
|
||||
|
||||
--Types
|
||||
subtype iphase_t is integer range 0 to 1;
|
||||
type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
|
||||
type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
|
||||
type alu_src_t is (reg_a, reg_b, const);
|
||||
type ddata_src_t is (reg_a, reg_b, const);
|
||||
type daddr_src_t is (reg_a, reg_b, const);
|
||||
subtype instr_name_t is string(1 to 12);
|
||||
type instr_name_array_t is array (0 to 63) of instr_name_t;
|
||||
subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
|
||||
subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
subtype reg_ptr_t is unsigned (3 downto 0);
|
||||
type dmem_array_t is array (natural range <>) of dmem_data_t;
|
||||
type instr_addr_array is array (integer range <>) of inst_addr_t;
|
||||
subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
|
||||
|
||||
type alu_op_t is
|
||||
(
|
||||
pass_op2,
|
||||
op1_add_op2,
|
||||
op1_sub_op2,
|
||||
op1_addc_op2,
|
||||
op1_subc_op2,
|
||||
op1_and_op2,
|
||||
op1_or_op2,
|
||||
op1_xor_op2,
|
||||
swap_op,
|
||||
shl_op,
|
||||
shr_op,
|
||||
rol_op,
|
||||
ror_op,
|
||||
rolc_op,
|
||||
rorc_op
|
||||
);
|
||||
|
||||
type alu_status_t is record
|
||||
zero : STD_LOGIC;
|
||||
carry : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cpu_status_t is record
|
||||
alu : alu_status_t;
|
||||
xmem_wait : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type ctrl_lines_t is record
|
||||
reg_we : STD_LOGIC;
|
||||
reg_src_sel : reg_src_t;
|
||||
alu_op1_src_sel : alu_src_t;
|
||||
alu_op2_src_sel : alu_src_t;
|
||||
alu_opsel : alu_op_t;
|
||||
alu_load : STD_LOGIC;
|
||||
alu_cy_in : STD_LOGIC;
|
||||
ddata_src_sel : ddata_src_t;
|
||||
daddr_src_sel : daddr_src_t;
|
||||
pc_load : STD_LOGIC;
|
||||
pc_inc : STD_LOGIC;
|
||||
stk_push : STD_LOGIC;
|
||||
stk_pop : STD_LOGIC;
|
||||
stk_pushd : STD_LOGIC;
|
||||
stk_popd : STD_LOGIC;
|
||||
mem_access : mem_access_t;
|
||||
mem_read : STD_LOGIC;
|
||||
mem_write : STD_LOGIC;
|
||||
int_exit : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type dpath_ctrl_out_t is record
|
||||
lines : ctrl_lines_t;
|
||||
reg_a_ptr : reg_ptr_t;
|
||||
reg_b_ptr : reg_ptr_t;
|
||||
end record;
|
||||
|
||||
type int_ctrl_in_t is record
|
||||
enable : std_logic;
|
||||
polarity : std_logic;
|
||||
edge_sens : std_logic;
|
||||
request : std_logic;
|
||||
end record;
|
||||
|
||||
type creg_ctrl_out_t is record
|
||||
page_sel : page_sel_t;
|
||||
int_ctrl : int_ctrl_in_t;
|
||||
stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
|
||||
end record;
|
||||
|
||||
type creg_ctrl_in_t is record
|
||||
alu : alu_status_t;
|
||||
end record;
|
||||
|
||||
|
||||
type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
|
||||
|
||||
constant instr_name_array : instr_name_array_t :=
|
||||
(
|
||||
"NOP ", -- 00
|
||||
"HALT ", -- 01
|
||||
"MOV|R|R ", -- 02
|
||||
"MOV|R|K ", -- 03
|
||||
"MOVX|R|Ri ", -- 04
|
||||
"MOVX|R|Ki ", -- 05
|
||||
"MOVX|Ri|R ", -- 06
|
||||
"MOVX|Ri|K ", -- 07
|
||||
"MOVX|Ki|R ", -- 08
|
||||
"MOVC|R|Ri ", -- 09
|
||||
"MOVC|R|Ki ", -- 0A
|
||||
"MOVC|Ri|R ", -- 0B
|
||||
"MOVC|Ri|K ", -- 0C
|
||||
"MOVC|Ki|R ", -- 0D
|
||||
"CMP|R|R ", -- 0E
|
||||
"CMP|R|K ", -- 0F
|
||||
"ADD|R|R ", -- 10
|
||||
"ADD|R|K ", -- 11
|
||||
"ADDC|R|R ", -- 12
|
||||
"ADDC|R|K ", -- 13
|
||||
"SUB|R|R ", -- 14
|
||||
"SUB|R|K ", -- 15
|
||||
"SUBC|R|R ", -- 16
|
||||
"SUBC|R|K ", -- 17
|
||||
"AND|R|R ", -- 18
|
||||
"AND|R|K ", -- 19
|
||||
"OR|R|R ", -- 1A
|
||||
"OR|R|K ", -- 1B
|
||||
"XOR|R|R ", -- 1C
|
||||
"XOR|R|K ", -- 1D
|
||||
"SHL|R ", -- 1E
|
||||
"SHR|R ", -- 1F
|
||||
"ROL|R ", -- 20
|
||||
"ROR|R ", -- 21
|
||||
"ROLC|R ", -- 22
|
||||
"RORC|R ", -- 23
|
||||
"XOUT|Ki|R ", -- 24
|
||||
"XOUT|Ri|K ", -- 25
|
||||
"COUT|Ki|R ", -- 26
|
||||
"COUT|Ri|K ", -- 27
|
||||
"XIN|R|Ki ", -- 28
|
||||
"CIN|R|Ki ", -- 29
|
||||
"SWAP|R ", -- 2A
|
||||
"SETC ", -- 2B
|
||||
"UNDEF ", -- 2C
|
||||
"UNDEF ", -- 2D
|
||||
"SUB|K|R ", -- 2E
|
||||
"SUBC|K|R ", -- 2F
|
||||
"JMP|K ", -- 30
|
||||
"JZ|K ", -- 31
|
||||
"JNZ|K ", -- 32
|
||||
"JC|K ", -- 33
|
||||
"JNC|K ", -- 34
|
||||
"JLT|K ", -- 35
|
||||
"JGT|K ", -- 36
|
||||
"JLE|K ", -- 37
|
||||
"JGE|K ", -- 38
|
||||
"JEQ|K ", -- 39
|
||||
"JNE|K ", -- 3A
|
||||
"CALL|K ", -- 3B
|
||||
"PUSH|R ", -- 3C
|
||||
"POP|R ", -- 3D
|
||||
"RET ", -- 3E
|
||||
"RETI " -- 3F
|
||||
);
|
||||
-- Functions
|
||||
function Instr(opcode : opcode_t) return inst_t;
|
||||
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
|
||||
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
|
||||
function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
|
||||
function ctrl_lines_default return ctrl_lines_t;
|
||||
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
|
||||
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
|
||||
function gen_murom return murom_t;
|
||||
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
|
||||
function MIN (X, Y: INTEGER) return INTEGER;
|
||||
function MAX (X, Y: INTEGER) return INTEGER;
|
||||
|
||||
end cpu_pkg;
|
||||
|
||||
package body cpu_pkg is
|
||||
|
||||
function Instr(opcode : opcode_t) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
|
||||
variable inst : inst_t := (others => '0');
|
||||
begin
|
||||
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
|
||||
inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
|
||||
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
|
||||
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
|
||||
|
||||
return inst;
|
||||
|
||||
end Instr;
|
||||
|
||||
function ctrl_lines_default return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
begin
|
||||
result.pc_load := '0';
|
||||
result.pc_inc := '0';
|
||||
result.stk_push := '0';
|
||||
result.stk_pop := '0';
|
||||
result.stk_pushd := '0';
|
||||
result.stk_popd := '0';
|
||||
result.reg_we := '0';
|
||||
result.reg_src_sel := alu_src;
|
||||
result.ddata_src_sel := reg_a;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '0';
|
||||
result.alu_cy_in := '0';
|
||||
result.mem_access := cmem_access;
|
||||
result.mem_read := '0';
|
||||
result.mem_write := '0';
|
||||
result.int_exit := '0';
|
||||
return result;
|
||||
|
||||
end ctrl_lines_default;
|
||||
|
||||
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
|
||||
variable instr_name : instr_name_t;
|
||||
begin
|
||||
instr_name := instr_name_array(to_integer(opcode));
|
||||
return idecoder(instr_name, iphase, status);
|
||||
end idecoder;
|
||||
|
||||
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
variable ze, cy, xmem_wait : STD_LOGIC;
|
||||
|
||||
begin
|
||||
ze := status.alu.zero;
|
||||
cy := status.alu.carry;
|
||||
xmem_wait := status.xmem_wait;
|
||||
|
||||
result := ctrl_lines_default;
|
||||
if iphase = 0 then
|
||||
result.pc_inc := '1';
|
||||
end if;
|
||||
|
||||
case instr_name is
|
||||
|
||||
when "HALT " =>
|
||||
result.pc_inc := '0';
|
||||
when "SETC " => -- carry <= 1
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
result.alu_cy_in := '1';
|
||||
when "MOV|R|R " => -- R(a) <= R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOV|R|K " => -- R(a) <= #kk
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := pass_op2;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|Ri|R " => -- [R(b)] <= R(a)
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVC|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "COUT|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := cio_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVC|R|Ri " => -- R(a) <= [R(b)]
|
||||
result.mem_access := cmem_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := reg_b;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := cmem_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CIN|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := cio_access;
|
||||
result.reg_src_sel := cmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "MOVC|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := cmem_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "COUT|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := cio_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVX|Ri|R " => -- [R(b)] <= R(a)
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := reg_b;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
if xmem_wait = '1' then
|
||||
result.mem_write := '1';
|
||||
result.pc_inc := '0';
|
||||
end if;
|
||||
when "MOVX|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
if xmem_wait = '1' then
|
||||
result.mem_write := '1';
|
||||
result.pc_inc := '0';
|
||||
end if;
|
||||
when "XOUT|Ri|K " => -- [R(a)] <= kk
|
||||
result.mem_access := xio_access;
|
||||
result.daddr_src_sel := reg_a;
|
||||
result.ddata_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
if xmem_wait = '1' then
|
||||
result.pc_inc := '0';
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "MOVX|R|Ri " => -- R(a) <= [R(b)]
|
||||
result.mem_access := xmem_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := reg_b;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
if xmem_wait = '0' then
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
else
|
||||
result.pc_inc := '0';
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
when "MOVX|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := xmem_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
if xmem_wait = '0' then
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
else
|
||||
result.pc_inc := '0';
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
when "XIN|R|Ki " => -- R(a) <= [#addr]
|
||||
result.mem_access := xio_access;
|
||||
result.reg_src_sel := xmem_src;
|
||||
result.daddr_src_sel := const;
|
||||
if iphase = 0 then
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
if xmem_wait = '0' then
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
else
|
||||
result.pc_inc := '0';
|
||||
result.mem_read := '1';
|
||||
end if;
|
||||
when "MOVX|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := xmem_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
if xmem_wait = '1' then
|
||||
result.pc_inc := '0';
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "XOUT|Ki|R " => -- [#addr] <= R(a)
|
||||
result.mem_access := xio_access;
|
||||
result.daddr_src_sel := const;
|
||||
result.ddata_src_sel := reg_a;
|
||||
if iphase = 0 then
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
if xmem_wait = '1' then
|
||||
result.pc_inc := '0';
|
||||
result.mem_write := '1';
|
||||
end if;
|
||||
when "ADD|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_add_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADD|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_add_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADDC|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_addc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ADDC|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_addc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUB|K|R " => -- R(a) <= k - R(a)
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := const;
|
||||
result.alu_op2_src_sel := reg_a;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|R|R " => -- R(a) <= R(a) + R(b)
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|R|K " => -- R(a) <= R(a) + k
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SUBC|K|R " => -- R(a) <= K - R(a)
|
||||
result.alu_opsel := op1_subc_op2;
|
||||
result.alu_op1_src_sel := const;
|
||||
result.alu_op2_src_sel := reg_a;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "AND|R|R " => -- R(a) <= R(a) and R(b)
|
||||
result.alu_opsel := op1_and_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "AND|R|K " => -- R(a) <= R(a) and k
|
||||
result.alu_opsel := op1_and_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "OR|R|R " => -- R(a) <= R(a) or R(b)
|
||||
result.alu_opsel := op1_or_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "OR|R|K " => -- R(a) <= R(a) or R(b)
|
||||
result.alu_opsel := op1_or_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "XOR|R|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.alu_opsel := op1_xor_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "XOR|R|K " => -- R(a) <= R(a) xor R(b)
|
||||
result.alu_opsel := op1_xor_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SWAP|R " => -- R(a) <= R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := swap_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SHL|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := shl_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "SHR|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := shr_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROL|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rol_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROR|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := ror_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "ROLC|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rolc_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "RORC|R " => -- R(a) <= R(a) xor R(b)
|
||||
result.reg_src_sel := alu_src;
|
||||
result.alu_opsel := rorc_op;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_load := '1';
|
||||
if iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CMP|R|R " => --
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := reg_b;
|
||||
result.alu_load := '1';
|
||||
when "CMP|R|K " => --
|
||||
result.alu_opsel := op1_sub_op2;
|
||||
result.alu_op1_src_sel := reg_a;
|
||||
result.alu_op2_src_sel := const;
|
||||
result.alu_load := '1';
|
||||
when "JMP|K " => -- PC <= #addr
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
when "JZ|K " => -- PC <= #addr, zero
|
||||
if iphase = 0 then
|
||||
if ze = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNZ|K " => -- PC <= #addr, !zero
|
||||
if iphase = 0 then
|
||||
if ze = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JC|K " => -- PC <= #addr, carry
|
||||
if iphase = 0 then
|
||||
if cy = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNC|K " => -- PC <= #addr, !carry
|
||||
if iphase = 0 then
|
||||
if cy = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JLT|K " => -- PC <= #addr, !carry
|
||||
if iphase = 0 then
|
||||
if cy = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JGT|K " => --
|
||||
if iphase = 0 then
|
||||
if (cy or ze) = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JLE|K " => --
|
||||
if iphase = 0 then
|
||||
if (cy xor ze) = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JGE|K " => --
|
||||
if iphase = 0 then
|
||||
if (not cy or ze) = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JEQ|K " => --
|
||||
if iphase = 0 then
|
||||
if ze = '1' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "JNE|K " => --
|
||||
if iphase = 0 then
|
||||
if ze = '0' then
|
||||
result.pc_load := '1';
|
||||
end if;
|
||||
end if;
|
||||
when "PUSH|R " => -- push
|
||||
if iphase = 0 then
|
||||
result.stk_pushd := '1';
|
||||
end if;
|
||||
when "POP|R " => -- pop
|
||||
result.reg_src_sel := stk_src;
|
||||
if iphase = 0 then
|
||||
result.stk_popd := '1';
|
||||
elsif iphase = 1 then
|
||||
result.reg_we := '1';
|
||||
end if;
|
||||
when "CALL|K " => -- call
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
result.stk_push := '1';
|
||||
end if;
|
||||
when "RET " => -- return
|
||||
if iphase = 0 then
|
||||
result.pc_load := '1';
|
||||
result.stk_pop := '1';
|
||||
end if;
|
||||
when "RETI " => -- return
|
||||
result.pc_inc := '0';
|
||||
result.int_exit := '1';
|
||||
|
||||
when others => null; -- nop
|
||||
end case;
|
||||
|
||||
return result;
|
||||
|
||||
end idecoder;
|
||||
|
||||
function gen_murom return murom_t is
|
||||
variable result : murom_t;
|
||||
variable opcode : opcode_t;
|
||||
variable iphase : iphase_t;
|
||||
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
|
||||
variable status : cpu_status_t;
|
||||
variable pos : integer := 0;
|
||||
|
||||
begin
|
||||
for i in 0 to 2**addr'length-1 loop
|
||||
addr := to_unsigned(i, addr'length);
|
||||
opcode := addr(opcode'length-1 downto 0);
|
||||
pos := opcode'length;
|
||||
iphase := 0;
|
||||
if addr(pos) = '1' then
|
||||
iphase := 1;
|
||||
end if;
|
||||
pos := pos + 1;
|
||||
status.alu.zero := addr(pos);
|
||||
pos := pos + 1;
|
||||
status.alu.carry := addr(pos);
|
||||
pos := pos + 1;
|
||||
status.xmem_wait := addr(pos);
|
||||
|
||||
result(i) := idecoder(opcode, iphase, status);
|
||||
end loop;
|
||||
|
||||
return result;
|
||||
end gen_murom;
|
||||
|
||||
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
|
||||
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
|
||||
begin
|
||||
addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
|
||||
return addr;
|
||||
|
||||
end get_muromaddr;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MIN (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y < X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MIN;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function MAX (X, Y: INTEGER) return INTEGER is
|
||||
variable res : integer := X;
|
||||
begin
|
||||
if Y > X then
|
||||
res := Y;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end MAX;
|
||||
|
||||
|
||||
end cpu_pkg;
|
||||
|
||||
@@ -1,87 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The datapath controller
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity dpath_ctrl is
|
||||
Generic (
|
||||
use_rom : boolean := true
|
||||
);
|
||||
Port (
|
||||
inst_in : in inst_t;
|
||||
iphase_in : in iphase_t;
|
||||
status_in : in cpu_status_t;
|
||||
ctrl_out : out dpath_ctrl_out_t;
|
||||
idout : out inst_addr_t;
|
||||
ddout : out dmem_data_t
|
||||
);
|
||||
end dpath_ctrl;
|
||||
|
||||
architecture Behavioral of dpath_ctrl is
|
||||
|
||||
signal opcode : opcode_t;
|
||||
signal ctrl_lines : ctrl_lines_t;
|
||||
signal dbg_iname : instr_name_t;
|
||||
|
||||
begin
|
||||
|
||||
idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
|
||||
ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
|
||||
opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
|
||||
|
||||
ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
|
||||
ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
|
||||
ctrl_out.lines <= ctrl_lines;
|
||||
|
||||
-- pragma translate_off
|
||||
dbg_iname <= instr_name_array(to_integer(opcode));
|
||||
-- pragma translate_on
|
||||
|
||||
gen_ctrl_rom:
|
||||
if use_rom = true generate
|
||||
|
||||
i_dec:
|
||||
process(opcode, iphase_in, status_in)
|
||||
constant rom_data : murom_t := gen_murom;
|
||||
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
|
||||
begin
|
||||
addr := get_muromaddr(opcode, iphase_in, status_in);
|
||||
ctrl_lines <= rom_data(to_integer(addr));
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
gen_ctrl:
|
||||
if use_rom = false generate
|
||||
i_dec:
|
||||
process (opcode, iphase_in, status_in)
|
||||
begin
|
||||
ctrl_lines <= idecoder(opcode, iphase_in, status_in);
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,177 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Interrupt controller
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity int_ctrl is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ctrl_in : in int_ctrl_in_t;
|
||||
int_in : in STD_LOGIC;
|
||||
int_exit : in STD_LOGIC;
|
||||
iphase_in : in iphase_t;
|
||||
pc_addr_out : out inst_addr_t;
|
||||
int_ack_out : out STD_LOGIC;
|
||||
stat_save_out : out STD_LOGIC;
|
||||
stat_rest_out : out STD_LOGIC;
|
||||
pc_load_out : out STD_LOGIC;
|
||||
stk_push_out : out STD_LOGIC;
|
||||
stk_pop_out : out STD_LOGIC
|
||||
);
|
||||
end int_ctrl;
|
||||
|
||||
architecture Behavioral of int_ctrl is
|
||||
|
||||
type int_state_t is (int_idle, int_inject, int_active, int_release);
|
||||
type pin_state_t is (pin_s0, pin_s1, pin_s2);
|
||||
|
||||
signal int_state, int_state_next : int_state_t;
|
||||
signal pin_state, pin_state_next : pin_state_t;
|
||||
signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
|
||||
signal int_request : std_logic;
|
||||
signal int_sampled : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
int_ack_out <= int_ack;
|
||||
pc_load_out <= pc_load;
|
||||
stk_push_out <= stk_push;
|
||||
stk_pop_out <= stk_pop;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
irg_ctrl_fsm:
|
||||
process (int_state, iphase_in, int_request, int_exit)
|
||||
begin
|
||||
|
||||
pc_addr_out <= to_unsigned(1, inst_addr_t'length);
|
||||
int_state_next <= int_state;
|
||||
int_ack <= '0';
|
||||
pc_load <= '0';
|
||||
stk_push <= '0';
|
||||
stk_pop <= '0';
|
||||
|
||||
case int_state is
|
||||
|
||||
when int_idle =>
|
||||
if int_request = '1' and iphase_in = 1 then
|
||||
int_state_next <= int_inject;
|
||||
end if;
|
||||
when int_inject =>
|
||||
if iphase_in = 0 then
|
||||
int_ack <= '1';
|
||||
pc_load <= '1';
|
||||
elsif iphase_in = 1 then
|
||||
stk_push <= '1';
|
||||
int_state_next <= int_active;
|
||||
end if;
|
||||
when int_active =>
|
||||
if int_exit = '1' and iphase_in = 1 then
|
||||
int_state_next <= int_release;
|
||||
end if;
|
||||
when int_release =>
|
||||
if iphase_in = 0 then
|
||||
stk_pop <= '1';
|
||||
pc_load <= '1';
|
||||
elsif iphase_in = 1 then
|
||||
int_state_next <= int_idle;
|
||||
end if;
|
||||
when others =>
|
||||
int_state_next <= int_idle;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
irq_ctrl_states:
|
||||
process (rst, clk, int_state_next)
|
||||
begin
|
||||
if rst = '1' then
|
||||
int_state <= int_idle;
|
||||
elsif rising_edge(clk) then
|
||||
int_state <= int_state_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
pin_sample:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
int_sampled <= int_in xor (not ctrl_in.polarity);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
pin_fsm:
|
||||
process (pin_state, int_sampled, int_ack, ctrl_in)
|
||||
begin
|
||||
int_request <= '0';
|
||||
pin_state_next <= pin_state;
|
||||
case pin_state is
|
||||
when pin_s0 =>
|
||||
if int_sampled = '1' or ctrl_in.request = '1' then
|
||||
if ctrl_in.enable = '1' then
|
||||
pin_state_next <= pin_s1;
|
||||
end if;
|
||||
end if;
|
||||
when pin_s1 =>
|
||||
int_request <= '1';
|
||||
if int_ack = '1' then
|
||||
pin_state_next <= pin_s2;
|
||||
end if;
|
||||
when pin_s2 =>
|
||||
if ctrl_in.edge_sens = '0' then
|
||||
pin_state_next <= pin_s0;
|
||||
elsif int_sampled = '0' then
|
||||
pin_state_next <= pin_s0;
|
||||
end if;
|
||||
when others =>
|
||||
pin_state_next <= pin_s0;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
pin_states:
|
||||
process (rst, clk, pin_state_next)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pin_state <= pin_s0;
|
||||
elsif rising_edge(clk) then
|
||||
pin_state <= pin_state_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
stat_save_restore:
|
||||
process (clk, stk_push, stk_pop)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
stat_save_out <= stk_push;
|
||||
stat_rest_out <= stk_pop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,70 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Programm counter
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity pc is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
inc : in STD_LOGIC;
|
||||
load : in STD_LOGIC;
|
||||
pc_in : in inst_addr_t;
|
||||
pc_out : out inst_addr_t;
|
||||
pc_next : out inst_addr_t
|
||||
);
|
||||
end pc;
|
||||
|
||||
architecture Behavioral of pc is
|
||||
|
||||
begin
|
||||
|
||||
proc_pc:
|
||||
process(rst, clk, inc, load, pc_in)
|
||||
variable vpc, vpc_reg: inst_addr_t;
|
||||
begin
|
||||
if rst = '1' then
|
||||
vpc_reg := (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if inc = '1' or load = '1' then
|
||||
vpc_reg := vpc;
|
||||
elsif inc = '0' then
|
||||
pc_next <= vpc;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if load = '1' then
|
||||
vpc := pc_in;
|
||||
else
|
||||
vpc := vpc_reg + 1;
|
||||
end if;
|
||||
pc_out <= vpc_reg;
|
||||
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,81 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: On-Chip work registers
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity reg_dual is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
ptr_a : in reg_ptr_t;
|
||||
ptr_b : in reg_ptr_t;
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end reg_dual;
|
||||
|
||||
architecture Behavioral of reg_dual is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
|
||||
|
||||
signal mem : mem_t;
|
||||
begin
|
||||
|
||||
addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
|
||||
addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
|
||||
|
||||
reg_in_ab:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we_a = '1' then
|
||||
mem(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reg_out_a:
|
||||
process(mem, addr_a)
|
||||
begin
|
||||
dout_a <= TO_01(mem(to_integer(addr_a)));
|
||||
end process;
|
||||
|
||||
reg_out_b:
|
||||
process(mem, addr_b)
|
||||
begin
|
||||
dout_b <= TO_01(mem(to_integer(addr_b)));
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,73 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity stack_ctrl is
|
||||
Generic (
|
||||
addr_width : integer := 3
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
push : in STD_LOGIC;
|
||||
pop : in STD_LOGIC;
|
||||
ptr_out : out unsigned (addr_width-1 downto 0);
|
||||
din : in inst_addr_t;
|
||||
dout : out inst_addr_t;
|
||||
mem_we : out STD_LOGIC
|
||||
);
|
||||
end stack_ctrl;
|
||||
|
||||
architecture Behavioral of stack_ctrl is
|
||||
|
||||
signal ptr : unsigned (addr_width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
ptr_out <= ptr;
|
||||
|
||||
stk_ptr:
|
||||
process(rst, clk, ptr, push, pop)
|
||||
begin
|
||||
if rst = '1' then
|
||||
ptr <= (others => '0');
|
||||
dout <= (others => '0');
|
||||
mem_we <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
mem_we <= push;
|
||||
if push = '1' then
|
||||
ptr <= ptr + 1;
|
||||
dout <= din;
|
||||
elsif pop = '1' then
|
||||
ptr <= ptr - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,109 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity cpu_embedded is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_wait : in STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
end cpu_embedded;
|
||||
|
||||
architecture rtl of cpu_embedded is
|
||||
|
||||
signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
COMPONENT cpu
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_wait : in STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
COMPONENT irom
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
inst_cpu: cpu
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_in,
|
||||
int_ack => int_ack,
|
||||
xmem_wait => xmem_wait,
|
||||
xmem_we => xmem_we,
|
||||
xmem_re => xmem_re,
|
||||
instr_din => irom_data,
|
||||
instr_addr => irom_addr,
|
||||
xmem_din => xmem_din,
|
||||
xmem_dout => xmem_dout,
|
||||
xmem_addr => xmem_addr,
|
||||
io_sel => io_sel
|
||||
);
|
||||
|
||||
inst_irom: irom
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
addr => irom_addr,
|
||||
dout => irom_data
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -1,79 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE dctest OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 17) of inst_t;
|
||||
|
||||
-- Assembled from dctest.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"010", -- 0x000: JMP 0x010
|
||||
"110000" & X"011", -- 0x001: JMP 0x011
|
||||
"000000" & X"000", -- 0x002:
|
||||
"000000" & X"000", -- 0x003:
|
||||
"000000" & X"000", -- 0x004:
|
||||
"000000" & X"000", -- 0x005:
|
||||
"000000" & X"000", -- 0x006:
|
||||
"000000" & X"000", -- 0x007:
|
||||
"000000" & X"000", -- 0x008:
|
||||
"000000" & X"000", -- 0x009:
|
||||
"000000" & X"000", -- 0x00A:
|
||||
"000000" & X"000", -- 0x00B:
|
||||
"000000" & X"000", -- 0x00C:
|
||||
"000000" & X"000", -- 0x00D:
|
||||
"000000" & X"000", -- 0x00E:
|
||||
"000000" & X"000", -- 0x00F:
|
||||
"110000" & X"010", -- 0x010: JMP 0x010
|
||||
"111111" & X"000" -- 0x011: RETI
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end dctest;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,317 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE dctest OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from dctest.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"01", -- 0x04
|
||||
X"12", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"48", -- 0x17
|
||||
X"61", -- 0x18
|
||||
X"6C", -- 0x19
|
||||
X"6C", -- 0x1A
|
||||
X"6F", -- 0x1B
|
||||
X"0D", -- 0x1C
|
||||
X"0A", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"4A", -- 0x1F
|
||||
X"65", -- 0x20
|
||||
X"6E", -- 0x21
|
||||
X"73", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"57", -- 0x24
|
||||
X"65", -- 0x25
|
||||
X"6C", -- 0x26
|
||||
X"63", -- 0x27
|
||||
X"6F", -- 0x28
|
||||
X"6D", -- 0x29
|
||||
X"65", -- 0x2A
|
||||
X"20", -- 0x2B
|
||||
X"74", -- 0x2C
|
||||
X"6F", -- 0x2D
|
||||
X"20", -- 0x2E
|
||||
X"4A", -- 0x2F
|
||||
X"41", -- 0x30
|
||||
X"53", -- 0x31
|
||||
X"4D", -- 0x32
|
||||
X"20", -- 0x33
|
||||
X"43", -- 0x34
|
||||
X"50", -- 0x35
|
||||
X"55", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"52", -- 0x38
|
||||
X"65", -- 0x39
|
||||
X"61", -- 0x3A
|
||||
X"64", -- 0x3B
|
||||
X"79", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"54", -- 0x3E
|
||||
X"65", -- 0x3F
|
||||
X"73", -- 0x40
|
||||
X"74", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"6E", -- 0x43
|
||||
X"67", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"50", -- 0x46
|
||||
X"61", -- 0x47
|
||||
X"73", -- 0x48
|
||||
X"73", -- 0x49
|
||||
X"65", -- 0x4A
|
||||
X"64", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"45", -- 0x4D
|
||||
X"72", -- 0x4E
|
||||
X"72", -- 0x4F
|
||||
X"6F", -- 0x50
|
||||
X"72", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"0D", -- 0x53
|
||||
X"0A", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end dctest;
|
||||
|
||||
@@ -1,413 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from dctest.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"01", -- 0x04
|
||||
X"12", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"48", -- 0x17
|
||||
X"61", -- 0x18
|
||||
X"6C", -- 0x19
|
||||
X"6C", -- 0x1A
|
||||
X"6F", -- 0x1B
|
||||
X"0D", -- 0x1C
|
||||
X"0A", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"4A", -- 0x1F
|
||||
X"65", -- 0x20
|
||||
X"6E", -- 0x21
|
||||
X"73", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"57", -- 0x24
|
||||
X"65", -- 0x25
|
||||
X"6C", -- 0x26
|
||||
X"63", -- 0x27
|
||||
X"6F", -- 0x28
|
||||
X"6D", -- 0x29
|
||||
X"65", -- 0x2A
|
||||
X"20", -- 0x2B
|
||||
X"74", -- 0x2C
|
||||
X"6F", -- 0x2D
|
||||
X"20", -- 0x2E
|
||||
X"4A", -- 0x2F
|
||||
X"41", -- 0x30
|
||||
X"53", -- 0x31
|
||||
X"4D", -- 0x32
|
||||
X"20", -- 0x33
|
||||
X"43", -- 0x34
|
||||
X"50", -- 0x35
|
||||
X"55", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"52", -- 0x38
|
||||
X"65", -- 0x39
|
||||
X"61", -- 0x3A
|
||||
X"64", -- 0x3B
|
||||
X"79", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"54", -- 0x3E
|
||||
X"65", -- 0x3F
|
||||
X"73", -- 0x40
|
||||
X"74", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"6E", -- 0x43
|
||||
X"67", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"50", -- 0x46
|
||||
X"61", -- 0x47
|
||||
X"73", -- 0x48
|
||||
X"73", -- 0x49
|
||||
X"65", -- 0x4A
|
||||
X"64", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"45", -- 0x4D
|
||||
X"72", -- 0x4E
|
||||
X"72", -- 0x4F
|
||||
X"6F", -- 0x50
|
||||
X"72", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"0D", -- 0x53
|
||||
X"0A", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,317 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE itest OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"48", -- 0x00
|
||||
X"61", -- 0x01
|
||||
X"6C", -- 0x02
|
||||
X"6C", -- 0x03
|
||||
X"6F", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end itest;
|
||||
|
||||
@@ -1,413 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"48", -- 0x00
|
||||
X"61", -- 0x01
|
||||
X"6C", -- 0x02
|
||||
X"6C", -- 0x03
|
||||
X"6F", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE mul8x8 OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 26) of inst_t;
|
||||
|
||||
-- Assembled from mul8x8.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"001", -- 0x000: JMP 0x001
|
||||
"000011" & X"450", -- 0x001: MOV R00, 0x45
|
||||
"000011" & X"F51", -- 0x002: MOV R01, 0xF5
|
||||
"111011" & X"005", -- 0x003: CALL 0x005
|
||||
"110000" & X"004", -- 0x004: JMP 0x004
|
||||
"111100" & X"002", -- 0x005: PUSH R02
|
||||
"111100" & X"003", -- 0x006: PUSH R03
|
||||
"111100" & X"004", -- 0x007: PUSH R04
|
||||
"000010" & X"014", -- 0x008: MOV R04, R01
|
||||
"000011" & X"001", -- 0x009: MOV R01, 0x00
|
||||
"000011" & X"002", -- 0x00A: MOV R02, 0x00
|
||||
"000011" & X"003", -- 0x00B: MOV R03, 0x00
|
||||
"001111" & X"014", -- 0x00C: CMP R04, 0x01
|
||||
"111001" & X"015", -- 0x00D: JEQ 0x015
|
||||
"011111" & X"004", -- 0x00E: SHR R04
|
||||
"110100" & X"012", -- 0x00F: JNC 0x012
|
||||
"010000" & X"002", -- 0x010: ADD R02, R00
|
||||
"010010" & X"013", -- 0x011: ADDC R03, R01
|
||||
"011110" & X"000", -- 0x012: SHL R00
|
||||
"100010" & X"001", -- 0x013: ROLC R01
|
||||
"110000" & X"00C", -- 0x014: JMP 0x00C
|
||||
"010000" & X"020", -- 0x015: ADD R00, R02
|
||||
"010010" & X"031", -- 0x016: ADDC R01, R03
|
||||
"111101" & X"004", -- 0x017: POP R04
|
||||
"111101" & X"003", -- 0x018: POP R03
|
||||
"111101" & X"002", -- 0x019: POP R02
|
||||
"111110" & X"000" -- 0x01A: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mul8x8;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,317 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE mul8x8 OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from mul8x8.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mul8x8;
|
||||
|
||||
@@ -1,413 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from mul8x8.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,89 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE reti_issue OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 27) of inst_t;
|
||||
|
||||
-- Assembled from reti_issue.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"000011" & X"050", -- 0x002: MOV R00, 0x05
|
||||
"100110" & X"030", -- 0x003: COUT (0x03), R00
|
||||
"000011" & X"000", -- 0x004: MOV R00, 0x00
|
||||
"000000" & X"000", -- 0x005: NOP
|
||||
"010001" & X"010", -- 0x006: INC R00
|
||||
"000000" & X"000", -- 0x007: NOP
|
||||
"111011" & X"01B", -- 0x008: CALL 0x01B
|
||||
"000000" & X"000", -- 0x009: NOP
|
||||
"111100" & X"003", -- 0x00A: PUSH R03
|
||||
"000000" & X"000", -- 0x00B: NOP
|
||||
"111100" & X"002", -- 0x00C: PUSH R02
|
||||
"000000" & X"000", -- 0x00D: NOP
|
||||
"111100" & X"001", -- 0x00E: PUSH R01
|
||||
"000000" & X"000", -- 0x00F: NOP
|
||||
"111100" & X"000", -- 0x010: PUSH R00
|
||||
"000000" & X"000", -- 0x011: NOP
|
||||
"111101" & X"000", -- 0x012: POP R00
|
||||
"000000" & X"000", -- 0x013: NOP
|
||||
"111101" & X"001", -- 0x014: POP R01
|
||||
"000000" & X"000", -- 0x015: NOP
|
||||
"111101" & X"002", -- 0x016: POP R02
|
||||
"000000" & X"000", -- 0x017: NOP
|
||||
"111101" & X"003", -- 0x018: POP R03
|
||||
"000000" & X"000", -- 0x019: NOP
|
||||
"110000" & X"005", -- 0x01A: JMP 0x005
|
||||
"111110" & X"000" -- 0x01B: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end reti_issue;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,317 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE reti_issue OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from reti_issue.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end reti_issue;
|
||||
|
||||
@@ -1,413 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from reti_issue.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,129 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for embedded cpu with rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY tb_cpu_embedded IS
|
||||
END tb_cpu_embedded;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cpu_embedded IS
|
||||
|
||||
COMPONENT cpu_embedded
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_wait : in STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
type sram_t is array (integer range <>) of dmem_data_t;
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal ce : std_logic := '0';
|
||||
signal int_in : std_logic := '0';
|
||||
signal int_ack : std_logic;
|
||||
signal xmem_wait : std_logic := '0';
|
||||
signal xmem_din : dmem_data_t := (others => '-');
|
||||
signal xmem_dout : dmem_data_t;
|
||||
signal xmem_addr : dmem_addr_t;
|
||||
signal xmem_we : std_logic;
|
||||
signal xmem_re : std_logic;
|
||||
signal io_sel : std_logic;
|
||||
signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: cpu_embedded
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_in,
|
||||
int_ack => int_ack,
|
||||
xmem_wait => xmem_wait,
|
||||
xmem_we => xmem_we,
|
||||
xmem_re => xmem_re,
|
||||
xmem_din => xmem_din,
|
||||
xmem_dout => xmem_dout,
|
||||
xmem_addr => xmem_addr,
|
||||
io_sel => io_sel
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk);
|
||||
ce <= '1';
|
||||
|
||||
wait for 1000*CLK_PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
xmem_din <= X"00";
|
||||
elsif rising_edge(clk) then
|
||||
if io_sel = '0' then
|
||||
if xmem_we = '1' then
|
||||
sram(to_integer(xmem_addr)) <= xmem_dout;
|
||||
end if;
|
||||
xmem_din <= to_01(sram(to_integer(xmem_addr)));
|
||||
else
|
||||
xmem_din <= X"FF";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,218 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Formal test of correct function of JCPU,
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_cpu IS
|
||||
END tb_cpu;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cpu IS
|
||||
|
||||
COMPONENT cpu
|
||||
Generic (
|
||||
use_instr_register : boolean;
|
||||
use_ctrl_rom : boolean
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_wait : in STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT irom
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
type prom_t is array (integer range <>) of inst_t;
|
||||
type sram_t is array (integer range <>) of dmem_data_t;
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal ce : std_logic := '0';
|
||||
signal int_in : std_logic := '0';
|
||||
signal int_ack : std_logic;
|
||||
signal xmem_wait : std_logic := '1';
|
||||
signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
|
||||
signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
signal xmem_din : dmem_data_t := (others => '-');
|
||||
signal xmem_dout : dmem_data_t;
|
||||
signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
signal xmem_we : std_logic;
|
||||
signal xmem_re : std_logic;
|
||||
signal io_sel : std_logic;
|
||||
signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
|
||||
|
||||
type reg_t is record
|
||||
revision : dmem_data_t;
|
||||
testid : dmem_data_t;
|
||||
interrupt : std_logic;
|
||||
end record;
|
||||
|
||||
signal reg : reg_t;
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
int_in <= reg.interrupt;
|
||||
uut: cpu
|
||||
GENERIC MAP
|
||||
(
|
||||
use_instr_register => false,
|
||||
use_ctrl_rom => true
|
||||
)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_in,
|
||||
int_ack => int_ack,
|
||||
xmem_wait => xmem_wait,
|
||||
xmem_we => xmem_we,
|
||||
xmem_re => xmem_re,
|
||||
instr_din => irom_data,
|
||||
instr_addr => irom_addr,
|
||||
xmem_din => xmem_din,
|
||||
xmem_dout => xmem_dout,
|
||||
xmem_addr => xmem_addr,
|
||||
io_sel => io_sel
|
||||
);
|
||||
|
||||
the_irom: irom
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
addr => irom_addr,
|
||||
dout => irom_data
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
XWAIT_GEN:process(rst, clk)
|
||||
variable cnt : unsigned(3 downto 0);
|
||||
begin
|
||||
if (rst = '1') then
|
||||
cnt := (others => '1');
|
||||
elsif rising_edge(clk) then
|
||||
if cnt /= "0000" then
|
||||
cnt := cnt - 1;
|
||||
else
|
||||
cnt := (others => '1');
|
||||
xmem_wait <= not xmem_wait;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
file RESULT: text open write_mode is "../tools/opc.list";
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
for i in 0 to instr_name_array'length-1 loop
|
||||
fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
|
||||
end loop;
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk);
|
||||
ce <= '1';
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
SRAM_RW: process(rst, clk)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
reg.revision <= (others => '0');
|
||||
reg.testid <= (others => '0');
|
||||
reg.interrupt <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if int_ack = '1' then
|
||||
-- reg.interrupt <= '0';
|
||||
end if;
|
||||
if xmem_we = '1' then
|
||||
if io_sel = '0' then
|
||||
sram(to_integer(xmem_addr)) <= xmem_dout;
|
||||
else
|
||||
case xmem_addr is
|
||||
when X"00" =>
|
||||
reg.revision <= xmem_dout;
|
||||
when X"01" =>
|
||||
reg.testid <= xmem_dout;
|
||||
when X"02" =>
|
||||
reg.interrupt <= xmem_dout(0);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
else
|
||||
if io_sel = '0' then
|
||||
xmem_din <= to_01(sram(to_integer(xmem_addr)));
|
||||
else
|
||||
case xmem_addr is
|
||||
when X"00" =>
|
||||
xmem_din <= reg.revision;
|
||||
when X"01" =>
|
||||
xmem_din <= reg.testid;
|
||||
when others =>
|
||||
xmem_din <= X"BC";
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,10 +0,0 @@
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd"
|
||||
@@ -1,42 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
str1 = %Q!lbl: dc "Hallo", ", ", 0, 1, " der","Jens"!
|
||||
|
||||
i=0;
|
||||
|
||||
def get_stri_lit (str)
|
||||
res = [""];
|
||||
state = "out"
|
||||
|
||||
j = 0;
|
||||
k = 0;
|
||||
for i in (0..str.length-1)
|
||||
c = str[i];
|
||||
nstate = state
|
||||
case state
|
||||
when "out"
|
||||
if c == "\""[0]
|
||||
nstate = "in"
|
||||
end
|
||||
when "in"
|
||||
if c == "\""[0]
|
||||
nstate = "out"
|
||||
if j > 0
|
||||
k = k + 1;
|
||||
res[k] = ""
|
||||
end
|
||||
else
|
||||
res[k] = res[k] + format("%c", c);
|
||||
j = j + 1;
|
||||
end
|
||||
end
|
||||
state = nstate
|
||||
end;
|
||||
return res
|
||||
end
|
||||
|
||||
get_stri_lit(str1).each do |word|
|
||||
puts word
|
||||
end
|
||||
|
||||
|
||||
@@ -1,46 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: Insertion of code fragments into templates
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
arg = $*
|
||||
rom_filename = arg[0].to_s
|
||||
tpl_filename = arg[1].to_s
|
||||
|
||||
subst_pattern = "JASM_ROM_INSERT_HERE"
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Open file
|
||||
# --------------------------------------------------------
|
||||
romfile = File.open(rom_filename, "r")
|
||||
tplfile = File.open(tpl_filename, "r")
|
||||
re = Regexp.new(subst_pattern)
|
||||
|
||||
while (line = tplfile.gets)
|
||||
puts line
|
||||
line.scan(re).each do |word|
|
||||
romfile.each do |raw_line|
|
||||
puts raw_line
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1,32 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
@@ -1,151 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE loadable OF irom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : inst_addr_t;
|
||||
signal jtag_ld_dout : inst_t;
|
||||
signal jtag_ld_din : inst_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (31 downto 0);
|
||||
constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
|
||||
jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,494 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: A small assembler for the JCPU
|
||||
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
arg = $*
|
||||
MAX_SIZE_ROM = 1024
|
||||
PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
|
||||
ENTITY_NAME = "rom"
|
||||
ENTITY_DATA_TYPE = "inst_t"
|
||||
ENTITY_ADDR_TYPE = "inst_addr_t"
|
||||
OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Open file
|
||||
# --------------------------------------------------------
|
||||
filename = arg.to_s
|
||||
if !File.exists?(filename)
|
||||
STDERR.puts "#{filename} does not exist"
|
||||
exit 1
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Pass 1
|
||||
# --------------------------------------------------------
|
||||
lc = 0 # Line counter
|
||||
pc = 0 # Program counter
|
||||
chip_dc = [0,0,0,0] # chip data counter
|
||||
xmem_dc = 0 # xmem data counter
|
||||
curr_segment = "UNDEF";
|
||||
page = 0
|
||||
|
||||
label_list=[[],[]]
|
||||
instr_list=[nil]
|
||||
file = File.open(filename, "r")
|
||||
file.each do |raw_line|
|
||||
lc += 1
|
||||
|
||||
# Make all upper case
|
||||
iline = "#{raw_line}".strip.upcase
|
||||
|
||||
# Remove comments
|
||||
iline = iline.gsub(/;.*/, "")
|
||||
|
||||
# Split instruction at spaces
|
||||
iline_member = iline.split(" ")
|
||||
|
||||
if iline_member[0] == nil
|
||||
next
|
||||
end
|
||||
|
||||
mc = 0;
|
||||
label = nil
|
||||
clean_line = nil
|
||||
if (iline_member[0] =~ /\w+:/)
|
||||
mc += 1
|
||||
label = iline_member[0].delete(":")
|
||||
if label_list.rindex(label) != nil
|
||||
STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
|
||||
exit 1
|
||||
end
|
||||
end
|
||||
|
||||
case iline_member[mc]
|
||||
when nil
|
||||
value = format("0x%3.3X",pc)
|
||||
when "EQU"
|
||||
if 0 == (iline_member[mc+1] =~ /\d+/)
|
||||
value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
|
||||
else
|
||||
value = iline_member[mc+1]
|
||||
end
|
||||
when "ORG", "CODE"
|
||||
pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
|
||||
value = format("0x%3.3X",pc)
|
||||
when "CDATA", "CMEM"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
|
||||
exit 1
|
||||
end
|
||||
curr_segment = "CMEM";
|
||||
page = iline_member[mc+1].to_i(16)
|
||||
when "XDATA", "XMEM"
|
||||
curr_segment = "XMEM";
|
||||
when "DC"
|
||||
len = 0;
|
||||
iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte|
|
||||
len += 1
|
||||
end
|
||||
if curr_segment == "CMEM"
|
||||
STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
|
||||
exit 1
|
||||
else
|
||||
value = format("0x%2.2X",xmem_dc)
|
||||
puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
|
||||
xmem_dc += len
|
||||
end
|
||||
when "DB"
|
||||
len = iline_member[mc+1].to_i
|
||||
if curr_segment == "CMEM"
|
||||
value = format("0x%2.2X",chip_dc[page])
|
||||
puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
|
||||
chip_dc[page] += len
|
||||
else
|
||||
value = format("0x%2.2X",xmem_dc)
|
||||
puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
|
||||
xmem_dc += len
|
||||
end
|
||||
else
|
||||
op_line = iline_member[mc+1..iline_member.nitems].to_s
|
||||
value = format("0x%3.3X",pc)
|
||||
opc = iline_member[mc]
|
||||
if iline_member[mc+1] != nil
|
||||
op1 = op_line.gsub(/,+.*$/, "")
|
||||
end
|
||||
if iline_member[mc+2] != nil
|
||||
op2 = op_line.scan(/,.+$/).to_s.delete(", ")
|
||||
end
|
||||
if instr_list[pc] == nil
|
||||
instr_list[pc] = [lc, pc, opc , op1 , op2]
|
||||
pc += 1
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
|
||||
exit 1
|
||||
end
|
||||
end;
|
||||
|
||||
# Push labels
|
||||
if label
|
||||
label_list = label_list + [label, value]
|
||||
end
|
||||
end
|
||||
file.close
|
||||
|
||||
# --------------------------------------------------------
|
||||
def instr(opcode)
|
||||
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
|
||||
end
|
||||
|
||||
def tcl_bits(pc, opcode)
|
||||
return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
|
||||
end
|
||||
|
||||
def instr_k(opcode, k)
|
||||
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
|
||||
end
|
||||
|
||||
def tcl_bits_k(pc, opcode, k)
|
||||
return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
|
||||
end
|
||||
|
||||
def instr_r(opcode, r)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
|
||||
end
|
||||
|
||||
def tcl_bits_r(pc, opcode, r)
|
||||
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
|
||||
end
|
||||
|
||||
def instr_kr(opcode, k, r)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
|
||||
end
|
||||
|
||||
def tcl_bits_kr(pc, opcode, k, r)
|
||||
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
|
||||
end
|
||||
|
||||
def instr_rk(opcode, r, k)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
|
||||
end
|
||||
|
||||
def tcl_bits_rk(pc, opcode, r, k)
|
||||
return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
|
||||
end
|
||||
|
||||
def instr_rr(opcode, ra, rb)
|
||||
return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
|
||||
end
|
||||
|
||||
def tcl_bits_rr(pc, opcode, ra, rb)
|
||||
return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Read mnemonic set
|
||||
# --------------------------------------------------------
|
||||
filename = OPC_LIST_NAME
|
||||
if !File.exists?(filename)
|
||||
STDERR.puts "#{filename} does not exist"
|
||||
exit 1
|
||||
end
|
||||
|
||||
mnemo_list = []
|
||||
num_opcodes = 0
|
||||
file = File.open(filename, "r")
|
||||
file.each do |raw_line|
|
||||
mnemo_list[num_opcodes] = raw_line.split(" ")[1]
|
||||
num_opcodes += 1
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Pass 2
|
||||
# --------------------------------------------------------
|
||||
pc = 0
|
||||
opc_start = 2
|
||||
num_errors = 0
|
||||
vhdl_trans_list = [nil]
|
||||
vhdl_comment_list = [nil]
|
||||
vhdl_tcl_list = [nil]
|
||||
instr_list.each do |instruct|
|
||||
|
||||
# puts instruct
|
||||
if instruct == nil
|
||||
vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
|
||||
vhdl_comment_list[pc] = format("0x%3.3X:", pc)
|
||||
vhdl_tcl_list[pc] = tcl_bits(pc, 0)
|
||||
pc += 1
|
||||
next
|
||||
end
|
||||
|
||||
# determine arglen of instruction
|
||||
ilen = 0
|
||||
if instruct[opc_start+1] == nil
|
||||
arglen = 0
|
||||
elsif instruct[opc_start+2] == nil
|
||||
arglen = 1
|
||||
elsif instruct[opc_start+3] == nil
|
||||
arglen = 2
|
||||
end
|
||||
|
||||
# Symbol substitution
|
||||
error = false
|
||||
for i in (1..3)
|
||||
subst_pos = opc_start+i
|
||||
if instruct[subst_pos] == nil
|
||||
next
|
||||
end
|
||||
expr_token = ""
|
||||
expr_subst = nil
|
||||
is_direct = true;
|
||||
|
||||
# instruct[subst_pos] = instruct[subst_pos].delete(" ")
|
||||
|
||||
# checks R0 .. R16, Mnemonics
|
||||
instr_str = instruct[subst_pos]
|
||||
if 0 == (instr_str =~ /\(.+\)/)
|
||||
instr_str = instr_str.delete("()")
|
||||
is_direct = false;
|
||||
end
|
||||
|
||||
expr_token = instr_str.split(/\+|\-|\*|\//)[0]
|
||||
if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
|
||||
idx = label_list.rindex(expr_token)
|
||||
if idx != nil
|
||||
expr_subst = label_list[idx+1]
|
||||
instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
|
||||
error = true
|
||||
end
|
||||
end
|
||||
|
||||
if expr_subst != nil
|
||||
if 0 == (expr_subst =~ /\d+/)
|
||||
if is_direct == true
|
||||
instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
|
||||
else
|
||||
instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
|
||||
end
|
||||
else
|
||||
if 0 != (expr_subst =~ /R[0-9]+/)
|
||||
STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
|
||||
error = true
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
# Parse operands
|
||||
reg = [0,0]
|
||||
kk = 0
|
||||
format = instruct[opc_start]
|
||||
for i in (0..1)
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
|
||||
# Check indirect addressing
|
||||
reg[i] = instruct[opc_start+i+1].delete("R()").to_i
|
||||
format += "|R"
|
||||
if reg[i] > 15
|
||||
STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
|
||||
error = true
|
||||
end
|
||||
else
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
|
||||
kk = instruct[opc_start+i+1].delete("()").to_i(16)
|
||||
format += "|K"
|
||||
end
|
||||
end
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
|
||||
format += "i";
|
||||
end
|
||||
end
|
||||
|
||||
# Output instruction
|
||||
opcode = mnemo_list.rindex(format).to_i
|
||||
mnemo = instruct[2];
|
||||
|
||||
case format
|
||||
when "NOP", "HALT", "RET", "RETI"
|
||||
vhdl_trans_list[pc] = instr(opcode)
|
||||
vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
|
||||
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
|
||||
when "MOVC|R|Ri", "MOVX|R|Ri"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
|
||||
when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
|
||||
when "MOVC|Ri|R", "MOVX|Ri|R"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
|
||||
minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
|
||||
when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
|
||||
when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
|
||||
when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
|
||||
when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
|
||||
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
|
||||
when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
|
||||
vhdl_trans_list[pc] = instr_k(opcode, kk)
|
||||
vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
|
||||
minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
|
||||
when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
|
||||
vhdl_trans_list[pc] = instr_r(opcode, reg[0])
|
||||
vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
when "TST|R"
|
||||
kk = 0
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("CMP|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "INC|R"
|
||||
kk = 1
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("ADD|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "DEC|R"
|
||||
kk = 1
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("SUB|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
|
||||
error = true
|
||||
end
|
||||
|
||||
if error
|
||||
num_errors += 1
|
||||
break
|
||||
end
|
||||
vhdl_comment_list[pc] = minstr_comment
|
||||
|
||||
puts vhdl_trans_list[pc] + " -- " + minstr_comment
|
||||
|
||||
pc += 1
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Output ROM file
|
||||
# --------------------------------------------------------
|
||||
if num_errors == 0
|
||||
|
||||
filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("ENTITY %s IS\n", ENTITY_NAME)
|
||||
file.puts format("\tPort (\n")
|
||||
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE)
|
||||
file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("END %s;\n", ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
|
||||
file.puts format("\n")
|
||||
file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..pc-2)
|
||||
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
||||
end;
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("begin")
|
||||
file.puts format("\n")
|
||||
file.puts format("PROM_READ:")
|
||||
file.puts format("\tprocess(clk, ce)\n")
|
||||
file.puts format("\tbegin\n")
|
||||
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
||||
file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
|
||||
file.puts format("\t\tend if;\n")
|
||||
file.puts format("\tend process;\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("end %s;\n", PROJECT_NAME)
|
||||
puts format("ROM file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
end
|
||||
if num_errors == 0
|
||||
|
||||
filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..pc-2)
|
||||
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
||||
end;
|
||||
if pc < (MAX_SIZE_ROM-1)
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
for i in (pc..(MAX_SIZE_ROM-2))
|
||||
file.puts "\t\t" + instr(0) + ",\n"
|
||||
end;
|
||||
file.puts "\t\t" + instr(0) + "\n"
|
||||
else
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
end
|
||||
file.puts format("\t);\n")
|
||||
puts format("PREINIT file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
end
|
||||
if num_errors == 0
|
||||
filename = format("rom_%s.tcl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
for i in (0..pc-1)
|
||||
# Chipscope 8.1
|
||||
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
||||
|
||||
# Chipscope 9.1
|
||||
file.puts format("\# %s", vhdl_comment_list[i])
|
||||
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
|
||||
end;
|
||||
puts format("TCL snippet written to \"%s\"\n",filename)
|
||||
file.close
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Output final statistics
|
||||
# --------------------------------------------------------
|
||||
if num_errors == 0
|
||||
puts "Program uses #{pc} instruction addresses"
|
||||
puts "No errors found"
|
||||
exit 0
|
||||
else
|
||||
puts "#{num_errors} errors found"
|
||||
exit 1
|
||||
end
|
||||
@@ -1,814 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: A small assembler for the JCPU
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
arg = $*
|
||||
FILE_SUFFIX = "jsm"
|
||||
IROM_MAX_SIZE = 1024
|
||||
IROM_ENTITY_NAME = "irom"
|
||||
IROM_DATA_TYPE = "inst_t"
|
||||
IROM_ADDR_TYPE = "inst_addr_t"
|
||||
XROM_MAX_SIZE = 256
|
||||
XROM_DATA_TYPE = "dmem_data_t"
|
||||
XROM_ADDR_TYPE = "dmem_addr_t"
|
||||
XROM_ENTITY_NAME = "xrom"
|
||||
OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
|
||||
|
||||
# --------------------------------------------------------
|
||||
class Parser
|
||||
def curr_segment
|
||||
@curr_segment
|
||||
end
|
||||
def curr_segment=(arg)
|
||||
@curr_segment=arg
|
||||
end
|
||||
def add_label(labelname, addr)
|
||||
@label_list = @label_list + [labelname, addr]
|
||||
end
|
||||
def getLabelIdByName(label)
|
||||
return @label_list.rindex(label)
|
||||
end
|
||||
def getLabelNameById(id)
|
||||
return @label_list[id]
|
||||
end
|
||||
def put_instr(name, lc, opc , op1 , op2)
|
||||
if get_instr != nil
|
||||
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
|
||||
exit 1
|
||||
end
|
||||
@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
|
||||
end
|
||||
def get_instr
|
||||
return @instr_list[@pc]
|
||||
end
|
||||
def put_xmem(value, lc)
|
||||
if get_xmem != nil
|
||||
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
|
||||
exit 1
|
||||
end
|
||||
@xmem[xmem_dc] = value
|
||||
@xmem_dc = xmem_dc + 1
|
||||
end
|
||||
def get_xmem
|
||||
return @xmem[xmem_dc]
|
||||
end
|
||||
def xmem
|
||||
return @xmem
|
||||
end
|
||||
def put_cmem(value, lc)
|
||||
if get_cmem(page) != nil
|
||||
STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
|
||||
exit 1
|
||||
end
|
||||
@cmem[page][cmem_dc] = value
|
||||
@cmem_dc[page] = cmem_dc + 1
|
||||
end
|
||||
def get_cmem(pg)
|
||||
return @cmem[pg][cmem_dc]
|
||||
end
|
||||
def cmem(page)
|
||||
return @cmem[page]
|
||||
end
|
||||
def cmem_dc=(addr)
|
||||
@cmem_dc[page] = addr
|
||||
end
|
||||
def cmem_dc
|
||||
@cmem_dc[page]
|
||||
end
|
||||
def xmem_dc=(addr)
|
||||
@xmem_dc = addr
|
||||
end
|
||||
def xmem_dc
|
||||
@xmem_dc
|
||||
end
|
||||
def page=(page)
|
||||
@page = page;
|
||||
end
|
||||
def page
|
||||
@page;
|
||||
end
|
||||
def pc=(pc)
|
||||
@pc = pc;
|
||||
if (pc > @pc_max)
|
||||
@pc_max = pc
|
||||
end
|
||||
end
|
||||
def pc
|
||||
@pc;
|
||||
end
|
||||
def pc_max
|
||||
@pc_max;
|
||||
end
|
||||
def instr_list
|
||||
@instr_list
|
||||
end
|
||||
def label_list
|
||||
@label_list
|
||||
end
|
||||
|
||||
def initialize()
|
||||
@pc_max = 0
|
||||
@pc = 0 # Program counter
|
||||
@cmem_dc = [0,0,0,0] # chip data counter
|
||||
@xmem_dc = 0 # xmem data counter
|
||||
@curr_segment = "UNDEF";
|
||||
@page = 0
|
||||
@label_list=[[],[]]
|
||||
@instr_list=[nil]
|
||||
@cmem = [[],[]];
|
||||
@xmem = [];
|
||||
end
|
||||
def method_missing(name, *args)
|
||||
puts "I don't know the method #{name}"
|
||||
end
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
def parse(name, obj)
|
||||
|
||||
lc = 0 # Line counter
|
||||
file = File.open(name, "r")
|
||||
|
||||
file.each do |raw_line|
|
||||
lc += 1
|
||||
|
||||
# Make all upper case
|
||||
iline = "#{raw_line}".strip
|
||||
|
||||
# Remove comments
|
||||
iline = iline.gsub(/;.*/, "")
|
||||
|
||||
# Split instruction at spaces
|
||||
iline_member = iline.split(" ")
|
||||
|
||||
if iline_member[0] == nil
|
||||
next
|
||||
end
|
||||
|
||||
mc = 0;
|
||||
label = nil
|
||||
clean_line = nil
|
||||
if (iline_member[0] =~ /\w+:/)
|
||||
mc += 1
|
||||
label = iline_member[0].delete(":")
|
||||
if obj.getLabelIdByName(label) != nil
|
||||
STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
|
||||
exit 1
|
||||
end
|
||||
end
|
||||
|
||||
token = iline_member[mc]
|
||||
if token
|
||||
token = token.upcase
|
||||
end
|
||||
|
||||
case token
|
||||
when nil
|
||||
if obj.curr_segment == "CMEM"
|
||||
curr_addr = format("0x%3.3X",obj.cmem_dc)
|
||||
elsif obj.curr_segment == "XMEM"
|
||||
curr_addr = format("0x%3.3X",obj.xmem_dc)
|
||||
elsif obj.curr_segment == "CODE"
|
||||
curr_addr = format("0x%3.3X",obj.pc)
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Undefined segment", lc)
|
||||
exit 1
|
||||
end
|
||||
when "INCLUDE"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
inc_name = iline_member[mc+1].delete("\"")
|
||||
puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
|
||||
parse(inc_name, obj)
|
||||
when "EQU"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
if 0 == (iline_member[mc+1] =~ /\d+/)
|
||||
curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
|
||||
else
|
||||
curr_addr = iline_member[mc+1]
|
||||
end
|
||||
when "ORG"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
|
||||
case obj.curr_segment
|
||||
when "CODE"
|
||||
obj.pc = offset
|
||||
curr_addr = format("0x%3.3X",obj.pc)
|
||||
when "CMEM"
|
||||
obj.cmem_dc = offset
|
||||
when "XMEM"
|
||||
obj.xmem_dc = offset
|
||||
|
||||
end
|
||||
when "CODE"
|
||||
curr_addr = format("0x%3.3X",obj.pc)
|
||||
obj.curr_segment = "CODE";
|
||||
when "CDATA", "CMEM"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
obj.curr_segment = "CMEM";
|
||||
obj.page = iline_member[mc+1].to_i(16)
|
||||
when "XDATA", "XMEM"
|
||||
obj.curr_segment = "XMEM";
|
||||
when "DC"
|
||||
len = 0;
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
if obj.curr_segment == "CMEM"
|
||||
STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
|
||||
exit 1
|
||||
elsif obj.curr_segment == "XMEM"
|
||||
curr_addr = format("0x%2.2X",obj.xmem_dc)
|
||||
dc_old = obj.xmem_dc;
|
||||
val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
|
||||
|
||||
# Parse string literals
|
||||
val_array.each do |item|
|
||||
if 0 == (item =~ /.*\".*\"/)
|
||||
str = item.delete("\"")
|
||||
puts item
|
||||
for nn in (0..str.length-1)
|
||||
if str[nn] > 31
|
||||
obj.put_xmem(str[nn], lc);
|
||||
puts "S: " + str[nn].to_s
|
||||
len += 1
|
||||
end
|
||||
end;
|
||||
else
|
||||
argument = item
|
||||
puts "B: " + argument
|
||||
obj.put_xmem(eval(argument), lc);
|
||||
len += 1
|
||||
end
|
||||
end
|
||||
puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
|
||||
exit 1
|
||||
end
|
||||
when "DB"
|
||||
if iline_member[mc+1] == nil
|
||||
STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
|
||||
exit 1
|
||||
end
|
||||
len = eval(iline_member[mc+1]).to_i
|
||||
if obj.curr_segment == "CMEM"
|
||||
curr_addr = format("0x%2.2X",obj.cmem_dc)
|
||||
puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
|
||||
for nn in (1..len)
|
||||
obj.put_cmem(0, lc)
|
||||
end
|
||||
elsif obj.curr_segment == "XMEM"
|
||||
curr_addr = format("0x%2.2X",obj.xmem_dc)
|
||||
puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
|
||||
for nn in (1..len)
|
||||
obj.put_xmem(0, lc)
|
||||
end
|
||||
else
|
||||
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
|
||||
exit 1
|
||||
end
|
||||
else
|
||||
if obj.curr_segment != "CODE"
|
||||
STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
|
||||
exit 1
|
||||
end
|
||||
|
||||
op_line = iline_member[mc+1..iline_member.nitems].to_s
|
||||
curr_addr = format("0x%3.3X",obj.pc)
|
||||
opc = token
|
||||
if iline_member[mc+1] != nil
|
||||
op1 = op_line.gsub(/,+.*$/, "")
|
||||
end
|
||||
if iline_member[mc+2] != nil
|
||||
op2 = op_line.scan(/,.+$/).to_s.delete(", ")
|
||||
end
|
||||
obj.put_instr(name, lc, opc, op1, op2)
|
||||
obj.pc = obj.pc + 1
|
||||
end;
|
||||
|
||||
# Push labels
|
||||
if label
|
||||
obj.add_label(label, curr_addr)
|
||||
end
|
||||
end
|
||||
file.close
|
||||
return obj
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Instruction formatting
|
||||
# --------------------------------------------------------
|
||||
def instr(opcode)
|
||||
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
|
||||
end
|
||||
|
||||
def tcl_bits(pc, opcode)
|
||||
return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
|
||||
end
|
||||
|
||||
def instr_k(opcode, k)
|
||||
return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
|
||||
end
|
||||
|
||||
def tcl_bits_k(pc, opcode, k)
|
||||
return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
|
||||
end
|
||||
|
||||
def instr_r(opcode, r)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
|
||||
end
|
||||
|
||||
def tcl_bits_r(pc, opcode, r)
|
||||
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
|
||||
end
|
||||
|
||||
def instr_kr(opcode, k, r)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
|
||||
end
|
||||
|
||||
def tcl_bits_kr(pc, opcode, k, r)
|
||||
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
|
||||
end
|
||||
|
||||
def instr_rk(opcode, r, k)
|
||||
return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
|
||||
end
|
||||
|
||||
def tcl_bits_rk(pc, opcode, r, k)
|
||||
return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
|
||||
end
|
||||
|
||||
def instr_rr(opcode, ra, rb)
|
||||
return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
|
||||
end
|
||||
|
||||
def tcl_bits_rr(pc, opcode, ra, rb)
|
||||
return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Open file
|
||||
# --------------------------------------------------------
|
||||
filename = arg.to_s
|
||||
if !File.exists?(filename)
|
||||
STDERR.puts "#{filename} does not exist"
|
||||
exit 1
|
||||
end
|
||||
PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Pass 1
|
||||
# --------------------------------------------------------
|
||||
first_pass = Parser.new();
|
||||
parse(filename, first_pass)
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Read mnemonic set
|
||||
# --------------------------------------------------------
|
||||
filename = OPC_LIST_NAME
|
||||
if !File.exists?(filename)
|
||||
STDERR.puts "#{filename} does not exist"
|
||||
exit 1
|
||||
end
|
||||
|
||||
mnemo_list = []
|
||||
num_opcodes = 0
|
||||
file = File.open(filename, "r")
|
||||
file.each do |raw_line|
|
||||
mnemo_list[num_opcodes] = raw_line.split(" ")[1]
|
||||
num_opcodes += 1
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Pass 2
|
||||
# --------------------------------------------------------
|
||||
pc = 0
|
||||
opc_start = 2
|
||||
num_errors = 0
|
||||
vhdl_trans_list = [nil]
|
||||
vhdl_comment_list = [nil]
|
||||
vhdl_tcl_list = [nil]
|
||||
|
||||
# ToDo: Use class-methods
|
||||
label_list = first_pass.label_list
|
||||
instr_list = first_pass.instr_list
|
||||
|
||||
instr_list.each do |instruct|
|
||||
|
||||
# puts instruct
|
||||
if instruct == nil
|
||||
vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
|
||||
vhdl_comment_list[pc] = format("0x%3.3X:", pc)
|
||||
vhdl_tcl_list[pc] = tcl_bits(pc, 0)
|
||||
pc += 1
|
||||
next
|
||||
end
|
||||
|
||||
# determine arglen of instruction
|
||||
ilen = 0
|
||||
if instruct[opc_start+1] == nil
|
||||
arglen = 0
|
||||
elsif instruct[opc_start+2] == nil
|
||||
arglen = 1
|
||||
elsif instruct[opc_start+3] == nil
|
||||
arglen = 2
|
||||
end
|
||||
|
||||
# Symbol substitution
|
||||
error = false
|
||||
for i in (1..2)
|
||||
subst_pos = opc_start+i
|
||||
if instruct[subst_pos] == nil
|
||||
next
|
||||
end
|
||||
expr_token = ""
|
||||
expr_subst = nil
|
||||
is_direct = true;
|
||||
|
||||
# checks R0 .. R16, Mnemonics
|
||||
instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
|
||||
if (nil != (instruct[subst_pos] =~ /'high/))
|
||||
instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
|
||||
end
|
||||
instr_str = instruct[subst_pos]
|
||||
if 0 == (instr_str =~ /\(.+\)/)
|
||||
instr_str = instr_str.delete("()")
|
||||
is_direct = false;
|
||||
end
|
||||
|
||||
expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
|
||||
if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
|
||||
idx = label_list.rindex(expr_token)
|
||||
if idx != nil
|
||||
expr_subst = label_list[idx+1]
|
||||
instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
|
||||
else
|
||||
STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
|
||||
error = true
|
||||
end
|
||||
end
|
||||
|
||||
if expr_subst != nil
|
||||
if 0 == (expr_subst =~ /\d+/)
|
||||
if is_direct == true
|
||||
instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
|
||||
else
|
||||
instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
|
||||
end
|
||||
else
|
||||
if 0 != (expr_subst =~ /R[0-9]+/)
|
||||
STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
|
||||
error = true
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
# Parse operands
|
||||
reg = [0,0]
|
||||
kk = 0
|
||||
format = instruct[opc_start]
|
||||
for i in (0..1)
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
|
||||
# Check indirect addressing
|
||||
reg[i] = instruct[opc_start+i+1].delete("R()").to_i
|
||||
format += "|R"
|
||||
if reg[i] > 15
|
||||
STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
|
||||
error = true
|
||||
end
|
||||
else
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
|
||||
kk = eval(instruct[opc_start+i+1].delete("()"))
|
||||
format += "|K"
|
||||
end
|
||||
end
|
||||
if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
|
||||
format += "i";
|
||||
end
|
||||
end
|
||||
|
||||
if error
|
||||
num_errors += 1
|
||||
break
|
||||
end
|
||||
|
||||
# Output instruction
|
||||
opcode = mnemo_list.rindex(format).to_i
|
||||
mnemo = instruct[2];
|
||||
|
||||
case format
|
||||
# Native instructions
|
||||
when "NOP", "HALT", "RET", "RETI", "SETC"
|
||||
vhdl_trans_list[pc] = instr(opcode)
|
||||
vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
|
||||
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
|
||||
when "MOVC|R|Ri", "MOVX|R|Ri"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
|
||||
when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
|
||||
when "MOVC|Ri|R", "MOVX|Ri|R"
|
||||
vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
|
||||
minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
|
||||
when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
|
||||
kk = kk % 256;
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
|
||||
when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
|
||||
when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
|
||||
kk = kk % 256;
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
|
||||
when "SUB|K|R", "SUBC|K|R"
|
||||
kk = kk % 256;
|
||||
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
|
||||
when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
|
||||
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
|
||||
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
|
||||
minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
|
||||
when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
|
||||
vhdl_trans_list[pc] = instr_k(opcode, kk)
|
||||
vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
|
||||
minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
|
||||
when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
|
||||
vhdl_trans_list[pc] = instr_r(opcode, reg[0])
|
||||
vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
# Synthetic instructions
|
||||
when "CLRC"
|
||||
kk = 0;
|
||||
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
|
||||
opcode = mnemo_list.rindex("SUB|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "TST|R"
|
||||
kk = 0
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("CMP|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "NEG|R"
|
||||
kk = 0
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("SUB|K|R").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "NOT|R"
|
||||
kk = 0
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("XOR|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "INC|R"
|
||||
kk = 1
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("ADD|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
when "DEC|R"
|
||||
kk = 1
|
||||
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
||||
opcode = mnemo_list.rindex("SUB|R|K").to_i
|
||||
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
||||
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
||||
else
|
||||
STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
|
||||
error = true
|
||||
end
|
||||
|
||||
if error
|
||||
num_errors += 1
|
||||
break
|
||||
end
|
||||
|
||||
vhdl_comment_list[pc] = minstr_comment
|
||||
|
||||
puts vhdl_trans_list[pc] + " -- " + minstr_comment
|
||||
|
||||
pc += 1
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Output ROM file
|
||||
# --------------------------------------------------------
|
||||
if num_errors == 0
|
||||
|
||||
# I-ROM VHDL-ROM
|
||||
filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
|
||||
file.puts format("\tPort (\n")
|
||||
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE)
|
||||
file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("END %s;\n", IROM_ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
|
||||
file.puts format("\n")
|
||||
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..[IROM_MAX_SIZE, pc].min-2)
|
||||
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
||||
end;
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("begin")
|
||||
file.puts format("\n")
|
||||
file.puts format("PROM_READ:")
|
||||
file.puts format("\tprocess(clk, ce)\n")
|
||||
file.puts format("\tbegin\n")
|
||||
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
||||
file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
|
||||
file.puts format("\t\tend if;\n")
|
||||
file.puts format("\tend process;\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("end %s;\n", PROJECT_NAME)
|
||||
puts format("I-ROM file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
# I-ROM VHDL-ROM (loadable)
|
||||
filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
|
||||
file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..pc-2)
|
||||
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
||||
end;
|
||||
if pc < (IROM_MAX_SIZE-1)
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
for i in (pc..(IROM_MAX_SIZE-2))
|
||||
file.puts "\t\t" + instr(0) + ",\n"
|
||||
end;
|
||||
file.puts "\t\t" + instr(0) + "\n"
|
||||
else
|
||||
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
||||
end
|
||||
file.puts format("\t);\n")
|
||||
puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
# I-ROM TCL-Loader
|
||||
filename = format("%s.irom.tcl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("# ---------------------------------------------------------------");
|
||||
file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
|
||||
file.puts format("# User 1")
|
||||
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
|
||||
for i in (0..pc-1)
|
||||
# Chipscope 8.1
|
||||
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
||||
|
||||
# Chipscope 9.1
|
||||
file.puts format("\# %s", vhdl_comment_list[i])
|
||||
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
|
||||
end;
|
||||
puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
# X-ROM VHDL-ROM
|
||||
filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
|
||||
file.puts format("\tPort (\n")
|
||||
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
|
||||
file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE)
|
||||
file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("END %s;\n", XROM_ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
|
||||
file.puts format("\n")
|
||||
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
|
||||
file.puts format("\n")
|
||||
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..XROM_MAX_SIZE-2)
|
||||
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
|
||||
end;
|
||||
i = XROM_MAX_SIZE-1
|
||||
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i)
|
||||
file.puts format("\t);\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("begin")
|
||||
file.puts format("\n")
|
||||
file.puts format("PROM_READ:")
|
||||
file.puts format("\tprocess(clk, ce)\n")
|
||||
file.puts format("\tbegin\n")
|
||||
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
||||
file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
|
||||
file.puts format("\t\tend if;\n")
|
||||
file.puts format("\tend process;\n")
|
||||
file.puts format("\n")
|
||||
file.puts format("end %s;\n", PROJECT_NAME)
|
||||
puts format("X-ROM file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
# X-ROM VHDL-ROM (loadable)
|
||||
filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
|
||||
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
|
||||
file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
|
||||
file.puts format("\t(\n");
|
||||
for i in (0..XROM_MAX_SIZE-2)
|
||||
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
|
||||
end;
|
||||
i = XROM_MAX_SIZE-1
|
||||
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i)
|
||||
file.puts format("\t);\n")
|
||||
puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
# X-ROM TCL-Loader
|
||||
filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
|
||||
file = File.open(filename, "w")
|
||||
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
||||
file.puts format("# ---------------------------------------------------------------");
|
||||
file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
|
||||
file.puts format("# User 2")
|
||||
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
|
||||
for i in (0..first_pass.xmem.length-1)
|
||||
# Chipscope 8.1
|
||||
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
||||
|
||||
# Chipscope 9.1
|
||||
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
|
||||
end;
|
||||
puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
|
||||
file.close
|
||||
|
||||
end
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Output final statistics
|
||||
# --------------------------------------------------------
|
||||
if num_errors == 0
|
||||
puts "Program uses #{first_pass.pc_max} instruction addresses"
|
||||
puts "No errors found"
|
||||
exit 0
|
||||
else
|
||||
puts "#{num_errors} errors found"
|
||||
exit 1
|
||||
end
|
||||
|
||||
@@ -1,72 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; lcd.inc.jsm
|
||||
; -------------------------------------------------
|
||||
; needs xio-address equates for
|
||||
; reg_cg_char_addr: equ 0xXX ; RW
|
||||
; reg_cg_line_addr: equ 0xXX ; RW
|
||||
; reg_cg_data: equ 0xXX ; RW
|
||||
; reg_cg_ctrl: equ 0xXX ; WO
|
||||
|
||||
; needs delay.inc.jsm
|
||||
|
||||
; -------------------------------------------------
|
||||
cg_clr_line: push R0
|
||||
mov R0, 2
|
||||
xout (reg_cg_ctrl), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
cg_clr_screen: push R0
|
||||
mov R0, 1
|
||||
xout (reg_cg_ctrl), R0
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R0 : char address
|
||||
; R1 : line address
|
||||
cg_set_addr: call cg_wait_rdy
|
||||
xout (reg_cg_line_addr), R1
|
||||
xout (reg_cg_char_addr), R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R0 : character
|
||||
cg_putchar: call cg_wait_rdy
|
||||
xout (reg_cg_data), R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to string
|
||||
cg_puts: push R0
|
||||
cg_p_lp: movx R0, (R1)
|
||||
inc R1
|
||||
tst R0
|
||||
jz ex_cgp
|
||||
call cg_putchar
|
||||
jmp cg_p_lp
|
||||
ex_cgp: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to string
|
||||
cg_clr_puts: call cg_clr_line
|
||||
call cg_puts
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; R1 : ptr to string
|
||||
cg_puts_clr: call cg_puts
|
||||
call cg_clr_line
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
cg_wait_rdy: push R0
|
||||
cg_wr_lp: xin R0, (reg_hwstat)
|
||||
and R0, 0x02
|
||||
jz cg_wr_lp
|
||||
pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
@@ -1,7 +0,0 @@
|
||||
; JCPU On-Chip register
|
||||
cpu_revision: equ 0x00 ; RO
|
||||
cpu_control: equ 0x01 ; R/W
|
||||
cpu_status: equ 0x02 ; RO
|
||||
cpu_int_ctrl: equ 0x03 ; RW
|
||||
cpu_cmem_high: equ 0x04 ; RW
|
||||
cpu_stack_high: equ 0x05 ; RW
|
||||
@@ -1,64 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; Delays
|
||||
; -------------------------------------------------
|
||||
delay1s: push R15
|
||||
mov R15, 10
|
||||
loop1s: call delay100ms
|
||||
dec R15
|
||||
jnz loop1s
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100ms: push R15
|
||||
mov R15, 10
|
||||
loop100ms: call delay10ms
|
||||
dec R15
|
||||
jnz loop100ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10ms: push R15
|
||||
mov R15, 10
|
||||
loop10ms: call delay1ms
|
||||
dec R15
|
||||
jnz loop10ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1ms: push R15
|
||||
mov R15, 10
|
||||
loop1ms: call delay100us
|
||||
dec R15
|
||||
jnz loop1ms
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay100us: push R15
|
||||
mov R15, 10
|
||||
loop100us: call delay10us
|
||||
dec R15
|
||||
jnz loop100us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay10us: push R15
|
||||
mov R15, 99
|
||||
loop10us: nop
|
||||
nop
|
||||
nop
|
||||
dec R15
|
||||
jnz loop10us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
delay1us: push R15
|
||||
mov R15, 9
|
||||
loop1us: nop
|
||||
nop
|
||||
nop
|
||||
dec R15
|
||||
jnz loop1us
|
||||
pop R15
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
@@ -1,208 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; lcd.inc.jsm
|
||||
; -------------------------------------------------
|
||||
; needs xmem-address definition for
|
||||
; - lcd_port (LCD-Base)
|
||||
|
||||
; needs delay.inc.jsm
|
||||
|
||||
; -------------------------------------------------
|
||||
lcd_cmd: equ 0x00
|
||||
lcd_rd: equ 0x20
|
||||
lcd_data: equ 0x40
|
||||
lcd_enable: equ 0x80
|
||||
|
||||
LCD_CMD_Z1: equ 0x80
|
||||
LCD_CMD_Z2: equ 0xC0
|
||||
LCD_CMD_CLEAR: equ 0x01
|
||||
|
||||
; -------------------------------------------------
|
||||
; Init LCD
|
||||
; -------------------------------------------------
|
||||
LCD_init: mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call _write_lcd
|
||||
call delay10ms
|
||||
mov R2, 0x00
|
||||
mov R0, 0x03
|
||||
call _write_lcd
|
||||
call delay10ms
|
||||
|
||||
mov R2, 0x00
|
||||
mov R0, 0x02
|
||||
call _write_lcd
|
||||
call delay1ms
|
||||
|
||||
; 1. Function set: 4-Bit mode, two display lines
|
||||
mov R0, 0x28
|
||||
call LCD_writecmd
|
||||
|
||||
; 2. Display on, no cursor
|
||||
mov R0, 0x0C
|
||||
call LCD_writecmd
|
||||
|
||||
; 3. Cursor shift during write
|
||||
mov R0, 0x06
|
||||
call LCD_writecmd
|
||||
|
||||
; 4. Display clear
|
||||
mov R0, 0x01
|
||||
call LCD_writecmd
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_waitbsy
|
||||
; -------------------------------------------------
|
||||
LCD_waitbsy: push R0
|
||||
bsy_loop: call LCD_readstat
|
||||
and R0, 0x80
|
||||
jz ex_bsy
|
||||
call delay1us
|
||||
jmp bsy_loop
|
||||
ex_bsy: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writecmd
|
||||
; -------------------------------------------------
|
||||
; R0 = cmd
|
||||
LCD_writeaddr:
|
||||
LCD_writecmd: push R2
|
||||
mov R2, lcd_cmd
|
||||
call LCD_write
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_putsx
|
||||
; -------------------------------------------------
|
||||
; R1 = address of null-terminated string in XMEM
|
||||
LCD_putsx: push R0
|
||||
putsx_loop: movx R0, (R1)
|
||||
inc R1
|
||||
tst R0
|
||||
jz putsx_ex
|
||||
call LCD_writechar
|
||||
jmp putsx_loop
|
||||
putsx_ex: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_putsc
|
||||
; -------------------------------------------------
|
||||
; R1 = address of null-terminated string in CMEM
|
||||
LCD_putsc: push R0
|
||||
putsc_loop: movc R0, (R1)
|
||||
inc R1
|
||||
tst R0
|
||||
jz putsc_ex
|
||||
call LCD_writechar
|
||||
jmp putsc_loop
|
||||
putsc_ex: pop R0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_writechar
|
||||
; -------------------------------------------------
|
||||
; R0 = char
|
||||
LCD_writedata:
|
||||
LCD_writechar: push R2
|
||||
mov R2, lcd_data
|
||||
call LCD_write
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_write
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
; R2 = register
|
||||
LCD_write: call LCD_waitbsy
|
||||
push R0
|
||||
swap R0
|
||||
call _write_lcd
|
||||
pop R0
|
||||
call _write_lcd
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_readstat
|
||||
; -------------------------------------------------
|
||||
; R0 = status
|
||||
LCD_readstat: push R2
|
||||
mov R2, lcd_cmd
|
||||
call LCD_read
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; LCD_read
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
; R2 = register
|
||||
LCD_read: call _read_lcd
|
||||
swap R0
|
||||
push R0
|
||||
call _read_lcd
|
||||
pop R2
|
||||
or R0, R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; _write
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
_write_lcd: push R1
|
||||
|
||||
and R0, 0x0F
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, R0
|
||||
or R1, R2
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
or R1, lcd_rd
|
||||
xout (lcd_port), R1
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; _read
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
_read_lcd: push R1
|
||||
|
||||
mov R1, lcd_rd
|
||||
or R1, R2
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
mov R1, lcd_rd
|
||||
or R1, R2
|
||||
or R1, lcd_enable
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
xin R0, (lcd_port)
|
||||
and R0, 0x0F
|
||||
|
||||
mov R1, lcd_rd
|
||||
or R1, R2
|
||||
xout (lcd_port), R1
|
||||
call delay1us
|
||||
|
||||
pop R1
|
||||
ret
|
||||
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; mul8x8.inc.jsm
|
||||
; -------------------------------------------------
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter:
|
||||
; R0 : operand 1
|
||||
; R1 : operand 2
|
||||
; Return:
|
||||
; R0 : product low
|
||||
; R1 : product high
|
||||
mul8x8: push R2
|
||||
push R3
|
||||
push R4
|
||||
|
||||
mov R4, R1
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
mov R3, 0
|
||||
|
||||
loop1: cmp R4, 0x01
|
||||
jeq ende1
|
||||
|
||||
shr R4
|
||||
jnc next1
|
||||
|
||||
add R2, R0
|
||||
addc R3, R1
|
||||
|
||||
next1: shl R0
|
||||
rolc R1
|
||||
jmp loop1
|
||||
|
||||
ende1: add R0, R2
|
||||
addc R1, R3
|
||||
|
||||
pop R4
|
||||
pop R3
|
||||
pop R2
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
@@ -1,32 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; uart.inc.jsm
|
||||
; -------------------------------------------------
|
||||
; needs xmem-address definition for
|
||||
; - uart_status (Status register)
|
||||
; - uart_data (Data register)
|
||||
|
||||
; -------------------------------------------------
|
||||
; sout
|
||||
; -------------------------------------------------
|
||||
; R0 = input
|
||||
sout: push R1
|
||||
sout1: xin R1, (uart_status)
|
||||
and R1, 0x02
|
||||
jnz sout1
|
||||
xout (uart_data), R0
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; sin
|
||||
; -------------------------------------------------
|
||||
; R0 = output
|
||||
sin: push R1
|
||||
sin1: xin R1, (uart_status)
|
||||
and R1, 0x10
|
||||
jnz sin1
|
||||
xin R0, (uart_data)
|
||||
pop R1
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
@@ -1,32 +0,0 @@
|
||||
; -------------------------------------------------
|
||||
; utils.inc.jsm
|
||||
; -------------------------------------------------
|
||||
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0 : Bin value in lower nibble
|
||||
; Return
|
||||
; R0 : Hex character representing lower nibble
|
||||
nibble2hex: and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
jlt isNum1
|
||||
add R0, 0x07
|
||||
isNum1: add R0, 0x30
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Parameter
|
||||
; R0 : Bin value
|
||||
; Return
|
||||
; R0 : Hex character high
|
||||
; R1 : Hex character low
|
||||
bin2hex: push R0
|
||||
call nibble2hex
|
||||
mov R1, R0
|
||||
pop R0
|
||||
swap R0
|
||||
call nibble2hex
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
@@ -1,64 +0,0 @@
|
||||
0 NOP
|
||||
1 HALT
|
||||
2 MOV|R|R
|
||||
3 MOV|R|K
|
||||
4 MOVX|R|Ri
|
||||
5 MOVX|R|Ki
|
||||
6 MOVX|Ri|R
|
||||
7 MOVX|Ri|K
|
||||
8 MOVX|Ki|R
|
||||
9 MOVC|R|Ri
|
||||
10 MOVC|R|Ki
|
||||
11 MOVC|Ri|R
|
||||
12 MOVC|Ri|K
|
||||
13 MOVC|Ki|R
|
||||
14 CMP|R|R
|
||||
15 CMP|R|K
|
||||
16 ADD|R|R
|
||||
17 ADD|R|K
|
||||
18 ADDC|R|R
|
||||
19 ADDC|R|K
|
||||
20 SUB|R|R
|
||||
21 SUB|R|K
|
||||
22 SUBC|R|R
|
||||
23 SUBC|R|K
|
||||
24 AND|R|R
|
||||
25 AND|R|K
|
||||
26 OR|R|R
|
||||
27 OR|R|K
|
||||
28 XOR|R|R
|
||||
29 XOR|R|K
|
||||
30 SHL|R
|
||||
31 SHR|R
|
||||
32 ROL|R
|
||||
33 ROR|R
|
||||
34 ROLC|R
|
||||
35 RORC|R
|
||||
36 XOUT|Ki|R
|
||||
37 XOUT|Ri|K
|
||||
38 COUT|Ki|R
|
||||
39 COUT|Ri|K
|
||||
40 XIN|R|Ki
|
||||
41 CIN|R|Ki
|
||||
42 SWAP|R
|
||||
43 SETC
|
||||
44 UNDEF
|
||||
45 UNDEF
|
||||
46 SUB|K|R
|
||||
47 SUBC|K|R
|
||||
48 JMP|K
|
||||
49 JZ|K
|
||||
50 JNZ|K
|
||||
51 JC|K
|
||||
52 JNC|K
|
||||
53 JLT|K
|
||||
54 JGT|K
|
||||
55 JLE|K
|
||||
56 JGE|K
|
||||
57 JEQ|K
|
||||
58 JNE|K
|
||||
59 CALL|K
|
||||
60 PUSH|R
|
||||
61 POP|R
|
||||
62 RET
|
||||
63 RETI
|
||||
@@ -1,20 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
st = "\033[7m"
|
||||
en = "\033[m"
|
||||
|
||||
while TRUE
|
||||
print "str> "
|
||||
STDOUT.flush
|
||||
str = gets
|
||||
break if not str
|
||||
str.chop!
|
||||
print "pat> "
|
||||
STDOUT.flush
|
||||
re = gets
|
||||
break if not re
|
||||
re.chop!
|
||||
str.gsub! re, "#{st}\\&#{en}"
|
||||
print str, "\n"
|
||||
end
|
||||
print "\n"
|
||||
@@ -1,61 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,44 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
|
||||
template = <<'END'
|
||||
-- (tv #1342) read output FIFO
|
||||
(
|
||||
cycles => 1,
|
||||
cm_i => bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
|
||||
sep => msg(""),
|
||||
cm_o => bus_no_ack,
|
||||
irq => (others => '0')
|
||||
),
|
||||
|
||||
-- (tv #1343) wait while FIFO is read
|
||||
(
|
||||
cycles => 2,
|
||||
cm_i => bus_wait_ack,
|
||||
sep => msg(""),
|
||||
cm_o => bus_no_ack,
|
||||
irq => (others => '0')
|
||||
),
|
||||
|
||||
-- (tv #1343) wait for ack
|
||||
(
|
||||
cycles => 1,
|
||||
cm_i => bus_wait_ack,
|
||||
sep => msg(""),
|
||||
cm_o => bus_read_ack(dat => #{exp_data}),
|
||||
irq => (others => '0')
|
||||
),
|
||||
|
||||
END
|
||||
|
||||
puts "KS-128 testvectors:\n"
|
||||
puts "\n" * 3
|
||||
|
||||
|
||||
0.upto(10) { |sk_no|
|
||||
3.downto(0) { |sl_no|
|
||||
exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
|
||||
t = template.gsub(/"/, '\\"')
|
||||
puts eval("format(\"#{t}\")")
|
||||
}
|
||||
}
|
||||
@@ -1,32 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
@@ -1,151 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,15 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../src/dpram.vhd"
|
||||
vcom -explicit -93 "../src/async_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/tb_async_fifo_ctrl.vhd"
|
||||
vsim -t 1ps -lib work tb_async_fifo_ctrl
|
||||
view wave
|
||||
do {tb_async_fifo_ctrl.wdo}
|
||||
view structure
|
||||
view signals
|
||||
|
||||
run 10us
|
||||
@@ -1,36 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
|
||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
|
||||
add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
|
||||
add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
|
||||
add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
|
||||
configure wave -namecolwidth 190
|
||||
configure wave -valuecolwidth 80
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {115874 ps} {612358 ps}
|
||||
@@ -1,13 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../src/tb_gray_counter.vhd"
|
||||
vsim -t 1ps -lib work tb_gray_counter
|
||||
view wave
|
||||
do {tb_gray_counter.wdo}
|
||||
view structure
|
||||
view signals
|
||||
|
||||
run 1us
|
||||
@@ -1,25 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_gray_counter/rst
|
||||
add wave -noupdate -format Logic /tb_gray_counter/ce
|
||||
add wave -noupdate -format Logic /tb_gray_counter/clk
|
||||
add wave -noupdate -format Literal /tb_gray_counter/bcnt
|
||||
add wave -noupdate -format Literal /tb_gray_counter/bnxt
|
||||
add wave -noupdate -format Literal /tb_gray_counter/gcnt
|
||||
add wave -noupdate -format Literal /tb_gray_counter/gnxt
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {20898 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {134759 ps}
|
||||
@@ -1,15 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../src/dpram.vhd"
|
||||
vcom -explicit -93 "../src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/tb_sync_fifo_ctrl.vhd"
|
||||
vsim -t 1ps -lib work tb_sync_fifo_ctrl
|
||||
view wave
|
||||
do {tb_sync_fifo_ctrl.wdo}
|
||||
view structure
|
||||
view signals
|
||||
|
||||
run 10us
|
||||
@@ -1,32 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
|
||||
configure wave -namecolwidth 190
|
||||
configure wave -valuecolwidth 80
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {2166667 ps}
|
||||
@@ -1,244 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity async_fifo_ctrl is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
almost_full_thresh : integer := 6;
|
||||
almost_empty_thresh : integer := 2
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk_w : in STD_LOGIC;
|
||||
clk_r : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
ptr_w : out unsigned (addr_width-1 downto 0);
|
||||
ptr_r : out unsigned (addr_width-1 downto 0);
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC
|
||||
);
|
||||
end async_fifo_ctrl;
|
||||
|
||||
architecture Behavioral of async_fifo_ctrl is
|
||||
|
||||
signal gcnt_w : unsigned (addr_width downto 0);
|
||||
signal gcnt2_w : unsigned (addr_width downto 0);
|
||||
signal bcnt2_aw : unsigned (addr_width downto 0);
|
||||
signal bcnt_w : unsigned (addr_width downto 0);
|
||||
signal gnxt_w : unsigned (addr_width downto 0);
|
||||
signal bnxt_w : unsigned (addr_width downto 0);
|
||||
signal gcnt_r : unsigned (addr_width downto 0);
|
||||
signal gcnt2_r : unsigned (addr_width downto 0);
|
||||
signal bcnt2_ar : unsigned (addr_width downto 0);
|
||||
signal bcnt_r : unsigned (addr_width downto 0);
|
||||
signal gnxt_r : unsigned (addr_width downto 0);
|
||||
signal bnxt_r : unsigned (addr_width downto 0);
|
||||
|
||||
signal empty, full : std_logic;
|
||||
signal write_inhibit, read_inhibit : std_logic;
|
||||
signal winc, rinc : std_logic;
|
||||
|
||||
-- synthesis translate_off
|
||||
signal diffw : signed (addr_width downto 0);
|
||||
signal diffr : signed (addr_width downto 0);
|
||||
-- synthesis translate_on
|
||||
|
||||
begin
|
||||
|
||||
ptr_w <= bcnt_w(addr_width-1 downto 0);
|
||||
ptr_r <= bcnt_r(addr_width-1 downto 0);
|
||||
winc <= we and (not write_inhibit);
|
||||
rinc <= re and (not read_inhibit);
|
||||
fifo_full <= write_inhibit;
|
||||
fifo_empty <= read_inhibit;
|
||||
|
||||
proc_write_inhibit:
|
||||
process(rst, clk_w)
|
||||
begin
|
||||
if rst = '1' then
|
||||
write_inhibit <= '0';
|
||||
elsif rising_edge(clk_w) then
|
||||
write_inhibit <= full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_read_inhibit:
|
||||
process(rst, clk_r)
|
||||
begin
|
||||
if rst = '1' then
|
||||
read_inhibit <= '1';
|
||||
elsif rising_edge(clk_r) then
|
||||
read_inhibit <= empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_grptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
gcnt2_r <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_gwptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
gcnt2_w <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_full:
|
||||
process(gnxt_w, gcnt2_r)
|
||||
begin
|
||||
if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
|
||||
full <= '1';
|
||||
else
|
||||
full <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_empty:
|
||||
process(gnxt_r, gcnt2_w)
|
||||
begin
|
||||
if (gnxt_r = gcnt2_w) then
|
||||
empty <= '1';
|
||||
else
|
||||
empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_arptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
bcnt2_ar <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_awptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
bcnt2_aw <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk_w)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffw <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk_r)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffr <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_gray_counter_w : entity work.gray_counter
|
||||
generic map (
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk_w,
|
||||
ce => winc,
|
||||
bcnt => bcnt_w,
|
||||
bnxt => bnxt_w,
|
||||
gcnt => gcnt_w,
|
||||
gnxt => gnxt_w
|
||||
);
|
||||
|
||||
inst_gray_counter_r : entity work.gray_counter
|
||||
generic map (
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk_r,
|
||||
ce => rinc,
|
||||
bcnt => bcnt_r,
|
||||
bnxt => bnxt_r,
|
||||
gcnt => gcnt_r,
|
||||
gnxt => gnxt_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram;
|
||||
|
||||
architecture Behavioral of dpram is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,46 +0,0 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package fifo_ctrl_pkg is
|
||||
|
||||
-- Constants
|
||||
-- Types
|
||||
|
||||
-- Functions
|
||||
function bin2gray(xb : unsigned) return unsigned;
|
||||
function gray2bin(xg : unsigned) return unsigned;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
package body fifo_ctrl_pkg is
|
||||
|
||||
function bin2gray(xb : unsigned) return unsigned is
|
||||
variable xg : unsigned(xb'left downto xb'right);
|
||||
begin
|
||||
|
||||
xg(xg'left) := xb(xb'left);
|
||||
for i in 1 to xb'left loop
|
||||
xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
|
||||
end loop;
|
||||
|
||||
return xg;
|
||||
end bin2gray;
|
||||
|
||||
function gray2bin(xg : unsigned) return unsigned is
|
||||
variable xb : unsigned(xg'left downto xg'right);
|
||||
begin
|
||||
|
||||
xb(xb'left) := xg(xg'left);
|
||||
for i in 1 to xg'left loop
|
||||
xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
|
||||
end loop;
|
||||
|
||||
return xb;
|
||||
end gray2bin;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity gray_counter is
|
||||
Generic (
|
||||
width : natural := 3;
|
||||
init_value : natural := 0
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
bcnt : out unsigned (width-1 downto 0);
|
||||
bnxt : out unsigned (width-1 downto 0);
|
||||
gcnt : out unsigned (width-1 downto 0);
|
||||
gnxt : out unsigned (width-1 downto 0)
|
||||
);
|
||||
end gray_counter;
|
||||
|
||||
architecture Behavioral of gray_counter is
|
||||
|
||||
signal cntb : unsigned (width-1 downto 0);
|
||||
signal nxtb : unsigned (width-1 downto 0);
|
||||
signal cntg : unsigned (width-1 downto 0);
|
||||
signal nxtg : unsigned (width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
bnxt <= nxtb;
|
||||
gnxt <= nxtg;
|
||||
|
||||
process(rst, clk, ce, cntb, nxtb)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cntb <= to_unsigned(init_value, width);
|
||||
nxtb <= to_unsigned(init_value, width);
|
||||
cntg <= to_unsigned(init_value, width);
|
||||
nxtg <= to_unsigned(init_value, width);
|
||||
bcnt <= to_unsigned(init_value, width);
|
||||
gcnt <= to_unsigned(init_value, width);
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
bcnt <= nxtb;
|
||||
gcnt <= nxtg;
|
||||
cntb <= nxtb;
|
||||
cntg <= nxtg;
|
||||
end if;
|
||||
nxtg <= bin2gray(nxtb);
|
||||
nxtb <= cntb;
|
||||
if ce = '1' then
|
||||
nxtb <= cntb + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,199 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity sync_fifo_ctrl is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
almost_full_thresh : integer := 6;
|
||||
almost_empty_thresh : integer := 2
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
ptr_w : out unsigned (addr_width-1 downto 0);
|
||||
ptr_r : out unsigned (addr_width-1 downto 0);
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC
|
||||
);
|
||||
end sync_fifo_ctrl;
|
||||
|
||||
architecture Behavioral of sync_fifo_ctrl is
|
||||
|
||||
signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
|
||||
signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
|
||||
signal empty, full : std_logic;
|
||||
signal pre_empty, pre_full : std_logic;
|
||||
signal was_write : std_logic;
|
||||
signal write, read : std_logic;
|
||||
signal diff : unsigned (addr_width downto 0);
|
||||
|
||||
begin
|
||||
|
||||
read <= '1' when re = '1' and empty = '0' else '0';
|
||||
write <= '1' when we = '1' and full = '0' else '0';
|
||||
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
|
||||
|
||||
proc_diff_gen:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
diff <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' and read = '0' then
|
||||
diff <= diff + 1;
|
||||
elsif write = '0' and read = '1' then
|
||||
diff <= diff - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_full_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
full <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
full <= pre_full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_empty_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
empty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
empty <= pre_empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_w:
|
||||
process(was_write, pW_next, pR_next, pW, pR, we, re)
|
||||
begin
|
||||
if (pW_next = pR) and (we = '1' or was_write = '1') then
|
||||
pre_full <= '1';
|
||||
else
|
||||
pre_full <= '0';
|
||||
end if;
|
||||
if (pR_next = pW) and (re = '1' or was_write = '0') then
|
||||
pre_empty <= '1';
|
||||
else
|
||||
pre_empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_flag_write:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
was_write <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' then
|
||||
was_write <= '1';
|
||||
elsif read = '1' then
|
||||
was_write <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_w:
|
||||
process(rst, clk, pW, we, full)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pW <= to_unsigned(0, addr_width);
|
||||
pW_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
pW <= pW_next;
|
||||
end if;
|
||||
end if;
|
||||
pW_next <= pW;
|
||||
if we = '1' and full = '0' then
|
||||
pW_next <= pW + 1;
|
||||
end if;
|
||||
ptr_w <= pW;
|
||||
end process;
|
||||
|
||||
proc_ptr_r:
|
||||
process(rst, clk, pR_next, pR, re, empty)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pR <= to_unsigned(0, addr_width);
|
||||
pR_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if re = '1' then
|
||||
pR <= pR_next;
|
||||
end if;
|
||||
end if;
|
||||
pR_next <= pR;
|
||||
if re = '1' and empty = '0' then
|
||||
pR_next <= pR + 1;
|
||||
end if;
|
||||
ptr_r <= pR_next;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,176 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_async_fifo_ctrl IS
|
||||
END tb_async_fifo_ctrl;
|
||||
|
||||
ARCHITECTURE behavior OF tb_async_fifo_ctrl IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD_W : time := 10 ns;
|
||||
constant PERIOD_R : time := 20 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk_w : STD_LOGIC := '0';
|
||||
signal clk_r : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
signal mem_we : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal wdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata2 : unsigned (7 downto 0) := (others => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
din <= wdata;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.async_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk_w,
|
||||
clk_r => clk_r,
|
||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram: entity work.dpram
|
||||
GENERIC MAP (
|
||||
addr_width => ADDR_WIDTH,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk_w,
|
||||
clkb => clk_r,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => mem_we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => din,
|
||||
dout_b => dout
|
||||
);
|
||||
|
||||
tb_clk_w : PROCESS
|
||||
BEGIN
|
||||
clk_w <= not clk_w;
|
||||
wait for PERIOD_W/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_clk_r : PROCESS
|
||||
BEGIN
|
||||
clk_r <= not clk_r;
|
||||
wait for PERIOD_R/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD_W;
|
||||
rst <= '0';
|
||||
wait for 5*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 15*PERIOD_W;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 15*PERIOD_R;
|
||||
read_en <= '1';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en and not fifo_full;
|
||||
mem_we <= we;
|
||||
|
||||
tb_w : PROCESS(rst, clk_w)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
wdata <= (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if we = '1' then
|
||||
wdata <= wdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en and not fifo_empty;
|
||||
|
||||
tb_r : PROCESS(rst, clk_r)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
rdata <= (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
rdata2 <= rdata;
|
||||
if re = '1' then
|
||||
assert rdata2 = dout report "FIFO read error!" severity failure;
|
||||
rdata <= rdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,83 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_gray_counter
|
||||
-- Module Name: tb_gray_counter.vhd
|
||||
-- Project Name: gray_counter package
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
ENTITY tb_gray_counter IS
|
||||
END tb_gray_counter;
|
||||
|
||||
ARCHITECTURE behavior OF tb_gray_counter IS
|
||||
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant WIDTH : integer := 3;
|
||||
|
||||
--Signals
|
||||
signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal ce : STD_LOGIC := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_gray_counter : entity work.gray_counter
|
||||
generic map (width => WIDTH)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
bcnt => bcnt,
|
||||
bnxt => bnxt,
|
||||
gcnt => gcnt,
|
||||
gnxt => gnxt
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_counter : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
wait for 4*PERIOD;
|
||||
rst <= '0';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '1';
|
||||
wait for 3*PERIOD;
|
||||
ce <= '0';
|
||||
wait for 4*PERIOD;
|
||||
ce <= '1';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '0';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '1';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,221 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_sync_fifo_ctrl IS
|
||||
END tb_sync_fifo_ctrl;
|
||||
|
||||
ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
signal mem_we : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal wdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata2 : unsigned (7 downto 0) := (others => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
din <= wdata;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.sync_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram: entity work.dpram
|
||||
GENERIC MAP (
|
||||
addr_width => ADDR_WIDTH,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => mem_we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => din,
|
||||
dout_b => dout
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD;
|
||||
rst <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 3*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 4*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 17*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 15*PERIOD;
|
||||
read_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en and not fifo_full;
|
||||
mem_we <= we;
|
||||
|
||||
tb_w : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
wdata <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
wdata <= wdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en and not fifo_empty;
|
||||
|
||||
tb_r : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
rdata <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
rdata2 <= rdata;
|
||||
if re = '1' then
|
||||
assert rdata = dout report "FIFO read error!" severity failure;
|
||||
rdata <= rdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,297 +0,0 @@
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.5 [en] (X11; I; SunOS 5.7 sun4u) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<p>The <tt>fo</tt> function is currently overloaded as follows:
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double-quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO has been developed with this latter package, and still
|
||||
refers to this package by default. However, PCK_FIO works with
|
||||
<tt>IEEE.numeric_std</tt>
|
||||
as well. To use <tt>IEEE.numeric_std</tt>, replace the reference to <tt>IEEE.std_logic_arith</tt>
|
||||
in the source code. This needs to be done consistently in a design
|
||||
database (e.g. in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution is a file <tt>TB_PCK_FIO.vhd</tt> with a test
|
||||
bench for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company-wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some
|
||||
simulators/versions have problems with the package. The following is an
|
||||
overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" >
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO handling</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
|
||||
<caption ALIGN=BOTTOM>PCK_FIO and various simulators/versions</caption>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
@@ -1,206 +0,0 @@
|
||||
PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO
|
||||
-----------------------------------------
|
||||
|
||||
This is the result of running the PCK_FIO testbench.
|
||||
This file should be compared with PCK_FIO.out.gold, which is
|
||||
the reference output. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
--------------------
|
||||
-- Basic features --
|
||||
--------------------
|
||||
|
||||
-- First some auxiliary declarations
|
||||
> file RESULT: text is out "PCK_FIO.out";
|
||||
> variable L: line;
|
||||
> variable BoolTrue: boolean := TRUE;
|
||||
> variable BoolFalse: boolean := FALSE;
|
||||
> variable IntPos: integer := 5678;
|
||||
> variable BigIntPos: integer := 12345678;
|
||||
> variable IntNeg: integer := -8765;
|
||||
> variable BigIntNeg: integer := -87654321;
|
||||
> variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
> variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
> variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
> variable BitX: std_logic := 'X';
|
||||
> variable Bit1: std_logic := '1';
|
||||
> variable Bit0: std_logic := '0';
|
||||
|
||||
|
||||
-- fprint call with no arguments
|
||||
> fprint(RESULT, L, "No arguments.\n);"
|
||||
No arguments.
|
||||
|
||||
-- Special characters need to be escaped
|
||||
> fprint(RESULT, L, "Special characters: \% \\ " \n");
|
||||
Special characters: % \ "
|
||||
|
||||
-- Various format specifiers interprete the same object differently
|
||||
> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);"
|
||||
> fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
> );
|
||||
Format specifiers: 0x52 82 1010010 U:1010010
|
||||
|
||||
-- Format string can be shortened by using the iteration specifier
|
||||
> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);"
|
||||
> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
> );
|
||||
Iteration specifier: 0x52 0x12 0x52 0x12
|
||||
|
||||
------------------------------------
|
||||
-- Support for bit-oriented types --
|
||||
------------------------------------
|
||||
|
||||
-- Reasonable format
|
||||
> fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F
|
||||
|
||||
-- Decimal format
|
||||
> fprint(RESULT, L, "Decimal format: %7{%d }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Decimal format: 18 82 18 -46 -1 1 -1 1 0
|
||||
|
||||
-- Bit format
|
||||
> fprint(RESULT, L, "Bit format: %7{%b }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0
|
||||
|
||||
|
||||
-- Alignment
|
||||
-- Template of the call: (<fs> stands for the format specifier)
|
||||
|
||||
> fprint(RESULT, L, "Bitvectors with <fs>: %4{<fs>|}\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)
|
||||
> );
|
||||
|
||||
-- Results of the call with various format specifiers
|
||||
|
||||
Bitvectors with %1r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %2r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %3r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %4r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52|
|
||||
|
||||
Bitvectors with %-1r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-2r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-3r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-4r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 |
|
||||
|
||||
Bitvectors with %1d: 82|18|18|-46|
|
||||
Bitvectors with %2d: 82|18|18|-46|
|
||||
Bitvectors with %3d: 82| 18| 18|-46|
|
||||
Bitvectors with %4d: 82| 18| 18| -46|
|
||||
Bitvectors with %5d: 82| 18| 18| -46|
|
||||
Bitvectors with %6d: 82| 18| 18| -46|
|
||||
Bitvectors with %7d: 82| 18| 18| -46|
|
||||
Bitvectors with %8d: 82| 18| 18| -46|
|
||||
Bitvectors with %9d: 82| 18| 18| -46|
|
||||
|
||||
Bitvectors with %-1d: 82|18|18|-46|
|
||||
Bitvectors with %-2d: 82|18|18|-46|
|
||||
Bitvectors with %-3d: 82 |18 |18 |-46|
|
||||
Bitvectors with %-4d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-5d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-6d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-7d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-8d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-9d: 82 |18 |18 |-46 |
|
||||
|
||||
|
||||
-------------------------------
|
||||
-- Support for integer types --
|
||||
-------------------------------
|
||||
|
||||
|
||||
-- Template of the call: (<fs> stands for the format specifier)
|
||||
|
||||
> fprint(RESULT, L, "Integers with <fs>: %4{<fs>|}\n",
|
||||
> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
> );
|
||||
|
||||
-- Results of the call with various format specifiers
|
||||
|
||||
Integers with %5d: 5678|-8765|12345678|-87654321|
|
||||
Integers with %6d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %7d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %8d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %9d: 5678| -8765| 12345678|-87654321|
|
||||
Integers with %10d: 5678| -8765| 12345678| -87654321|
|
||||
|
||||
Integers with %-5d: 5678 |-8765|12345678|-87654321|
|
||||
Integers with %-6d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-7d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-8d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-9d: 5678 |-8765 |12345678 |-87654321|
|
||||
Integers with %-10d: 5678 |-8765 |12345678 |-87654321 |
|
||||
|
||||
Integers with %5r: 5678|-8765| 5678|-4321|
|
||||
Integers with %6r: 5678|- 8765| 45678|-54321|
|
||||
Integers with %7r: 5678|- 8765| 345678|-654321|
|
||||
Integers with %8r: 5678|- 8765| 2345678|-7654321|
|
||||
Integers with %9r: 5678|- 8765| 12345678|-87654321|
|
||||
Integers with %10r: 5678|- 8765| 12345678|- 87654321|
|
||||
|
||||
Integers with %-5r: 5678|-8765| 1234|-8765|
|
||||
Integers with %-6r: 5678 |-8765 | 12345|-87654|
|
||||
Integers with %-7r: 5678 |-8765 | 123456|-876543|
|
||||
Integers with %-8r: 5678 |-8765 | 1234567|-8765432|
|
||||
Integers with %-9r: 5678 |-8765 | 12345678|-87654321|
|
||||
Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 |
|
||||
|
||||
|
||||
----------------------
|
||||
-- Support for time --
|
||||
----------------------
|
||||
-- For portability reasons, time is converted
|
||||
-- into an integer value (of nanoseconds)
|
||||
> wait for 648 ns
|
||||
> fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
The time is now 648 ns
|
||||
|
||||
----------------------------------------
|
||||
-- Erroneous calls and error messages --
|
||||
----------------------------------------
|
||||
|
||||
-- Less arguments than formats specifiers
|
||||
> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
82 18
|
||||
** Warning: FIO_PrintLastValue: Format specifier beyond last argument
|
||||
** in format string: "%d %d %d %d \n"
|
||||
** ------^
|
||||
|
||||
-- Unsupported format specifier
|
||||
> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
0x52
|
||||
** Warning: FIO_PrintArg: Unexpected format specifier 'v'
|
||||
** in format string: "%r %v %r %r\n"
|
||||
** ----^
|
||||
** Assuming 'q' to proceed: V:0010010 0x52 0x12
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Things you wouldn't expect to work --
|
||||
----------------------------------------
|
||||
|
||||
-- Nested iteration
|
||||
> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>>
|
||||
@@ -1,916 +0,0 @@
|
||||
---- File: PCK_FIO.vhd
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
----
|
||||
---- Revision history:
|
||||
----
|
||||
---- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $
|
||||
---- $Revision: 1.1 $
|
||||
---- $Log: not supported by cvs2svn $
|
||||
---- Revision 1.16 1999/04/21 08:28:46 jand
|
||||
---- Tested with IEEE.numeric_std
|
||||
---- Small patch for Leapfrog
|
||||
----
|
||||
---- Revision 1.14 1997/07/14 10:16:04 jand
|
||||
---- prefix/postfix for bits/bitvectors set to empty strings by default
|
||||
----
|
||||
---- Revision 1.13 1997/07/11 17:42:57 jand
|
||||
---- Corrected Easics address
|
||||
----
|
||||
---- Revision 1.12 1997/07/11 17:38:49 jand
|
||||
---- Improved prefix/postfix support
|
||||
----
|
||||
---- Revision 1.11 1995/11/15 13:46:02 jand
|
||||
---- Catched integer'low value in fo for integers
|
||||
----
|
||||
---- Revision 1.10 1995/08/11 16:42:26 jand
|
||||
---- Reimplemented FIO_FormatExpand as a procedure in an attempt to
|
||||
---- avoid memory leakage problems in VSS
|
||||
----
|
||||
---- Revision 1.9 1995/08/09 13:47:51 jand
|
||||
---- Removed array of line trick in fprint for less memory, less
|
||||
---- CPU time, and more conservatism in general
|
||||
---- Rearranged FIO_PrintValue call so that fprint remains concise
|
||||
----
|
||||
---- Revision 1.8 1995/08/09 10:32:27 jand
|
||||
---- Removed fprint_flat to have a single call level
|
||||
---- Added explicit deallocators of line variables (has strong influence
|
||||
---- on memory usage in VSS - and possibly CPU time)
|
||||
---- Redefined 'fo' for type time to make it more portable
|
||||
----
|
||||
---- Revision 1.7 1995/08/07 08:56:04 jand
|
||||
---- Improved conciseness of fprint argument handling through array of line type
|
||||
----
|
||||
---- Revision 1.6 1995/08/04 18:19:13 jand
|
||||
---- Increase # arguments from 16 to 32
|
||||
---- Corrected bug within fprint 's call to Arg16
|
||||
---- Added support for bit format specifier 'b'
|
||||
----
|
||||
---- Revision 1.5 1995/08/02 10:22:37 jand
|
||||
---- Release 1.1 under GNU
|
||||
----
|
||||
---- Revision 1.4 1995/08/01 11:15:52 jand
|
||||
---- Added escaping during iteration string read
|
||||
----
|
||||
---- Revision 1.3 1995/08/01 08:23:47 jand
|
||||
---- Many improvements in robustness, conciseness and coding style
|
||||
----
|
||||
---- Revision 1.2 1995/07/30 16:15:43 jand
|
||||
---- Improved robustness for release to the world
|
||||
----
|
||||
---- Revision 1.1 1995/07/30 14:21:30 jand
|
||||
---- Initial revision
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
-- use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
@@ -1,72 +0,0 @@
|
||||
# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
# $Log: not supported by cvs2svn $
|
||||
# Revision 1.3 1999/04/21 08:08:35 jand
|
||||
# Tested with IEEE.numeric_std
|
||||
# Small patch for Leapfrog
|
||||
#
|
||||
#
|
||||
|
||||
PCK_FIO, Version 1.16
|
||||
Copyright (C) 1995, 1999 Easics NV
|
||||
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Contents
|
||||
--------
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO.vhd: VHDL source of the PCK_FIO package
|
||||
TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
------------
|
||||
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO.vhd into the same library.
|
||||
|
||||
If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need
|
||||
to edit the source code of the package and the test bench and replace the
|
||||
package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
To install the documentation, point your web browser to the file PCK_FIO.html
|
||||
and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
------------------
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
@@ -1,504 +0,0 @@
|
||||
---- File: TB_PCK_FIO.vhd
|
||||
----
|
||||
---- TBC_PCK_FIO: a test bench for the PCK_FIO package.
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 396 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
----
|
||||
---- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $
|
||||
---- $Revision: 1.1 $
|
||||
---- $Log: not supported by cvs2svn $
|
||||
---- Revision 1.7 1999/04/21 08:23:53 jand
|
||||
---- Tested with IEEE.numeric_std
|
||||
---- Small patch for Leapfrog
|
||||
----
|
||||
---- Revision 1.3 1998/09/29 10:09:44 vhdl
|
||||
---- to EASICS_PACKAGES
|
||||
----
|
||||
---- Revision 1.2 1998/09/29 09:17:51 vhdl
|
||||
---- library EASICS_PACKAGES;
|
||||
----
|
||||
---- Revision 1.1 1998/09/29 09:15:44 vhdl
|
||||
---- Initial revision
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
-- use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text is out "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n);""\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
@@ -1,86 +0,0 @@
|
||||
---- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
Changes from version 1.16 to version 2002.07
|
||||
============================================
|
||||
|
||||
PCK_FIO is now distributed under the GNU Lesser General Public Licencse
|
||||
instead of the ordinary GPL, to better reflect intended usage.
|
||||
|
||||
Cosmetic changes in source code to correct some typos in the testbench output.
|
||||
A new testbench is also supplied.
|
||||
|
||||
The package now uses IEEE.numeric_std as default.
|
||||
|
||||
URL http://www.easics.com has been made part of address.
|
||||
|
||||
Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
|
||||
Because of backwards-incompatibility, it has been necessary to supply
|
||||
different sets of files for 1987 and 1993.
|
||||
|
||||
Split the packages into a separate file for the header and a
|
||||
separate file for the body (in compliance with Easics' guidelines).
|
||||
|
||||
These changes resulted in the files:
|
||||
|
||||
Files for VHDL-1993:
|
||||
--------------------
|
||||
PCK_FIO_1993.vhd : the source code of the header file for the package
|
||||
PCK_FIO_1993_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1993.vhd: the testbench for the package
|
||||
|
||||
Files for VHDL-1987:
|
||||
--------------------
|
||||
PCK_FIO_1987.vhd: the source code of the header file for the package
|
||||
PCK_FIO_1987_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1987.vhd: the testbench for the package
|
||||
|
||||
Updated README and PCK_FIO.html to support these changes.
|
||||
|
||||
Adapted package files to support NUL termination of strings.
|
||||
fo(Arg: string) now prints the string until the first NUL.
|
||||
Several examples of its use are demonstrated in the supplied testbenches.
|
||||
|
||||
Made cosmetic changes to code to improve readability.
|
||||
|
||||
Acknowledgment
|
||||
--------------
|
||||
These changes have been implemented by Peter Geens.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,339 +0,0 @@
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<br>
|
||||
<pre>The <tt>fo</tt> function is currently overloaded as follows:</pre>
|
||||
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<p><br>To support null-terminated strings, the function <tt>fo</tt>(Arg:
|
||||
string) processes <tt>Arg</tt> up to the first <tt>NUL</tt> character,
|
||||
if any. If you want the whole string to be outputted you can just enter
|
||||
the string as a direct argument in <tt>fprint</tt>. See also the
|
||||
examples in the testbench.
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO works with both packages, but refers to the standard
|
||||
package <tt>IEEE.numeric_std</tt> by default. To use <tt>IEEE.std_logic_arith</tt>
|
||||
instead, replace the reference to <tt>IEEE.numeric_std</tt> in the source
|
||||
code. This needs to be done consistently in a design database (e.g.
|
||||
in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution are the files <tt>TB_PCK_FIO_1987.vhd and
|
||||
TB_PCK_FIO_1993</tt> with a test bench,depending on the standard you're
|
||||
running, for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is available in either standard VHDL Std1076-1987 or standard
|
||||
VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
|
||||
with the package. The following is an overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1987 and various simulators/versions</caption>
|
||||
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO_1987</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Incorrect output in compiled mode, interpreted mode works</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr NOSAVE>
|
||||
<td NOSAVE>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1993 and various simulators/versions</caption>
|
||||
|
||||
<tr NOSAVE>
|
||||
<th NOSAVE>Simulator</th>
|
||||
|
||||
<th NOSAVE>PCK_FIO_1993</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Compile errors due to improper handling of files by Synopsys</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.06</td>
|
||||
|
||||
<td>works fine</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim 5.4c and higher</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
@@ -1,105 +0,0 @@
|
||||
---- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
@@ -1,821 +0,0 @@
|
||||
---- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
-- unsigned to decimal
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
-- signed to decimal
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
-- string to decimal
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
-- boolean (0,1) to decimal
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
-- boolean (T,F) to decimal
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
-- test for end of format string
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
-- auxilary function fgets(Arg: string)
|
||||
-- gives index until first NUL
|
||||
-- reads string from 1 to Arg'length
|
||||
function fgets (Arg: string) return integer is
|
||||
variable index: integer := Arg'length;
|
||||
begin
|
||||
for i in 1 to Arg'length loop
|
||||
if Arg(i) = NUL then
|
||||
index := i - 1;
|
||||
exit;
|
||||
else
|
||||
null;
|
||||
end if;
|
||||
end loop;
|
||||
return index;
|
||||
end fgets;
|
||||
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg(1 to fgets(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,108 +0,0 @@
|
||||
---- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
@@ -1,814 +0,0 @@
|
||||
---- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
-- unsigned to decimal
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
-- signed to decimal
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
-- string to decimal
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
-- boolean (0,1) to decimal
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
-- boolean (T,F) to decimal
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
-- test for end of format string
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
-- auxilary function fgets(Arg :string)
|
||||
-- returns index of first NUL in Arg or if no NUL is present just Arg'length
|
||||
-- goes through Arg from 1 to Arg'length
|
||||
function fgets (Arg: string) return integer is
|
||||
variable index: integer := Arg'length;
|
||||
begin
|
||||
for i in 1 to Arg'length loop
|
||||
if Arg(i) = NUL then
|
||||
index := i - 1;
|
||||
exit;
|
||||
else
|
||||
null;
|
||||
end if;
|
||||
end loop;
|
||||
return index;
|
||||
end fgets;
|
||||
|
||||
-- returns the Arg string until the first NUL was encountered
|
||||
-- if fo is used on a string with NUL in it it will stop reading the rest
|
||||
-- of the string, even if a larger field width has been supplied. fo will
|
||||
-- then just pad the remaining characters with blanco's
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg(1 to fgets(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
---- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Version 2002.07
|
||||
===============
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
|
||||
PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
|
||||
TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
|
||||
TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
============
|
||||
|
||||
VHDL-1987
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
|
||||
|
||||
VHDL-1993
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
|
||||
|
||||
Numeric packages
|
||||
----------------
|
||||
If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
|
||||
to edit the source code of the package, both header and body, and the test bench
|
||||
and replace the package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
To install the documentation, put the file point PCK_FIO.html in a path of
|
||||
your choosing, point your web browser to it, and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
==================
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,531 +0,0 @@
|
||||
---- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text is out "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
constant TempString: string :="ABC" & NUL & "DEF";
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n" &
|
||||
"> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n"");\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n"&
|
||||
"--Testing string manipulation--\n"&
|
||||
"-------------------------------\n");
|
||||
fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
|
||||
& " & NUL & ""DEF""\n");
|
||||
-- temp_string: string:="ABC"&NUL&"DEF"
|
||||
-- test for detecting NUL in string
|
||||
fprint(RESULT, L, "\n--test for NUL ending in strings\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
|
||||
fprint(RESULT, L, fo(TempString));
|
||||
|
||||
-- direct inclusion of string in fprint should give whole string
|
||||
fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
|
||||
fprint(RESULT, L, TempString & "\n");
|
||||
|
||||
-- influence of given width
|
||||
|
||||
fprint(RESULT, L, "\n--if there are less characters in the given string then"
|
||||
& " in the width fo will\n"&
|
||||
"-- pad the remaining with blanco's according to the given justification\n");
|
||||
fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%-5s",fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
|
||||
fprint(RESULT, L, "%9s", TempString);
|
||||
fprint(RESULT, L, "\n\n-- if the width is smaller then the number" &
|
||||
" of characters in the string fprint\n" &
|
||||
"-- will output the string with the minimum of characters needed\n");
|
||||
fprint(RESULT, L, "\n--with specified width,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%2s",fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
|
||||
fprint(RESULT, L, "%4s", TempString);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
|
||||
|
||||
@@ -1,536 +0,0 @@
|
||||
---- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text open write_mode is "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
constant TempString: string :="ABC" & NUL & "DEF";
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n" &
|
||||
"> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n"");\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n"&
|
||||
"--Testing string manipulation--\n"&
|
||||
"-------------------------------\n");
|
||||
fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
|
||||
& " & NUL & ""DEF""\n");
|
||||
-- TempString: string:="ABC" & NUL & "DEF"
|
||||
-- test for detecting NUL in string
|
||||
fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
|
||||
fprint(RESULT, L, fo(TempString));
|
||||
|
||||
-- direct inclusion of string in fprint should give whole string
|
||||
fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
|
||||
fprint(RESULT, L, TempString & "\n");
|
||||
|
||||
-- influence of given width
|
||||
|
||||
fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
|
||||
"-- pad the remaining with blanco's according to the given justification\n");
|
||||
fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%-5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
|
||||
fprint(RESULT, L, "%9s", TempString);
|
||||
fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
|
||||
"-- will output the string with the minimum of characters needed\n");
|
||||
fprint(RESULT, L, "\n--with specified width,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%2s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
|
||||
fprint(RESULT, L, "%4s", TempString);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user