jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added shift_en input

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@197 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-04 15:15:54 +00:00
parent 9675773b2a
commit fe60d9d7a4
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/filter/src/delay_line.vhd
+3 -2
View File
@@ -42,6 +42,7 @@ Port
( (
clk : in std_logic; clk : in std_logic;
ce : in std_logic; ce : in std_logic;
shift_en : in std_logic;
delay : in natural range 0 to ntaps-1; delay : in natural range 0 to ntaps-1;
din : in sfixed; din : in sfixed;
dout : out sfixed dout : out sfixed
@@ -64,9 +65,9 @@ shift_register:
process(clk) process(clk)
variable delay_pipe : delay_pipe_t; variable delay_pipe : delay_pipe_t;
begin begin
if rising_edge(clk) then if rising_edge(clk) and ce = '1' then
dout <= delay_pipe(delay); dout <= delay_pipe(delay);
if ce = '1' then if shift_en = '1' then
delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din; delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din;
end if; end if;
end if; end if;