diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
index 96f2dc8..890a93f 100644
--- a/lib/filter/src/delay_line.vhd
+++ b/lib/filter/src/delay_line.vhd
@@ -42,6 +42,7 @@ Port
 (
 	clk			: in std_logic;
 	ce			: in std_logic;
+	shift_en	: in std_logic;
 	delay		: in natural range 0 to ntaps-1;
 	din			: in sfixed;
 	dout		: out sfixed
@@ -64,9 +65,9 @@ shift_register:
 	process(clk)
 	variable delay_pipe	: delay_pipe_t;
 	begin
-		if rising_edge(clk) then
+		if rising_edge(clk) and ce = '1' then
 			dout			<= delay_pipe(delay);
-			if ce = '1' then
+			if shift_en = '1' then
 				delay_pipe		:= delay_pipe(delay_pipe'left-1 downto 0) & din;
 			end if;
 		end if;