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- debug output reverted to unsigned vector

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-> (record doesnt work for netlist synthesis)
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git-svn-id: http://moon:8086/svn/vhdl/trunk@1020 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-24 11:44:56 +00:00
parent 11c9696320
commit f81cd4018f
3 changed files with 8 additions and 10 deletions
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lib/CPUs/MIPS/src/core/mips_top.vhd
+3 -3
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@@ -38,7 +38,7 @@ entity mips_top is
);
Port
(
debug : out chip_debug_t;
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
@@ -189,8 +189,8 @@ architecture rtl of mips_top is
begin
-------------------------------------------------------------------
debug.imem_err <= imem_err;
debug.dmem_err <= dmem_err;
debug(0) <= imem_err;
debug(1) <= dmem_err;
process(CLK_I)
variable reset_delay : unsigned (31 downto 0);