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- minor changes in register interface

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git-svn-id: http://moon:8086/svn/vhdl/trunk@824 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-25 21:11:10 +00:00
parent c0291407fe
commit f602a4baa7
1 changed files with 14 additions and 10 deletions
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lib/emac/src/emac_top_jb.vhd
+14 -10
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@@ -49,17 +49,19 @@ ARCHITECTURE behavior OF emac_top_jb IS
signal tx_ctrl_in : tx_ctrl_in_t; signal tx_ctrl_in : tx_ctrl_in_t;
signal tx_ctrl_out : tx_ctrl_out_t; signal tx_ctrl_out : tx_ctrl_out_t;
signal tx_din : unsigned(31 downto 0); signal tx_din : unsigned(31 downto 0);
signal tx_din_vld : std_logic;
signal rx_ctrl_in : rx_ctrl_in_t; signal rx_ctrl_in : rx_ctrl_in_t;
signal rx_ctrl_out : rx_ctrl_out_t; signal rx_ctrl_out : rx_ctrl_out_t;
signal rx_dout : unsigned(31 downto 0); signal rx_dout : unsigned(31 downto 0);
signal rx_dout_vld : std_logic;
signal rx_int_en : std_logic; signal rx_int_en : std_logic;
signal tx_int_en : std_logic; signal tx_int_en : std_logic;
signal irq_rx : std_logic; signal irq_rx : std_logic;
signal irq_tx : std_logic; signal irq_tx : std_logic;
signal if_rdy : std_logic;
begin begin
SRDY_O <= CYC_I; SRDY_O <= CYC_I;
@@ -71,9 +73,9 @@ registers_write:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
tx_ctrl_in.data_vld <= '0'; tx_din_vld <= '0';
tx_ctrl_in.tx_req_en <= '0'; tx_ctrl_in.tx_req_en <= '0';
rx_ctrl_in.uncommit <= '0'; rx_ctrl_in.uncommit <= '0';
if RST_I = '1' then if RST_I = '1' then
rx_int_en <= '0'; rx_int_en <= '0';
tx_int_en <= '0'; tx_int_en <= '0';
@@ -93,7 +95,7 @@ registers_write:
tx_ctrl_in.tx_size <= DAT_I(31 downto 16); tx_ctrl_in.tx_size <= DAT_I(31 downto 16);
when "0010" => when "0010" =>
tx_ctrl_in.data_vld <= '1'; tx_din_vld <= '1';
tx_din <= DAT_I; tx_din <= DAT_I;
when others => null; when others => null;
@@ -107,13 +109,14 @@ registers_read:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
rx_ctrl_in.data_read <= '0'; rx_ctrl_in.data_read <= '0';
ACK_O <= '0'; ACK_O <= rx_dout_vld and CYC_I and not WE_I;
DAT_O <= rx_dout;
if (STB_I and CYC_I) = '1' then if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(5 downto 2) is case ADDR_I(5 downto 2) is
when "0000" => when "0000" =>
ACK_O <= not WE_I;
DAT_O <= (others => '0');
DAT_O(31) <= tx_ctrl_in.tx_er; DAT_O(31) <= tx_ctrl_in.tx_er;
DAT_O(30) <= mii_rx_er; DAT_O(30) <= mii_rx_er;
DAT_O(29) <= mii_col; DAT_O(29) <= mii_col;
@@ -123,12 +126,11 @@ registers_read:
DAT_O(5) <= tx_int_en; DAT_O(5) <= tx_int_en;
DAT_O(4) <= rx_int_en; DAT_O(4) <= rx_int_en;
when "0001" => when "0001" =>
ACK_O <= not WE_I;
DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size; DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
when "0010" => when "0010" =>
rx_ctrl_in.data_read <= not WE_I; rx_ctrl_in.data_read <= not WE_I;
ACK_O <= rx_ctrl_out.data_vld;
DAT_O <= rx_dout;
when others => null; when others => null;
end case; end case;
@@ -155,6 +157,7 @@ inst_emac_rx : entity work.emac_rx
( (
clk => CLK_I, clk => CLK_I,
rst => RST_I, rst => RST_I,
dout_vld => rx_dout_vld,
dout => rx_dout, dout => rx_dout,
ctrl_in => rx_ctrl_in, ctrl_in => rx_ctrl_in,
ctrl_out => rx_ctrl_out, ctrl_out => rx_ctrl_out,
@@ -178,6 +181,7 @@ inst_emac_tx : entity work.emac_tx
( (
clk => CLK_I, clk => CLK_I,
rst => RST_I, rst => RST_I,
din_vld => tx_din_vld,
din => tx_din, din => tx_din,
ctrl_in => tx_ctrl_in, ctrl_in => tx_ctrl_in,
ctrl_out => tx_ctrl_out, ctrl_out => tx_ctrl_out,