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- pulled PHY out of sdram_ctrl_top.vhd

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- sdram_ctrl_frontend64_wb.vhd implements J-Bus interface and exports abstract PHY interface
- ctrl_ddr_wb64 wraps sdram_ctrl_frontend64_wb and adds specific PHY. This is now our new top level file

git-svn-id: http://moon:8086/svn/vhdl/trunk@1190 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 09:05:49 +00:00
parent ce636ef1ec
commit f55028c696
7 changed files with 210 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
+154
View File
@@ -0,0 +1,154 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity ctrl_ddr_wb64 is
Generic
(
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4
);
Port
(
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SDRAM_CLK_I : in STD_LOGIC;
SDRAM_CLK_FB_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- SDRAM signals
sd_clk_p : out STD_LOGIC;
sd_clk_n : out STD_LOGIC;
sd_cke : out STD_LOGIC;
sd_cs_n : out STD_LOGIC;
sd_cas_n : out STD_LOGIC;
sd_ras_n : out STD_LOGIC;
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
);
end ctrl_ddr_wb64;
architecture struct of ctrl_ddr_wb64 is
signal sdram_clk0 : std_logic;
signal sdram_rst0 : std_logic;
signal phy_ctrl : phy_ctrl_t;
signal phy_in : phy_in_t;
signal phy_out : phy_out_t;
begin
-- DDR SDRAM Controller Core
sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BURST_LEN => BURST_LEN,
F_SYSCLK => F_SYSCLK,
F_SDRCLK => F_SDRCLK,
FIFO_DEPTH => FIFO_DEPTH
)
PORT MAP
(
RST_I => RST_I,
CLK_I => CLK_I,
SDRAM_RST0 => sdram_rst0,
SDRAM_CLK0 => sdram_clk0,
CYC_I => CYC_I,
STB_I => STB_I,
SEL_I => SEL_I,
WE_I => WE_I,
ACK_O => ACK_O,
SRDY_O => SRDY_O,
MRDY_I => MRDY_I,
ADDR_I => ADDR_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
-- PHY signals
phy_in => phy_in,
phy_out => phy_out,
phy_ctrl => phy_ctrl
);
-- DDR phy
inst_sdram_phy : entity work.sdram_phy
Generic map
(
F_SDRCLK => F_SDRCLK
)
Port map
(
-- Clock interface
rst => RST_I,
clk => SDRAM_CLK_I,
clk_fb => SDRAM_CLK_FB_I,
clk0_out => sdram_clk0,
rst0_out => sdram_rst0,
-- PHY interface
phy_in => phy_in,
phy_out => phy_out,
phy_ctrl => phy_ctrl,
-- SDRAM part interface
part_clk_p => sd_clk_p,
part_clk_n => sd_clk_n,
part_addr => sd_addr,
part_ba => sd_ba,
part_dm => sd_dm,
part_dqs => sd_dqs,
part_data => sd_data,
part_cs_n => sd_cs_n,
part_we_n => sd_we_n,
part_cas_n => sd_cas_n,
part_ras_n => sd_ras_n,
part_cke => sd_cke
);
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+2 -2
View File
@@ -34,7 +34,7 @@ use UNISIM.vcomponents.all;
entity sdram_phy is entity sdram_phy is
Generic Generic
( (
f_sdrclk : real := 100.0 F_SDRCLK : real := 100.0
); );
Port Port
( (
@@ -101,7 +101,7 @@ begin
inst_sdram_clk : entity work.sdram_clk inst_sdram_clk : entity work.sdram_clk
GENERIC MAP GENERIC MAP
( (
clk_in_freq => f_sdrclk, clk_in_freq => F_SDRCLK,
clk0_out_phaseshift => 0, clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0 clk1_out_phaseshift => 0
) )
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+8 -8
View File
@@ -31,8 +31,8 @@ use work.sdram_types.all;
entity sdram_cmd is entity sdram_cmd is
Generic Generic
( (
f_sdrclk : real := 100.0; F_SDRCLK : real := 100.0;
BL : natural := 2 BURST_LEN : natural := 2
); );
Port Port
( (
@@ -68,13 +68,13 @@ architecture behaviour of sdram_cmd is
( SD_DESELECT => (0 ), ( SD_DESELECT => (0 ),
SD_NOP => (0 ), SD_NOP => (0 ),
SD_LMR => (TMRD-1 ), SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk)-1), SD_ACT => (to_cycles(TRCD, F_SDRCLK)-1),
SD_READ => (TCAS-1 ), SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk)-1), SD_WRITE => (to_cycles(TWR, F_SDRCLK)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk)-1), SD_PRE => (to_cycles(TRP, F_SDRCLK)-1),
SD_BST => (0 ), SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk)-1), SD_AR => (to_cycles(TRFC, F_SDRCLK)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk)-1) SD_SR => (to_cycles(TRFC, F_SDRCLK)-1)
); );
begin begin
@@ -91,7 +91,7 @@ fsm_sdr_state:
cc_preset <= TIMING(cmd); cc_preset <= TIMING(cmd);
burst_load_en <= '0'; burst_load_en <= '0';
cmd_ack <= '0'; cmd_ack <= '0';
burst_preset <= BL/2-1; burst_preset <= BURST_LEN/2-1;
phy_ctrl.re <= '0'; phy_ctrl.re <= '0';
phy_ctrl.drive_en <= '0'; phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0'; phy_ctrl.we <= '0';
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+5 -5
View File
@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is entity sdram_ctrl is
Generic Generic
( (
f_sysclk : real := 100.0; BURST_LEN : natural := 2;
BL : natural := 2 F_SYSCLK : real := 100.0
); );
Port ( Port (
rst : in STD_LOGIC; rst : in STD_LOGIC;
@@ -55,12 +55,12 @@ end sdram_ctrl;
architecture behaviour of sdram_ctrl is architecture behaviour of sdram_ctrl is
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); constant LMR_BURST_LEN : natural := NextExpBaseTwo(BURST_LEN);
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t; signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk); constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, F_SYSCLK);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic; signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic; signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic; signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic; signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk); constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, F_SYSCLK);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic; signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic; signal refresh_cnt_rst : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+22 -40
View File
@@ -32,17 +32,17 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is entity sdram_ctrl_frontend64_wb is
Generic Generic
( (
BL : natural := 2; BURST_LEN : natural := 2;
f_sysclk : real := 100.0; F_SYSCLK : real := 100.0;
f_sdrclk : real := 100.0; F_SDRCLK : real := 100.0;
fifo_depth : integer := 4 FIFO_DEPTH : integer := 4
); );
Port Port
( (
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
SDRAM_CLK_I : in STD_LOGIC; SDRAM_RST0 : in STD_LOGIC;
SDRAM_CLK_FB_I : in STD_LOGIC; SDRAM_CLK0 : in STD_LOGIC;
CYC_I : in STD_LOGIC; CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC; STB_I : in STD_LOGIC;
@@ -55,6 +55,11 @@ entity sdram_ctrl_frontend64_wb is
DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0); DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0); DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- Phy interface
phy_ctrl : out phy_ctrl_t;
phy_in : out phy_in_t;
phy_out : in phy_out_t;
-- SDRAM signals -- SDRAM signals
sd_clk_p : out STD_LOGIC; sd_clk_p : out STD_LOGIC;
sd_clk_n : out STD_LOGIC; sd_clk_n : out STD_LOGIC;
@@ -74,12 +79,6 @@ end sdram_ctrl_frontend64_wb;
architecture struct of sdram_ctrl_frontend64_wb is architecture struct of sdram_ctrl_frontend64_wb is
signal SDRAM_CLK0 : std_logic;
signal SDRAM_RST0 : std_logic;
signal phy_in : phy_in_t;
signal phy_out : phy_out_t;
signal u_addr : user_addr_t; signal u_addr : user_addr_t;
signal u_tag_in : user_tag_t; signal u_tag_in : user_tag_t;
signal u_cmd : user_cmd_t; signal u_cmd : user_cmd_t;
@@ -130,7 +129,7 @@ begin
inst_cat_fifo: entity work.fifo_sync inst_cat_fifo: entity work.fifo_sync
GENERIC MAP GENERIC MAP
( (
addr_width => fifo_depth, addr_width => FIFO_DEPTH,
data_width => CAT_FIFO_WIDTH data_width => CAT_FIFO_WIDTH
) )
PORT MAP PORT MAP
@@ -151,7 +150,7 @@ begin
inst_write_fifo: entity work.fifo_async inst_write_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => fifo_depth, addr_width => FIFO_DEPTH,
data_width => write_fifo_din'length data_width => write_fifo_din'length
) )
PORT MAP PORT MAP
@@ -173,7 +172,7 @@ begin
inst_read_fifo: entity work.fifo_async inst_read_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => fifo_depth, addr_width => FIFO_DEPTH,
data_width => read_fifo_din'length data_width => read_fifo_din'length
) )
PORT MAP PORT MAP
@@ -195,10 +194,10 @@ begin
inst_sdram_ctrl_top : entity work.sdram_ctrl_top inst_sdram_ctrl_top : entity work.sdram_ctrl_top
Generic map Generic map
( (
BL => BL, BURST_LEN => BURST_LEN,
f_sysclk => f_sysclk, F_SYSCLK => F_SYSCLK,
f_sdrclk => f_sdrclk, F_SDRCLK => F_SDRCLK,
fifo_depth => fifo_depth FIFO_DEPTH => FIFO_DEPTH
) )
Port map Port map
( (
@@ -206,10 +205,8 @@ begin
sys_rst_in => RST_I, sys_rst_in => RST_I,
sys_clk_in => CLK_I, sys_clk_in => CLK_I,
sdram_clk => SDRAM_CLK_I, sdram_rst0 => SDRAM_RST0,
sdram_clk_fb => SDRAM_CLK_FB_I, sdram_clk0 => SDRAM_CLK0,
sdram_clk_out => SDRAM_CLK0,
sdram_rst_out => SDRAM_RST0,
-- User interface -- User interface
u_tag => u_tag_in, u_tag => u_tag_in,
@@ -218,23 +215,8 @@ begin
u_cmd => u_cmd, u_cmd => u_cmd,
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
-- Phy user interface -- Phy controll interface
phy_in => phy_in, phy_ctrl => phy_ctrl
phy_out => phy_out,
-- SDRAM signals
sd_clk_p => sd_clk_p,
sd_clk_n => sd_clk_n,
sd_cke => sd_cke,
sd_cs_n => sd_cs_n,
sd_cas_n => sd_cas_n,
sd_ras_n => sd_ras_n,
sd_we_n => sd_we_n,
sd_addr => sd_addr,
sd_ba => sd_ba,
sd_dm => sd_dm,
sd_dqs => sd_dqs,
sd_data => sd_data
); );
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+4 -4
View File
@@ -33,7 +33,7 @@ entity sdram_ctrl_frontend_wb is
Generic Generic
( (
BL : natural := 2; BL : natural := 2;
f_sysclk : real := 100.0; F_SYSCLK : real := 100.0;
f_sdrclk : real := 100.0; f_sdrclk : real := 100.0;
fifo_depth : integer := 4 fifo_depth : integer := 4
); );
@@ -203,9 +203,9 @@ begin
Generic map Generic map
( (
BL => BL, BL => BL,
f_sysclk => f_sysclk, F_SYSCLK => F_SYSCLK,
f_sdrclk => f_sdrclk, F_SDRCLK => F_SDRCLK,
fifo_depth => fifo_depth FIFO_DEPTH => FIFO_DEPTH
) )
Port map Port map
( (
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+15 -53
View File
@@ -31,20 +31,18 @@ use work.sdram_types.all;
entity sdram_ctrl_top is entity sdram_ctrl_top is
Generic Generic
( (
BL : natural := 2; BURST_LEN : natural := 2;
f_sysclk : real := 100.0; F_SYSCLK : real := 100.0;
f_sdrclk : real := 100.0; F_SDRCLK : real := 100.0;
fifo_depth : natural := 3 FIFO_DEPTH : natural := 3
); );
Port Port
( (
sys_rst_in : in STD_LOGIC; sys_rst_in : in STD_LOGIC;
sys_clk_in : in STD_LOGIC; sys_clk_in : in STD_LOGIC;
sdram_clk : in STD_LOGIC; sdram_clk0 : in STD_LOGIC;
sdram_clk_fb : in STD_LOGIC; sdram_rst0 : in STD_LOGIC;
sdram_clk_out : out STD_LOGIC;
sdram_rst_out : out STD_LOGIC;
-- User interface -- User interface
u_busy : out STD_LOGIC; u_busy : out STD_LOGIC;
@@ -53,9 +51,8 @@ entity sdram_ctrl_top is
u_addr : in user_addr_t; u_addr : in user_addr_t;
u_tag : in user_tag_t; u_tag : in user_tag_t;
-- Phy user stuff -- Phy interface
phy_in : in phy_in_t; phy_ctrl : out phy_ctrl_t;
phy_out : out phy_out_t;
-- SDRAM signals -- SDRAM signals
sd_clk_p : out STD_LOGIC; sd_clk_p : out STD_LOGIC;
@@ -76,16 +73,12 @@ end sdram_ctrl_top;
architecture rtl of sdram_ctrl_top is architecture rtl of sdram_ctrl_top is
signal sdram_clk0 : std_logic;
signal sdram_rst0 : std_logic;
signal sd_cmd_in : sdr_cmd_t; signal sd_cmd_in : sdr_cmd_t;
signal sd_cmd : sdr_cmd_t; signal sd_cmd : sdr_cmd_t;
signal sd_cmd_we : std_logic; signal sd_cmd_we : std_logic;
signal cke : std_logic; signal cke : std_logic;
signal phy_ctrl : phy_ctrl_t; -- signal phy_ctrl : phy_ctrl_t;
-- SD command FIFO -- SD command FIFO
constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
@@ -107,8 +100,6 @@ architecture rtl of sdram_ctrl_top is
alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
begin begin
sdram_clk_out <= sdram_clk0;
sdram_rst_out <= sdram_rst0;
--------------------------------- ---------------------------------
phy_ctrl.part.cke <= cke; phy_ctrl.part.cke <= cke;
@@ -125,8 +116,8 @@ begin
inst_sdram_ctrl : entity work.sdram_ctrl inst_sdram_ctrl : entity work.sdram_ctrl
Generic map Generic map
( (
f_sysclk => f_sysclk, F_SYSCLK => F_SYSCLK,
BL => BL BURST_LEN => BURST_LEN
) )
Port map Port map
( (
@@ -150,7 +141,7 @@ begin
inst_sd_cmd_fifo: entity work.fifo_async inst_sd_cmd_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => fifo_depth, addr_width => FIFO_DEPTH,
data_width => CMD_FIFO_DATA_WIDTH data_width => CMD_FIFO_DATA_WIDTH
) )
PORT MAP PORT MAP
@@ -172,8 +163,8 @@ begin
inst_sdram_cmd : entity work.sdram_cmd inst_sdram_cmd : entity work.sdram_cmd
Generic map Generic map
( (
f_sdrclk => f_sdrclk, F_SDRCLK => F_SDRCLK,
BL => BL BURST_LEN => BURST_LEN
) )
Port map Port map
( (
@@ -188,35 +179,6 @@ begin
mode_word => sd_mode_fifo_out mode_word => sd_mode_fifo_out
); );
-- DDR phy
inst_sdram_phy : entity work.sdram_phy
Generic map
(
f_sdrclk => f_sdrclk
)
Port map
(
rst => sys_rst_in,
clk => sdram_clk,
clk_fb => sdram_clk_fb,
clk0_out => sdram_clk0,
rst0_out => sdram_rst0,
phy_in => phy_in,
phy_out => phy_out,
phy_ctrl => phy_ctrl,
part_clk_p => sd_clk_p,
part_clk_n => sd_clk_n,
part_addr => sd_addr,
part_ba => sd_ba,
part_dm => sd_dm,
part_dqs => sd_dqs,
part_data => sd_data,
part_cs_n => sd_cs_n,
part_we_n => sd_we_n,
part_cas_n => sd_cas_n,
part_ras_n => sd_ras_n,
part_cke => sd_cke
);
end architecture rtl; end architecture rtl;