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- pulled PHY out of sdram_ctrl_top.vhd

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- sdram_ctrl_frontend64_wb.vhd implements J-Bus interface and exports abstract PHY interface
- ctrl_ddr_wb64 wraps sdram_ctrl_frontend64_wb and adds specific PHY. This is now our new top level file

git-svn-id: http://moon:8086/svn/vhdl/trunk@1190 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 09:05:49 +00:00
parent ce636ef1ec
commit f55028c696
7 changed files with 210 additions and 112 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+5 -5
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@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk : real := 100.0;
BL : natural := 2
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0
);
Port (
rst : in STD_LOGIC;
@@ -55,12 +55,12 @@ end sdram_ctrl;
architecture behaviour of sdram_ctrl is
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BURST_LEN);
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, F_SYSCLK);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, F_SYSCLK);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;