jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[BB-FIFO]

Browse Source 
- now working

git-svn-id: http://moon:8086/svn/vhdl/trunk@1347 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-19 18:26:15 +00:00
parent 58dcfb0ea1
commit f1c3a17fa8
3 changed files with 53 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/misc/bbfifo.vhd
+18 -41
View File
@@ -50,69 +50,46 @@ end bbfifo;
architecture Behavioral of bbfifo is architecture Behavioral of bbfifo is
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0); type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
signal req : unsigned(0 to depth); signal bucket_array : bucket_array_t;
signal rdy : unsigned(1 to depth+1); signal Q : unsigned(0 to depth) := (others => '0');
signal bucket_array : bucket_array_t; signal ce : unsigned(1 to depth+1) := (others => '0');
signal ce_in : unsigned(1 to depth);
signal ce_out : unsigned(1 to depth);
begin begin
req(0) <= we; Q(0) <= we;
rdy(depth+1) <= re; ce(depth+1) <= re;
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0'; ready <= ce(1);
avail <= req(depth); avail <= Q(depth);
bucket_array(0) <= din; bucket_array(0) <= din;
dout <= bucket_array(depth); dout <= bucket_array(depth);
gen_ce: gen_bb:
for i in 1 to depth generate for i in 1 to depth generate
begin proc_ce:
process (rdy, req) process(Q, ce)
begin begin
ce_in(i) <= not req(i) and req(i-1); ce(i) <= not Q(i) or ce(i+1);
end process; end process;
end generate;
gen_rdy: proc_q:
for i in 1 to depth generate process(clk)
begin
process (clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
rdy(i) <= '1'; Q(i) <= '0';
elsif req(i-1) = '1' then elsif ce(i) = '1' then
rdy(i) <= rdy(i+1); Q(i) <= Q(i-1);
end if; end if;
end if; end if;
end process; end process;
end generate;
gen_req: proc_data:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
req(i) <= '0';
elsif rdy(i+1) = '1' then
req(i) <= req(i-1);
end if;
end if;
end process;
end generate;
gen_data:
for i in 1 to depth generate
begin
process (clk) process (clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
bucket_array(i) <= (others => '0'); bucket_array(i) <= (others => '0');
elsif req(i-1) = '1' then elsif ce(i) = '1' then
bucket_array(i) <= bucket_array(i-1); bucket_array(i) <= bucket_array(i-1);
end if; end if;
end if; end if;
lib/misc/sim/tb_bbfifo.wdo
+30 -31
View File
@@ -1,31 +1,30 @@
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_bbfifo/rst add wave -noupdate -format Logic /tb_bbfifo/rst
add wave -noupdate -format Logic /tb_bbfifo/clk add wave -noupdate -format Logic /tb_bbfifo/clk
add wave -noupdate -format Logic /tb_bbfifo/re add wave -noupdate -format Logic /tb_bbfifo/re
add wave -noupdate -format Logic /tb_bbfifo/we add wave -noupdate -format Logic /tb_bbfifo/we
add wave -noupdate -format Logic /tb_bbfifo/ready add wave -noupdate -format Logic /tb_bbfifo/ready
add wave -noupdate -format Logic /tb_bbfifo/avail add wave -noupdate -format Logic /tb_bbfifo/avail
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/inst_bbfifo/bucket_array
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/q
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout_reg
add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out TreeUpdate [SetDefaultTree]
TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {49969 ps} 0}
WaveRestoreCursors {{Cursor 1} {170000 ps} 0} configure wave -namecolwidth 150
configure wave -namecolwidth 150 configure wave -valuecolwidth 100
configure wave -valuecolwidth 100 configure wave -justifyvalue left
configure wave -justifyvalue left configure wave -signalnamewidth 1
configure wave -signalnamewidth 1 configure wave -snapdistance 10
configure wave -snapdistance 10 configure wave -datasetprefix 0
configure wave -datasetprefix 0 configure wave -rowmargin 4
configure wave -rowmargin 4 configure wave -childrowmargin 2
configure wave -childrowmargin 2 configure wave -gridoffset 0
configure wave -gridoffset 0 configure wave -gridperiod 1
configure wave -gridperiod 1 configure wave -griddelta 40
configure wave -griddelta 40 configure wave -timeline 0
configure wave -timeline 0 update
update WaveRestoreZoom {0 ps} {1050 ns}
WaveRestoreZoom {76738 ps} {299465 ps}
lib/misc/tb_bbfifo.vhd
+5 -1
View File
@@ -75,7 +75,7 @@ RE_GEN: process
begin begin
wait for 2*CLK_PERIOD; wait for 2*CLK_PERIOD;
wait until rising_edge(clk) and avail = '1'; wait until rising_edge(clk) and avail = '1';
re <= '0'; re <= '1';
dout_reg <= dout; dout_reg <= dout;
wait until rising_edge(clk); wait until rising_edge(clk);
re <= '0'; re <= '0';
@@ -127,6 +127,10 @@ STIMULUS: process
we <= '1'; we <= '1';
din <= din + 1; din <= din + 1;
wait until rising_edge(clk) and ready = '1'; wait until rising_edge(clk) and ready = '1';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
we <= '0';
wait; wait;