jens
f1c3a17fa8
- now working git-svn-id: http://moon:8086/svn/vhdl/trunk@1347 cc03376c-175c-47c8-b038-4cd826a8556b
101 lines
2.7 KiB
VHDL
101 lines
2.7 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Dual-ported register file with asynchrous read
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008/10/20 19:26:01 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity bbfifo is
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Generic
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(
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depth : integer := 2;
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data_width : integer := 8
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);
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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re : in STD_LOGIC;
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we : in STD_LOGIC;
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ready : out STD_LOGIC;
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avail : out STD_LOGIC;
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din : in unsigned(data_width-1 downto 0);
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dout : out unsigned(data_width-1 downto 0)
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);
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end bbfifo;
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architecture Behavioral of bbfifo is
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type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
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signal bucket_array : bucket_array_t;
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signal Q : unsigned(0 to depth) := (others => '0');
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signal ce : unsigned(1 to depth+1) := (others => '0');
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begin
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Q(0) <= we;
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ce(depth+1) <= re;
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ready <= ce(1);
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avail <= Q(depth);
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bucket_array(0) <= din;
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dout <= bucket_array(depth);
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gen_bb:
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for i in 1 to depth generate
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proc_ce:
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process(Q, ce)
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begin
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ce(i) <= not Q(i) or ce(i+1);
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end process;
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proc_q:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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Q(i) <= '0';
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elsif ce(i) = '1' then
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Q(i) <= Q(i-1);
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end if;
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end if;
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end process;
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proc_data:
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process (clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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bucket_array(i) <= (others => '0');
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elsif ce(i) = '1' then
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bucket_array(i) <= bucket_array(i-1);
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end if;
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end if;
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end process;
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end generate;
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end Behavioral;
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