[BB-FIFO]
- now working git-svn-id: http://moon:8086/svn/vhdl/trunk@1347 cc03376c-175c-47c8-b038-4cd826a8556b
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+18
-41
@@ -50,69 +50,46 @@ end bbfifo;
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architecture Behavioral of bbfifo is
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architecture Behavioral of bbfifo is
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type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
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type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
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signal req : unsigned(0 to depth);
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signal bucket_array : bucket_array_t;
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signal rdy : unsigned(1 to depth+1);
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signal Q : unsigned(0 to depth) := (others => '0');
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signal bucket_array : bucket_array_t;
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signal ce : unsigned(1 to depth+1) := (others => '0');
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signal ce_in : unsigned(1 to depth);
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signal ce_out : unsigned(1 to depth);
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begin
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begin
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req(0) <= we;
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Q(0) <= we;
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rdy(depth+1) <= re;
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ce(depth+1) <= re;
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ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
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ready <= ce(1);
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avail <= req(depth);
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avail <= Q(depth);
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bucket_array(0) <= din;
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bucket_array(0) <= din;
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dout <= bucket_array(depth);
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dout <= bucket_array(depth);
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gen_ce:
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gen_bb:
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for i in 1 to depth generate
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for i in 1 to depth generate
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begin
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proc_ce:
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process (rdy, req)
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process(Q, ce)
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begin
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begin
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ce_in(i) <= not req(i) and req(i-1);
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ce(i) <= not Q(i) or ce(i+1);
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end process;
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end process;
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end generate;
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gen_rdy:
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proc_q:
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for i in 1 to depth generate
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process(clk)
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begin
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process (clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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rdy(i) <= '1';
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Q(i) <= '0';
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elsif req(i-1) = '1' then
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elsif ce(i) = '1' then
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rdy(i) <= rdy(i+1);
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Q(i) <= Q(i-1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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gen_req:
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proc_data:
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for i in 1 to depth generate
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begin
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process (clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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req(i) <= '0';
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elsif rdy(i+1) = '1' then
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req(i) <= req(i-1);
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end if;
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end if;
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end process;
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end generate;
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gen_data:
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for i in 1 to depth generate
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begin
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process (clk)
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process (clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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bucket_array(i) <= (others => '0');
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bucket_array(i) <= (others => '0');
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elsif req(i-1) = '1' then
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elsif ce(i) = '1' then
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bucket_array(i) <= bucket_array(i-1);
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bucket_array(i) <= bucket_array(i-1);
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end if;
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end if;
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end if;
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end if;
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@@ -8,13 +8,12 @@ add wave -noupdate -format Logic /tb_bbfifo/ready
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add wave -noupdate -format Logic /tb_bbfifo/avail
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add wave -noupdate -format Logic /tb_bbfifo/avail
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/inst_bbfifo/bucket_array
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/q
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout_reg
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add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
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WaveRestoreCursors {{Cursor 1} {49969 ps} 0}
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configure wave -namecolwidth 150
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -justifyvalue left
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@@ -28,4 +27,4 @@ configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timeline 0
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update
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update
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WaveRestoreZoom {76738 ps} {299465 ps}
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WaveRestoreZoom {0 ps} {1050 ns}
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@@ -75,7 +75,7 @@ RE_GEN: process
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begin
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begin
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wait for 2*CLK_PERIOD;
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wait for 2*CLK_PERIOD;
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wait until rising_edge(clk) and avail = '1';
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wait until rising_edge(clk) and avail = '1';
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re <= '0';
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re <= '1';
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dout_reg <= dout;
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dout_reg <= dout;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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re <= '0';
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re <= '0';
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@@ -127,6 +127,10 @@ STIMULUS: process
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we <= '1';
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we <= '1';
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din <= din + 1;
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din <= din + 1;
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wait until rising_edge(clk) and ready = '1';
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wait until rising_edge(clk) and ready = '1';
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we <= '1';
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din <= din + 1;
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wait until rising_edge(clk) and ready = '1';
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we <= '0';
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wait;
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wait;
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