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[BB-FIFO]

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- now working

git-svn-id: http://moon:8086/svn/vhdl/trunk@1347 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2016-12-19 18:26:15 +00:00
parent 58dcfb0ea1
commit f1c3a17fa8
3 changed files with 53 additions and 73 deletions
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lib/misc/bbfifo.vhd
+18 -41
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@@ -50,69 +50,46 @@ end bbfifo;
architecture Behavioral of bbfifo is
type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
signal req : unsigned(0 to depth);
signal rdy : unsigned(1 to depth+1);
signal bucket_array : bucket_array_t;
signal ce_in : unsigned(1 to depth);
signal ce_out : unsigned(1 to depth);
signal bucket_array : bucket_array_t;
signal Q : unsigned(0 to depth) := (others => '0');
signal ce : unsigned(1 to depth+1) := (others => '0');
begin
req(0) <= we;
rdy(depth+1) <= re;
ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
avail <= req(depth);
Q(0) <= we;
ce(depth+1) <= re;
ready <= ce(1);
avail <= Q(depth);
bucket_array(0) <= din;
dout <= bucket_array(depth);
gen_ce:
gen_bb:
for i in 1 to depth generate
begin
process (rdy, req)
proc_ce:
process(Q, ce)
begin
ce_in(i) <= not req(i) and req(i-1);
ce(i) <= not Q(i) or ce(i+1);
end process;
end generate;
gen_rdy:
for i in 1 to depth generate
begin
process (clk)
proc_q:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
rdy(i) <= '1';
elsif req(i-1) = '1' then
rdy(i) <= rdy(i+1);
Q(i) <= '0';
elsif ce(i) = '1' then
Q(i) <= Q(i-1);
end if;
end if;
end process;
end generate;
gen_req:
for i in 1 to depth generate
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
req(i) <= '0';
elsif rdy(i+1) = '1' then
req(i) <= req(i-1);
end if;
end if;
end process;
end generate;
gen_data:
for i in 1 to depth generate
begin
proc_data:
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
bucket_array(i) <= (others => '0');
elsif req(i-1) = '1' then
elsif ce(i) = '1' then
bucket_array(i) <= bucket_array(i-1);
end if;
end if;