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- improved TB

git-svn-id: http://moon:8086/svn/vhdl/trunk@1369 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-01-15 12:14:40 +00:00
parent 76c81bff41
commit ee807ecdc8
3 changed files with 37 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/misc/sim/tb_bbfifo.fdo
+1 -1
View File
@@ -11,4 +11,4 @@ do {tb_bbfifo.wdo}
view wave
view structure
view signals
run 500 ns
run 1000 ns
lib/misc/sim/tb_bbfifo.wdo
+2 -2
View File
@@ -16,7 +16,7 @@ add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/q
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/inst_bbfifo/bucket_array
add wave -noupdate -format Literal -radix unsigned /tb_bbfifo/inst_bbfifo/fill
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {77874 ps} 0}
WaveRestoreCursors {{Cursor 1} {494499 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -30,4 +30,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {525 ns}
WaveRestoreZoom {0 ps} {1050 ns}
lib/misc/tb_bbfifo.vhd
+34 -2
View File
@@ -76,13 +76,20 @@ CLK_GEN: process
RE_GEN: process
begin
wait for 2*CLK_PERIOD;
wait until rising_edge(clk) and dout_vld = '1';
wait until rising_edge(clk);
re <= '1';
dout_reg <= dout;
wait until rising_edge(clk);
re <= '0';
end process;
PROC_DOUT_REG: process
begin
wait until rising_edge(clk);
if re = '1' and dout_vld = '1' then
dout_reg <= dout;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
@@ -133,7 +140,32 @@ STIMULUS: process
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '0';
wait for 30*CLK_PERIOD;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and full = '0';
we <= '0';
wait;