diff --git a/lib/misc/sim/tb_bbfifo.fdo b/lib/misc/sim/tb_bbfifo.fdo
index 8ec6244..2803994 100644
--- a/lib/misc/sim/tb_bbfifo.fdo
+++ b/lib/misc/sim/tb_bbfifo.fdo
@@ -11,4 +11,4 @@ do {tb_bbfifo.wdo}
 view wave
 view structure
 view signals
-run 500 ns
+run 1000 ns
diff --git a/lib/misc/sim/tb_bbfifo.wdo b/lib/misc/sim/tb_bbfifo.wdo
index bd422d9..ea03f2c 100644
--- a/lib/misc/sim/tb_bbfifo.wdo
+++ b/lib/misc/sim/tb_bbfifo.wdo
@@ -16,7 +16,7 @@ add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/q
 add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/inst_bbfifo/bucket_array
 add wave -noupdate -format Literal -radix unsigned /tb_bbfifo/inst_bbfifo/fill
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {77874 ps} 0}
+WaveRestoreCursors {{Cursor 1} {494499 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -30,4 +30,4 @@ configure wave -gridperiod 1
 configure wave -griddelta 40
 configure wave -timeline 0
 update
-WaveRestoreZoom {0 ps} {525 ns}
+WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/misc/tb_bbfifo.vhd b/lib/misc/tb_bbfifo.vhd
index 2277236..3519a15 100644
--- a/lib/misc/tb_bbfifo.vhd
+++ b/lib/misc/tb_bbfifo.vhd
@@ -76,13 +76,20 @@ CLK_GEN: process
 RE_GEN: process
 	begin
 		wait for 2*CLK_PERIOD;
-		wait until rising_edge(clk) and dout_vld = '1';
+		wait until rising_edge(clk);
 		re <= '1';
-		dout_reg <= dout;
 		wait until rising_edge(clk);
 		re <= '0';
 	end process;
 
+PROC_DOUT_REG: process
+	begin
+		wait until rising_edge(clk);
+		if re = '1' and dout_vld = '1' then
+			dout_reg <= dout;
+		end if;
+	end process;
+
 ------------------------------------------------------------------------------------------
 
 STIMULUS: process
@@ -133,7 +140,32 @@ STIMULUS: process
 		din <= din + 1;
 		wait until rising_edge(clk) and full = '0';
 		we <= '0';
+
+		wait for 30*CLK_PERIOD;
+		wait until rising_edge(clk) and full = '0';
 		
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and full = '0';
+		we <= '0';
 
 		wait;