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- synced ifg_rdy to sys_clk

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git-svn-id: http://moon:8086/svn/vhdl/trunk@847 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-30 10:02:39 +00:00
parent d7c023950b
commit ed9601c6aa
1 changed files with 53 additions and 39 deletions
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lib/emac/src/emac_tx.vhd
+52 -38
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@@ -64,9 +64,10 @@ ARCHITECTURE behavior OF emac_tx IS
signal alloc_OK : std_logic; signal alloc_OK : std_logic;
signal alloc_req : std_logic; signal alloc_req : std_logic;
signal alloc_ack : std_logic; signal alloc_ack : std_logic;
signal alloc_size : word_ptr_t;
signal alloc_remain : unsigned(1 downto 0);
signal nwords_free : word_ptr_t; signal nwords_free : word_ptr_t;
signal alloc_size : word_ptr_t;
signal mem_alloc_en : std_logic; signal mem_alloc_en : std_logic;
signal mem_free_en : std_logic; signal mem_free_en : std_logic;
@@ -92,7 +93,6 @@ ARCHITECTURE behavior OF emac_tx IS
signal ram_din_a : unsigned(31 downto 0); signal ram_din_a : unsigned(31 downto 0);
signal ram_dout_a : unsigned(31 downto 0); signal ram_dout_a : unsigned(31 downto 0);
signal ram_en_b : std_logic; signal ram_en_b : std_logic;
signal ram_we_b : std_logic;
signal ram_addr_b : word_ptr_t; signal ram_addr_b : word_ptr_t;
signal ram_din_b : unsigned(31 downto 0); signal ram_din_b : unsigned(31 downto 0);
signal ram_dout_b : unsigned(31 downto 0); signal ram_dout_b : unsigned(31 downto 0);
@@ -108,14 +108,16 @@ ARCHITECTURE behavior OF emac_tx IS
signal reset_pipe : unsigned(31 downto 0); signal reset_pipe : unsigned(31 downto 0);
subtype inter_frame_gap_cnt_t is natural range 0 to 95; subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t; -- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
signal inter_frame_gap_rdy : std_logic; signal ifg_cnt : ifg_cnt_t;
signal ifg_rdy : std_logic;
signal ifg_idle : std_logic;
type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit); type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free); type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free, xfer_wait);
signal xfer_s, xfer_sn : xfer_state_t; signal xfer_s, xfer_sn : xfer_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0); type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
@@ -151,8 +153,7 @@ begin
cmd_fifo_we <= commit_en; cmd_fifo_we <= commit_en;
cmd_fifo_re <= uncommit_en; cmd_fifo_re <= uncommit_en;
cmd_fifo_din <= fill_remain & "01" & resize(fill_size, 16) & resize(fill_base, 16); cmd_fifo_din <= fill_remain & "01" & resize(fill_size, 16) & resize(fill_base, 16);
ram_en_b <= not mii_fifo_full or uncommit_en; ram_en_b <= not mii_fifo_full;
ram_we_b <= '0';
ram_addr_b <= xfer_ptr; ram_addr_b <= xfer_ptr;
xfer_tag <= cmd_fifo_dout(35 downto 32); xfer_tag <= cmd_fifo_dout(35 downto 32);
@@ -208,10 +209,11 @@ host_state:
end if; end if;
when host_alloc => when host_alloc =>
alloc_ack <= '1';
host_sn <= host_idle;
if alloc_OK = '1' then if alloc_OK = '1' then
host_sn <= host_setup; host_sn <= host_setup;
else
host_sn <= host_idle;
alloc_ack <= '1';
end if; end if;
when host_setup => when host_setup =>
@@ -220,6 +222,7 @@ host_state:
fill_ptr_set <= '1'; fill_ptr_set <= '1';
when host_arm => when host_arm =>
alloc_ack <= '1';
fill_cnt_adv <= '1'; fill_cnt_adv <= '1';
host_sn <= host_fill; host_sn <= host_fill;
@@ -254,16 +257,17 @@ alloc_request_logic:
alloc_req <= '0'; alloc_req <= '0';
elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
alloc_req <= '1'; alloc_req <= '1';
fill_remain <= ctrl_in.tx_size(1 downto 0); alloc_remain <= ctrl_in.tx_size(1 downto 0);
fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2); alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
if ctrl_in.tx_size(1 downto 0) /= "00" then if ctrl_in.tx_size(1 downto 0) /= "00" then
fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1; alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
end if; end if;
ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16); ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
elsif alloc_ack = '1' then elsif alloc_ack = '1' then
alloc_req <= '0'; alloc_req <= '0';
if alloc_OK = '1' then if alloc_OK = '1' then
alloc_size <= fill_size; fill_size <= alloc_size;
fill_remain <= alloc_remain;
end if; end if;
end if; end if;
end if; end if;
@@ -274,7 +278,7 @@ host_alloc_armed_register:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if reset_en = '1' or ctrl_in.pkt_commit_en = '1' or ctrl_in.pkt_alloc_en = '1' then if reset_en = '1' or commit_en = '1' then
ctrl_out.pkt_armed <= '0'; ctrl_out.pkt_armed <= '0';
elsif alloc_ack = '1' then elsif alloc_ack = '1' then
ctrl_out.pkt_armed <= alloc_OK; ctrl_out.pkt_armed <= alloc_OK;
@@ -288,7 +292,7 @@ alloc_eval_logic:
begin begin
if rising_edge(clk) then if rising_edge(clk) then
alloc_OK <= '0'; alloc_OK <= '0';
if fill_size < nwords_free then if alloc_size < nwords_free then
alloc_OK <= '1'; alloc_OK <= '1';
end if; end if;
end if; end if;
@@ -315,7 +319,7 @@ nwords_free_counter:
if reset_en = '1' then if reset_en = '1' then
nwords_free <= (others => '1'); nwords_free <= (others => '1');
elsif mem_alloc_en = '1' then elsif mem_alloc_en = '1' then
nwords_free <= nwords_free - alloc_size; nwords_free <= nwords_free - fill_size;
elsif mem_free_en = '1' then elsif mem_free_en = '1' then
nwords_free <= nwords_free + xfer_size; nwords_free <= nwords_free + xfer_size;
end if; end if;
@@ -331,7 +335,7 @@ fill_counter:
if rising_edge(clk) then if rising_edge(clk) then
if fill_cnt_set = '1' then if fill_cnt_set = '1' then
fill_rdy <= '0'; fill_rdy <= '0';
fill_cnt <= alloc_size; fill_cnt <= fill_size;
elsif fill_cnt_adv = '1' then elsif fill_cnt_adv = '1' then
if fill_cnt /= 0 then if fill_cnt /= 0 then
fill_cnt <= fill_cnt - 1; fill_cnt <= fill_cnt - 1;
@@ -370,7 +374,7 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, inter_frame_gap_rdy, mem_alloc_en, mii_fifo_full) process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, ifg_rdy, mem_alloc_en, mii_fifo_full)
begin begin
xfer_cnt_set <= '0'; xfer_cnt_set <= '0';
@@ -391,21 +395,24 @@ xfer_state:
when xfer_idle => when xfer_idle =>
if cmd_fifo_empty = '0' then if cmd_fifo_empty = '0' then
xfer_ptr_set <= '1';
xfer_cnt_set <= '1';
xfer_sn <= xfer_wait;
end if;
when xfer_wait =>
if inter_frame_gap_rdy = '1' then
xfer_sn <= xfer_setup; xfer_sn <= xfer_setup;
xfer_cnt_adv <= '1';
end if; end if;
when xfer_setup => when xfer_setup =>
xfer_ptr_set <= '1';
xfer_cnt_set <= '1';
xfer_sn <= xfer_arm;
when xfer_arm =>
xfer_cnt_adv <= '1'; xfer_cnt_adv <= '1';
xfer_ptr_adv <= '1'; xfer_sn <= xfer_wait;
xfer_sn <= xfer_active;
when xfer_wait =>
if ifg_rdy = '1' then
xfer_sn <= xfer_active;
xfer_cnt_adv <= '1';
xfer_ptr_adv <= '1';
end if;
when xfer_active => when xfer_active =>
mii_fifo_we <= '1'; mii_fifo_we <= '1';
@@ -428,7 +435,7 @@ xfer_state:
end if; end if;
when xfer_free => when xfer_free =>
if inter_frame_gap_rdy = '0' then if ifg_rdy = '0' then
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
end if; end if;
@@ -438,20 +445,27 @@ xfer_state:
end process; end process;
------------------------------------------------------------------
interframe_gap_ready:
process(clk)
begin
if rising_edge(clk) then
ifg_rdy <= ifg_idle;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
interframe_gap_counter: interframe_gap_counter:
process(mii_tx_clk) process(mii_tx_clk)
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
if reset_en = '1' then ifg_idle <= '0';
inter_frame_gap_rdy <= '1'; if reset_en = '1' or tx_en = '1' then
elsif tx_en = '1' then ifg_cnt <= ifg_cnt_t'high;
inter_frame_gap_rdy <= '0'; elsif ifg_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high; ifg_cnt <= ifg_cnt - 1;
elsif inter_frame_gap_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
else else
inter_frame_gap_rdy <= '1'; ifg_idle <= '1';
end if; end if;
end if; end if;
end process; end process;