From ed9601c6aabb304e13995342a25b88a028c74fbb Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Mar 2010 10:02:39 +0000 Subject: [PATCH] - synced ifg_rdy to sys_clk Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@847 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/emac_tx.vhd | 92 +++++++++++++++++++++++----------------- 1 file changed, 53 insertions(+), 39 deletions(-) diff --git a/lib/emac/src/emac_tx.vhd b/lib/emac/src/emac_tx.vhd index 0ce5314..c8cd4ec 100644 --- a/lib/emac/src/emac_tx.vhd +++ b/lib/emac/src/emac_tx.vhd @@ -64,9 +64,10 @@ ARCHITECTURE behavior OF emac_tx IS signal alloc_OK : std_logic; signal alloc_req : std_logic; signal alloc_ack : std_logic; + signal alloc_size : word_ptr_t; + signal alloc_remain : unsigned(1 downto 0); signal nwords_free : word_ptr_t; - signal alloc_size : word_ptr_t; signal mem_alloc_en : std_logic; signal mem_free_en : std_logic; @@ -92,7 +93,6 @@ ARCHITECTURE behavior OF emac_tx IS signal ram_din_a : unsigned(31 downto 0); signal ram_dout_a : unsigned(31 downto 0); signal ram_en_b : std_logic; - signal ram_we_b : std_logic; signal ram_addr_b : word_ptr_t; signal ram_din_b : unsigned(31 downto 0); signal ram_dout_b : unsigned(31 downto 0); @@ -108,14 +108,16 @@ ARCHITECTURE behavior OF emac_tx IS signal reset_pipe : unsigned(31 downto 0); - subtype inter_frame_gap_cnt_t is natural range 0 to 95; - signal inter_frame_gap_cnt : inter_frame_gap_cnt_t; - signal inter_frame_gap_rdy : std_logic; + subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps +-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps + signal ifg_cnt : ifg_cnt_t; + signal ifg_rdy : std_logic; + signal ifg_idle : std_logic; type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit); signal host_s, host_sn : host_state_t; - type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free); + type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free, xfer_wait); signal xfer_s, xfer_sn : xfer_state_t; type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0); @@ -151,8 +153,7 @@ begin cmd_fifo_we <= commit_en; cmd_fifo_re <= uncommit_en; cmd_fifo_din <= fill_remain & "01" & resize(fill_size, 16) & resize(fill_base, 16); - ram_en_b <= not mii_fifo_full or uncommit_en; - ram_we_b <= '0'; + ram_en_b <= not mii_fifo_full; ram_addr_b <= xfer_ptr; xfer_tag <= cmd_fifo_dout(35 downto 32); @@ -208,10 +209,11 @@ host_state: end if; when host_alloc => - alloc_ack <= '1'; - host_sn <= host_idle; if alloc_OK = '1' then host_sn <= host_setup; + else + host_sn <= host_idle; + alloc_ack <= '1'; end if; when host_setup => @@ -220,6 +222,7 @@ host_state: fill_ptr_set <= '1'; when host_arm => + alloc_ack <= '1'; fill_cnt_adv <= '1'; host_sn <= host_fill; @@ -254,16 +257,17 @@ alloc_request_logic: alloc_req <= '0'; elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then alloc_req <= '1'; - fill_remain <= ctrl_in.tx_size(1 downto 0); - fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2); + alloc_remain <= ctrl_in.tx_size(1 downto 0); + alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2); if ctrl_in.tx_size(1 downto 0) /= "00" then - fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1; + alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1; end if; ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16); elsif alloc_ack = '1' then alloc_req <= '0'; if alloc_OK = '1' then - alloc_size <= fill_size; + fill_size <= alloc_size; + fill_remain <= alloc_remain; end if; end if; end if; @@ -274,7 +278,7 @@ host_alloc_armed_register: process(clk) begin if rising_edge(clk) then - if reset_en = '1' or ctrl_in.pkt_commit_en = '1' or ctrl_in.pkt_alloc_en = '1' then + if reset_en = '1' or commit_en = '1' then ctrl_out.pkt_armed <= '0'; elsif alloc_ack = '1' then ctrl_out.pkt_armed <= alloc_OK; @@ -288,7 +292,7 @@ alloc_eval_logic: begin if rising_edge(clk) then alloc_OK <= '0'; - if fill_size < nwords_free then + if alloc_size < nwords_free then alloc_OK <= '1'; end if; end if; @@ -315,7 +319,7 @@ nwords_free_counter: if reset_en = '1' then nwords_free <= (others => '1'); elsif mem_alloc_en = '1' then - nwords_free <= nwords_free - alloc_size; + nwords_free <= nwords_free - fill_size; elsif mem_free_en = '1' then nwords_free <= nwords_free + xfer_size; end if; @@ -331,7 +335,7 @@ fill_counter: if rising_edge(clk) then if fill_cnt_set = '1' then fill_rdy <= '0'; - fill_cnt <= alloc_size; + fill_cnt <= fill_size; elsif fill_cnt_adv = '1' then if fill_cnt /= 0 then fill_cnt <= fill_cnt - 1; @@ -370,7 +374,7 @@ xfer_state_next: end process; xfer_state: - process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, inter_frame_gap_rdy, mem_alloc_en, mii_fifo_full) + process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, ifg_rdy, mem_alloc_en, mii_fifo_full) begin xfer_cnt_set <= '0'; @@ -391,22 +395,25 @@ xfer_state: when xfer_idle => if cmd_fifo_empty = '0' then - xfer_ptr_set <= '1'; - xfer_cnt_set <= '1'; - xfer_sn <= xfer_wait; + xfer_sn <= xfer_setup; end if; + when xfer_setup => + xfer_ptr_set <= '1'; + xfer_cnt_set <= '1'; + xfer_sn <= xfer_arm; + + when xfer_arm => + xfer_cnt_adv <= '1'; + xfer_sn <= xfer_wait; + when xfer_wait => - if inter_frame_gap_rdy = '1' then - xfer_sn <= xfer_setup; - xfer_cnt_adv <= '1'; + if ifg_rdy = '1' then + xfer_sn <= xfer_active; + xfer_cnt_adv <= '1'; + xfer_ptr_adv <= '1'; end if; - when xfer_setup => - xfer_cnt_adv <= '1'; - xfer_ptr_adv <= '1'; - xfer_sn <= xfer_active; - when xfer_active => mii_fifo_we <= '1'; xfer_cnt_adv <= not mii_fifo_full; @@ -428,7 +435,7 @@ xfer_state: end if; when xfer_free => - if inter_frame_gap_rdy = '0' then + if ifg_rdy = '0' then xfer_sn <= xfer_idle; end if; @@ -438,20 +445,27 @@ xfer_state: end process; +------------------------------------------------------------------ +interframe_gap_ready: + process(clk) + begin + if rising_edge(clk) then + ifg_rdy <= ifg_idle; + end if; + end process; + ------------------------------------------------------------------ interframe_gap_counter: process(mii_tx_clk) begin if rising_edge(mii_tx_clk) then - if reset_en = '1' then - inter_frame_gap_rdy <= '1'; - elsif tx_en = '1' then - inter_frame_gap_rdy <= '0'; - inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high; - elsif inter_frame_gap_cnt /= 0 then - inter_frame_gap_cnt <= inter_frame_gap_cnt - 1; + ifg_idle <= '0'; + if reset_en = '1' or tx_en = '1' then + ifg_cnt <= ifg_cnt_t'high; + elsif ifg_cnt /= 0 then + ifg_cnt <= ifg_cnt - 1; else - inter_frame_gap_rdy <= '1'; + ifg_idle <= '1'; end if; end if; end process;