jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- Switched to 64-Bit SDRAM- and VGA-controller

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@110 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-25 11:48:04 +00:00
parent 7cdfa6929d
commit ed47f478f8
2 changed files with 47 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys.vhd
+23 -17
View File
@@ -260,7 +260,7 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT vga_frontend
COMPONENT vga_frontend64
GENERIC
(
sys_freq : integer;
@@ -279,13 +279,13 @@ ARCHITECTURE behavior OF mips_sys IS
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
SEL_O : out unsigned(7 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(31 downto 0);
MDAT_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(63 downto 0);
MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
@@ -353,14 +353,15 @@ ARCHITECTURE behavior OF mips_sys IS
-- VGA Master
signal MRDY_O_vga : std_logic;
signal MDAT_O_vga : word_t;
signal ADDR_O_vga : word_t;
signal SEL_O_vga : unsigned(3 downto 0);
signal SEL_O_vga : unsigned(7 downto 0);
signal WE_O_vga : std_logic;
signal CYC_O_vga : std_logic;
signal STB_O_vga : std_logic;
signal SRDY_I_vga : std_logic;
signal ACK_I_vga : std_logic;
signal MDAT_I_vga : unsigned(63 downto 0);
signal MDAT_O_vga : unsigned(63 downto 0);
-- Slaves
signal CYC_I_flash : std_logic;
@@ -376,7 +377,9 @@ ARCHITECTURE behavior OF mips_sys IS
signal CYC_I_sdram : std_logic;
signal ACK_O_sdram : std_logic;
signal SRDY_O_sdram : std_logic;
signal SDAT_O_sdram : unsigned(31 downto 0);
signal SDAT_O_sdram : unsigned(63 downto 0);
signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_ram : std_logic;
signal ACK_O_ram : std_logic;
@@ -435,13 +438,15 @@ BEGIN
usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
---------------------------------------------------------------
-- Arbiter
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
@@ -453,6 +458,7 @@ BEGIN
arb_req(0) <= CYC_O_cpu;
arb_req(1) <= CYC_O_vga;
MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I;
arbiter_proc:
process(clk)
@@ -559,7 +565,7 @@ signal_mux:
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
MDAT_I <= SDAT_O_sdram when CYC_I_sdram = '1' else
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
@@ -734,12 +740,12 @@ inst_uart_wb : uart_wb
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => ddr_frequency_hz,
fifo_depth => 6
fifo_depth => 5
)
PORT MAP
(
@@ -750,13 +756,13 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
CYC_I => CYC_I_sdram,
STB_I => STB_O,
SEL_I => SEL_O,
SEL_I => SEL_I_sdram,
WE_I => WE_O,
ACK_O => ACK_O_sdram,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_sdram,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_I => SDAT_I_sdram,
DAT_O => SDAT_O_sdram,
-- SDRAM signals
@@ -795,7 +801,7 @@ inst_clockgen : entity work.clockgen
error_out => open
);
inst_vga_frontend : vga_frontend
inst_vga_frontend : vga_frontend64
GENERIC MAP
(
sys_freq => 100E6,
@@ -819,7 +825,7 @@ inst_vga_frontend : vga_frontend
SRDY_I => SRDY_I_vga,
MRDY_O => MRDY_O_vga,
ADDR_O => ADDR_O_vga,
MDAT_I => MDAT_I,
MDAT_I => MDAT_I_vga,
MDAT_O => MDAT_O_vga,
-- JBUS Slave signals