diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index bd9826f..0ef2cc9 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -260,7 +260,7 @@ ARCHITECTURE behavior OF mips_sys IS ); END COMPONENT; - COMPONENT vga_frontend + COMPONENT vga_frontend64 GENERIC ( sys_freq : integer; @@ -279,13 +279,13 @@ ARCHITECTURE behavior OF mips_sys IS CYC_O : out STD_LOGIC; STB_O : out STD_LOGIC; WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); + SEL_O : out unsigned(7 downto 0); ACK_I : in STD_LOGIC; SRDY_I : in STD_LOGIC; MRDY_O : out STD_LOGIC; ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(31 downto 0); - MDAT_O : out unsigned(31 downto 0); + MDAT_I : in unsigned(63 downto 0); + MDAT_O : out unsigned(63 downto 0); -- JBUS Slave signals CYC_I : in STD_LOGIC; @@ -353,14 +353,15 @@ ARCHITECTURE behavior OF mips_sys IS -- VGA Master signal MRDY_O_vga : std_logic; - signal MDAT_O_vga : word_t; signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(3 downto 0); + signal SEL_O_vga : unsigned(7 downto 0); signal WE_O_vga : std_logic; signal CYC_O_vga : std_logic; signal STB_O_vga : std_logic; signal SRDY_I_vga : std_logic; signal ACK_I_vga : std_logic; + signal MDAT_I_vga : unsigned(63 downto 0); + signal MDAT_O_vga : unsigned(63 downto 0); -- Slaves signal CYC_I_flash : std_logic; @@ -376,7 +377,9 @@ ARCHITECTURE behavior OF mips_sys IS signal CYC_I_sdram : std_logic; signal ACK_O_sdram : std_logic; signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(31 downto 0); + signal SDAT_O_sdram : unsigned(63 downto 0); + signal SDAT_I_sdram : unsigned(63 downto 0); + signal SEL_I_sdram : unsigned(7 downto 0); signal CYC_I_ram : std_logic; signal ACK_O_ram : std_logic; @@ -435,13 +438,15 @@ BEGIN usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2); flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0'; - + SDAT_I_sdram <= MDAT_O & MDAT_O; + SEL_I_sdram <= "0000" & SEL_O; + --------------------------------------------------------------- -- Arbiter MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0'); + MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0'); + SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; @@ -453,6 +458,7 @@ BEGIN arb_req(0) <= CYC_O_cpu; arb_req(1) <= CYC_O_vga; + MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; arbiter_proc: process(clk) @@ -559,7 +565,7 @@ signal_mux: ------------------------------------------------------------------ SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga; ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga; - MDAT_I <= SDAT_O_sdram when CYC_I_sdram = '1' else + MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else SDAT_O_ram when CYC_I_ram = '1' else SDAT_O_rom when CYC_I_rom = '1' else SDAT_O_flash when CYC_I_flash = '1' else @@ -734,12 +740,12 @@ inst_uart_wb : uart_wb ); -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb +inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb GENERIC MAP ( BL => BURST_LEN, f_sysclk => ddr_frequency_hz, - fifo_depth => 6 + fifo_depth => 5 ) PORT MAP ( @@ -750,13 +756,13 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb CYC_I => CYC_I_sdram, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_I_sdram, WE_I => WE_O, ACK_O => ACK_O_sdram, MRDY_I => MRDY_O, SRDY_O => SRDY_O_sdram, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => SDAT_I_sdram, DAT_O => SDAT_O_sdram, -- SDRAM signals @@ -795,7 +801,7 @@ inst_clockgen : entity work.clockgen error_out => open ); -inst_vga_frontend : vga_frontend +inst_vga_frontend : vga_frontend64 GENERIC MAP ( sys_freq => 100E6, @@ -819,7 +825,7 @@ inst_vga_frontend : vga_frontend SRDY_I => SRDY_I_vga, MRDY_O => MRDY_O_vga, ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I, + MDAT_I => MDAT_I_vga, MDAT_O => MDAT_O_vga, -- JBUS Slave signals diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index b03f084..abf5de5 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -304,7 +304,7 @@ ARCHITECTURE behavior OF mips_sys IS ); END COMPONENT; - COMPONENT vga_frontend + COMPONENT vga_frontend64 GENERIC ( sys_freq : integer; @@ -323,13 +323,13 @@ ARCHITECTURE behavior OF mips_sys IS CYC_O : out STD_LOGIC; STB_O : out STD_LOGIC; WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); + SEL_O : out unsigned(7 downto 0); ACK_I : in STD_LOGIC; SRDY_I : in STD_LOGIC; MRDY_O : out STD_LOGIC; ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(31 downto 0); - MDAT_O : out unsigned(31 downto 0); + MDAT_I : in unsigned(63 downto 0); + MDAT_O : out unsigned(63 downto 0); -- JBUS Slave signals CYC_I : in STD_LOGIC; @@ -411,14 +411,15 @@ ARCHITECTURE behavior OF mips_sys IS -- VGA Master signal MRDY_O_vga : std_logic; - signal MDAT_O_vga : word_t; signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(3 downto 0); + signal SEL_O_vga : unsigned(7 downto 0); signal WE_O_vga : std_logic; signal CYC_O_vga : std_logic; signal STB_O_vga : std_logic; signal SRDY_I_vga : std_logic; signal ACK_I_vga : std_logic; + signal MDAT_I_vga : unsigned(63 downto 0); + signal MDAT_O_vga : unsigned(63 downto 0); -- Slaves signal CYC_I_flash : std_logic; @@ -434,7 +435,9 @@ ARCHITECTURE behavior OF mips_sys IS signal CYC_I_sdram : std_logic; signal ACK_O_sdram : std_logic; signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(31 downto 0); + signal SDAT_O_sdram : unsigned(63 downto 0); + signal SDAT_I_sdram : unsigned(63 downto 0); + signal SEL_I_sdram : unsigned(7 downto 0); signal CYC_I_ram : std_logic; signal ACK_O_ram : std_logic; @@ -500,6 +503,9 @@ BEGIN ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0'; ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0'; + SDAT_I_sdram <= MDAT_O & MDAT_O; + SEL_I_sdram <= "0000" & SEL_O; + sys_flash_ssram_out: process(clk) @@ -529,9 +535,9 @@ sys_flash_ssram_out: --------------------------------------------------------------- -- Arbiter MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0'); + MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0'); + SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; @@ -543,6 +549,7 @@ sys_flash_ssram_out: arb_req(0) <= CYC_O_cpu; arb_req(1) <= CYC_O_vga; + MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; arbiter_proc: process(clk) @@ -657,7 +664,7 @@ signal_mux: SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga; ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga; MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else - SDAT_O_sdram when CYC_I_sdram = '1' else + SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else SDAT_O_ram when CYC_I_ram = '1' else SDAT_O_rom when CYC_I_rom = '1' else SDAT_O_flash when CYC_I_flash = '1' else @@ -878,12 +885,12 @@ inst_ssram_port_wb : entity work.ssram_port_wb ssram_bw_n => sys_ssram_bw_n ); -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb +inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb GENERIC MAP ( BL => BURST_LEN, f_sysclk => ddr_frequency_hz, - fifo_depth => 6 + fifo_depth => 5 ) PORT MAP ( @@ -894,13 +901,13 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb CYC_I => CYC_I_sdram, STB_I => STB_O, - SEL_I => SEL_O, + SEL_I => SEL_I_sdram, WE_I => WE_O, ACK_O => ACK_O_sdram, MRDY_I => MRDY_O, SRDY_O => SRDY_O_sdram, ADDR_I => ADDR_O, - DAT_I => MDAT_O, + DAT_I => SDAT_I_sdram, DAT_O => SDAT_O_sdram, -- SDRAM signals @@ -939,14 +946,14 @@ inst_clockgen : entity work.clockgen error_out => open ); -inst_vga_frontend : vga_frontend +inst_vga_frontend : vga_frontend64 GENERIC MAP ( sys_freq => 100E6, fifo_depth => 2048, fifo_almost_full_thresh => 1860, fifo_almost_empty_thresh => 256, - tsvga => ts_vga_800_600_72 + tsvga => ts_vga_testbench ) PORT MAP ( @@ -963,7 +970,7 @@ inst_vga_frontend : vga_frontend SRDY_I => SRDY_I_vga, MRDY_O => MRDY_O_vga, ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I, + MDAT_I => MDAT_I_vga, MDAT_O => MDAT_O_vga, -- JBUS Slave signals