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- added coef_latency

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git-svn-id: http://moon:8086/svn/vhdl/trunk@188 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-02 16:22:28 +00:00
parent a165d37bb7
commit eb818a15bb
1 changed files with 10 additions and 1 deletions
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lib/filter/src/tb_fir_stage_sys.vhd
+10 -1
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@@ -52,10 +52,12 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS
nbits_out : integer; nbits_out : integer;
nbits_out_frac : integer; nbits_out_frac : integer;
input_latency : integer; input_latency : integer;
coef_latency : integer;
pipe_latency : integer pipe_latency : integer
); );
PORT PORT
( (
rst : in std_logic;
clk : in std_logic; clk : in std_logic;
x_in : in sfixed; x_in : in sfixed;
y_in : in sfixed; y_in : in sfixed;
@@ -72,6 +74,7 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS
constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
--Inputs --Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0'; SIGNAL clk : std_logic := '0';
SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
@@ -115,10 +118,12 @@ BEGIN
nbits_out => nbits_stages, nbits_out => nbits_stages,
nbits_out_frac => nbits_stages_frac, nbits_out_frac => nbits_stages_frac,
input_latency => 1, input_latency => 1,
coef_latency => 1,
pipe_latency => 2 pipe_latency => 2
) )
PORT MAP PORT MAP
( (
rst => rst,
clk => clk, clk => clk,
x_in => x_in, x_in => x_in,
y_in => zero_in, y_in => zero_in,
@@ -138,10 +143,12 @@ BEGIN
nbits_out => nbits_stages, nbits_out => nbits_stages,
nbits_out_frac => nbits_stages_frac, nbits_out_frac => nbits_stages_frac,
input_latency => 2, input_latency => 2,
coef_latency => 1,
pipe_latency => 2 pipe_latency => 2
) )
PORT MAP PORT MAP
( (
rst => rst,
clk => clk, clk => clk,
x_in => x(i-1), x_in => x(i-1),
y_in => y(i-1), y_in => y(i-1),
@@ -160,10 +167,12 @@ BEGIN
nbits_out => nbits_out, nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac, nbits_out_frac => nbits_out_frac,
input_latency => 2, input_latency => 2,
coef_latency => 1,
pipe_latency => 2 pipe_latency => 2
) )
PORT MAP PORT MAP
( (
rst => rst,
clk => clk, clk => clk,
x_in => x(ntaps-2), x_in => x(ntaps-2),
y_in => y(ntaps-2), y_in => y(ntaps-2),
@@ -187,7 +196,7 @@ BEGIN
-- Wait 100 ns for global reset to finish -- Wait 100 ns for global reset to finish
wait for 4*PERIOD; wait for 4*PERIOD;
rst <= '0';
x_in <= to_sfixed(0.0, x_in); x_in <= to_sfixed(0.0, x_in);
wait for 40*PERIOD; wait for 40*PERIOD;