From eb818a15bbb52dbeed0f7b467ec0be7e1c449ad0 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 2 Jan 2009 16:22:28 +0000 Subject: [PATCH] - added coef_latency git-svn-id: http://moon:8086/svn/vhdl/trunk@188 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/tb_fir_stage_sys.vhd | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd index bb34477..f0109ca 100644 --- a/lib/filter/src/tb_fir_stage_sys.vhd +++ b/lib/filter/src/tb_fir_stage_sys.vhd @@ -52,10 +52,12 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS nbits_out : integer; nbits_out_frac : integer; input_latency : integer; + coef_latency : integer; pipe_latency : integer ); PORT ( + rst : in std_logic; clk : in std_logic; x_in : in sfixed; y_in : in sfixed; @@ -72,6 +74,7 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); --Inputs + SIGNAL rst : std_logic := '1'; SIGNAL clk : std_logic := '0'; SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); @@ -115,10 +118,12 @@ BEGIN nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, input_latency => 1, + coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, x_in => x_in, y_in => zero_in, @@ -138,10 +143,12 @@ BEGIN nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, input_latency => 2, + coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, x_in => x(i-1), y_in => y(i-1), @@ -160,10 +167,12 @@ BEGIN nbits_out => nbits_out, nbits_out_frac => nbits_out_frac, input_latency => 2, + coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, x_in => x(ntaps-2), y_in => y(ntaps-2), @@ -187,7 +196,7 @@ BEGIN -- Wait 100 ns for global reset to finish wait for 4*PERIOD; - + rst <= '0'; x_in <= to_sfixed(0.0, x_in); wait for 40*PERIOD;