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- changed reset generator and added BIU-Reset signal

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git-svn-id: http://moon:8086/svn/vhdl/trunk@418 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-03-30 09:05:19 +00:00
parent 1cbfc94fde
commit eb22574d20
1 changed files with 16 additions and 10 deletions
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lib/CPUs/MIPS/src/core/mips_top.vhd
+15 -9
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@@ -103,6 +103,7 @@ architecture rtl of mips_top is
signal dmem_din : word_t; signal dmem_din : word_t;
signal dmem_be : unsigned(3 downto 0); signal dmem_be : unsigned(3 downto 0);
signal biu_rst : STD_LOGIC;
signal cpu_rst : STD_LOGIC; signal cpu_rst : STD_LOGIC;
signal cpu_run : STD_LOGIC; signal cpu_run : STD_LOGIC;
@@ -186,20 +187,25 @@ begin
debug(1) <= dmem_err; debug(1) <= dmem_err;
process(CLK_I) process(CLK_I)
variable reset_delay : unsigned (5 downto 0); variable reset_delay : unsigned (31 downto 0);
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if RST_I = '1' then if RST_I = '1' then
reset_delay := (others => '1'); reset_delay := (others => '0');
biu_rst <= '1';
cpu_rst <= '1'; cpu_rst <= '1';
cpu_run <= '0'; cpu_run <= '0';
elsif reset_delay /= (5 downto 0 => '0') then
reset_delay := reset_delay - 1;
else else
cpu_rst <= '0'; reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1';
end if; if reset_delay(20) = '1' then
if reset_delay(reset_delay'left-1) = '0' then biu_rst <= '0';
cpu_run <= '1'; end if;
if reset_delay(31) = '1' then
cpu_rst <= '0';
end if;
if reset_delay(16) = '1' then
cpu_run <= '1';
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -262,7 +268,7 @@ inst_biu: biu
) )
PORT MAP PORT MAP
( (
RST_I => cpu_rst, RST_I => biu_rst,
CLK_I => CLK_I, CLK_I => CLK_I,
ACK_I => ACK_I, ACK_I => ACK_I,
SRDY_I => SRDY_I, SRDY_I => SRDY_I,