diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd
index 9226a68..268028f 100644
--- a/lib/CPUs/MIPS/src/core/mips_top.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_top.vhd
@@ -103,6 +103,7 @@ architecture rtl of mips_top is
 	signal dmem_din			: word_t;
 	signal dmem_be			: unsigned(3 downto 0);
 
+	signal biu_rst			: STD_LOGIC;
 	signal cpu_rst			: STD_LOGIC;
 	signal cpu_run			: STD_LOGIC;
 
@@ -186,21 +187,26 @@ begin
 	debug(1)		<= dmem_err;
 	
 	process(CLK_I)
-	variable reset_delay : unsigned (5 downto 0);
+	variable reset_delay : unsigned (31 downto 0);
 	begin
 		if rising_edge(CLK_I) then
 			if RST_I = '1' then
-				reset_delay := (others => '1');
+				reset_delay := (others => '0');
+				biu_rst	<= '1';
 				cpu_rst <= '1';
 				cpu_run	<= '0';
-			elsif reset_delay /= (5 downto 0 => '0') then
-				reset_delay := reset_delay - 1;
 			else
-				cpu_rst <= '0';
-			end if;	
-			if reset_delay(reset_delay'left-1) = '0' then
-				cpu_run	<= '1';
-			end if;	
+				reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1';
+				if reset_delay(20) = '1' then
+					biu_rst <= '0';
+				end if;	
+				if reset_delay(31) = '1' then
+					cpu_rst <= '0';
+				end if;	
+				if reset_delay(16) = '1' then
+					cpu_run	<= '1';
+				end if;	
+			end if;
 		end if;
 	end process;
 
@@ -262,7 +268,7 @@ inst_biu: biu
 	)
 	PORT MAP
 	(
-		RST_I			=> cpu_rst,
+		RST_I			=> biu_rst,
 		CLK_I			=> CLK_I,
 		ACK_I			=> ACK_I,
 		SRDY_I			=> SRDY_I,