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git-svn-id: http://moon:8086/svn/vhdl/trunk@1095 cc03376c-175c-47c8-b038-4cd826a8556b
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus II License Agreement,
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-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- Quartus II 15.0.0 Build 145 04/22/2015
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----------------------------------------------------------------------------
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-- ALtera Primitives Component Declaration File
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.VITAL_Timing.all;
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use IEEE.VITAL_Primitives.all;
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package dffeas_pack is
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-- default generic values
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CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
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CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
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CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
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CONSTANT DefSetupHoldCnst : TIME := 0 ns;
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CONSTANT DefPulseWdthCnst : TIME := 0 ns;
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CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
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CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
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CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
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CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
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CONSTANT DefXOnChecks : BOOLEAN := TRUE;
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end dffeas_pack;
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.VITAL_Timing.all;
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use work.dffeas_pack.all;
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package altera_primitives_components is
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component carry
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port (
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a_in : in std_logic;
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a_out : out std_logic );
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end component;
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component cascade
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port (
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a_in : in std_logic;
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a_out : out std_logic );
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end component;
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component global
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port (
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a_in : in std_logic;
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a_out : out std_logic);
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end component;
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component tri
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port(
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a_in : in std_logic;
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oe : in std_logic;
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a_out : out std_logic);
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end component;
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component carry_sum
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port (
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sin : in std_logic;
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cin : in std_logic;
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sout : out std_logic;
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cout : out std_logic );
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end component;
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component exp
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port (
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a_in : in std_logic;
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a_out : out std_logic);
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end component;
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component soft
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port (
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a_in : in std_logic;
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a_out : out std_logic );
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end component;
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component opndrn
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port (
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a_in : in std_logic;
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a_out : out std_logic );
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end component;
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component row_global
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port (
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a_in : in std_logic;
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a_out : out std_logic );
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end component;
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component lut_input
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port(
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a_in : in std_logic;
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a_out : out std_logic);
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end component;
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component lut_output
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port(
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a_in : in std_logic;
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a_out : out std_logic);
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end component;
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component dlatch
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port(
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d : in std_logic;
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ena : in std_logic;
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clrn : in std_logic;
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prn : in std_logic;
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q : out std_logic);
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end component;
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component latch
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port(
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d : in std_logic;
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ena : in std_logic;
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q : out std_logic);
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end component;
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component dff
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port(
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d, clk, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component dffe
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port(
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d, clk, ena, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component dffea
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port(
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d, clk, ena, clrn, prn, aload, adata : in std_logic;
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q : out std_logic);
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end component;
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component dffeas
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generic (
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power_up : string := "DONT_CARE";
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is_wysiwyg : string := "false";
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dont_touch : string := "false";
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x_on_violation : string := "on";
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lpm_type : string := "DFFEAS";
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tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
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tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
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tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
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tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
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tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
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tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
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tipd_clk : VitalDelayType01 := DefPropDelay01;
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tipd_d : VitalDelayType01 := DefPropDelay01;
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tipd_asdata : VitalDelayType01 := DefPropDelay01;
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tipd_sclr : VitalDelayType01 := DefPropDelay01;
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tipd_sload : VitalDelayType01 := DefPropDelay01;
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tipd_clrn : VitalDelayType01 := DefPropDelay01;
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tipd_prn : VitalDelayType01 := DefPropDelay01;
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tipd_aload : VitalDelayType01 := DefPropDelay01;
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tipd_ena : VitalDelayType01 := DefPropDelay01;
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TimingChecksOn: Boolean := True;
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MsgOn: Boolean := DefGlitchMsgOn;
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XOn: Boolean := DefGlitchXOn;
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MsgOnChecks: Boolean := DefMsgOnChecks;
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XOnChecks: Boolean := DefXOnChecks;
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InstancePath: STRING := "*" );
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port (
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d : in std_logic := '0';
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clk : in std_logic := '0';
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ena : in std_logic := '1';
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clrn : in std_logic := '1';
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prn : in std_logic := '1';
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aload : in std_logic := '0';
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asdata : in std_logic := '1';
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sclr : in std_logic := '0';
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sload : in std_logic := '0';
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devclrn : in std_logic := '1';
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devpor : in std_logic := '1';
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q : out std_logic );
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end component;
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component tff
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port(
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t, clk, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component tffe
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port(
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t, clk, ena, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component jkff
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port(
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j, k, clk, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component jkffe
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port(
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j, k, clk, ena, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component srff
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port(
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s, r, clk, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component srffe
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port(
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s, r, clk, ena, clrn, prn : in std_logic;
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q : out std_logic);
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end component;
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component clklock
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generic(
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input_frequency : natural := 10000;
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clockboost : natural := 1);
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port(
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inclk : in std_logic;
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outclk : out std_logic);
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end component;
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component alt_inbuf
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generic(
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io_standard : string := "NONE";
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_inbuf" );
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port(
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i : in std_logic;
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o : out std_logic);
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end component;
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component alt_outbuf
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generic(
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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slow_slew_rate : string := "NONE";
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_outbuf" );
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port(
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i : in std_logic;
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o : out std_logic);
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end component;
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component alt_outbuf_tri
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generic(
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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slow_slew_rate : string := "NONE";
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_outbuf_tri" );
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port(
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i : in std_logic;
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oe : in std_logic;
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o : out std_logic);
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end component;
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component alt_iobuf
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generic(
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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slow_slew_rate : string := "NONE";
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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input_termination : string := "NONE";
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output_termination : string := "NONE";
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lpm_type : string := "alt_iobuf" );
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port(
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i : in std_logic;
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oe : in std_logic;
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io : inout std_logic;
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o : out std_logic);
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end component;
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component alt_inbuf_diff
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generic(
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io_standard : string := "NONE";
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_inbuf_diff" );
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port(
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i : in std_logic;
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ibar : in std_logic;
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o : out std_logic);
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end component;
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component alt_outbuf_diff
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generic (
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_outbuf_diff" );
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port(
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i : in std_logic;
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o : out std_logic;
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obar : out std_logic );
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end component;
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component alt_outbuf_tri_diff
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generic (
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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lpm_type : string := "alt_outbuf_tri_diff" );
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port(
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i : in std_logic;
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oe : in std_logic;
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o : out std_logic;
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obar : out std_logic );
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end component;
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component alt_iobuf_diff
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generic (
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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input_termination : string := "NONE";
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output_termination : string := "NONE";
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lpm_type : string := "alt_iobuf_diff" );
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port(
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i : in std_logic;
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oe : in std_logic;
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io : inout std_logic;
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iobar : inout std_logic;
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o : out std_logic );
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end component;
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component alt_bidir_diff
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generic (
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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input_termination : string := "NONE";
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output_termination : string := "NONE";
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lpm_type : string := "alt_bidir_diff" );
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port(
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oe : in std_logic;
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bidirin : inout std_logic;
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io : inout std_logic;
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iobar : inout std_logic );
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end component;
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component alt_bidir_buf
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generic (
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io_standard : string := "NONE";
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current_strength : string := "NONE";
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current_strength_new : string := "NONE";
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slew_rate : integer := -1;
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location : string := "NONE";
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enable_bus_hold : string := "NONE";
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weak_pull_up_resistor : string := "NONE";
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termination : string := "NONE";
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input_termination : string := "NONE";
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output_termination : string := "NONE";
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lpm_type : string := "alt_bidir_buf" );
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port(
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oe : in std_logic;
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bidirin : inout std_logic;
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io : inout std_logic );
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end component;
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end altera_primitives_components;
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