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- fixed rdy-signal

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git-svn-id: http://moon:8086/svn/vhdl/trunk@200 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-04 15:31:46 +00:00
parent 9a756d4ca8
commit e4dc3e69a1
2 changed files with 21 additions and 13 deletions
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lib/filter/src/fir_semi_parallel.vhd
+16 -10
View File
@@ -113,7 +113,6 @@ begin
y(0) <= to_sfixed(0.0, y(0)); y(0) <= to_sfixed(0.0, y(0));
accu_load <= accu_ld_pipe(accu_ld_pipe'left); accu_load <= accu_ld_pipe(accu_ld_pipe'left);
rdy <= '1';
din_register: din_register:
process(clk) process(clk)
@@ -172,16 +171,21 @@ counter:
ce0 <= '0'; ce0 <= '0';
count0 <= cnt; count0 <= cnt;
if rst = '1' then if rst = '1' then
rdy <= '1';
en <= '0'; en <= '0';
cnt := count_t'high; cnt := count_t'high;
elsif cnt /= count_t'high then elsif cnt /= count_t'high then
cnt := cnt + 1; cnt := cnt + 1;
if cnt = count_t'high-1 then
rdy <= '1';
end if;
else else
en <= '0'; en <= '0';
if din_vld = '1' then if din_vld = '1' then
en <= '1'; en <= '1';
cnt := 0; cnt := 0;
ce0 <= '1'; ce0 <= '1';
rdy <= '0';
end if; end if;
end if; end if;
end if; end if;
@@ -260,15 +264,17 @@ gen_delays:
acumulator: acumulator:
process(clk) process(clk)
begin begin
if rising_edge(clk) and en = '1' then if rising_edge(clk) then
dout_vld <= accu_load; if rst = '1' then
if accu_load = '1' then dout_vld <= '0';
dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); elsif en = '1' then
end if; dout_vld <= accu_load;
if accu_load = '1' then if accu_load = '1' then
accu <= y(nstages); dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
else accu <= y(nstages);
accu <= resize(accu + y(nstages), accu); else
accu <= resize(accu + y(nstages), accu);
end if;
end if; end if;
end if; end if;
end process; end process;
lib/filter/src/tb_fir_semi_parallel.vhd
+5 -3
View File
@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
ENTITY tb_fir_semi_parallel IS ENTITY tb_fir_semi_parallel IS
Generic Generic
( (
ntaps_per_stage : integer := 4; ntaps_per_stage : integer := 32;
nstages : integer := 8; nstages : integer := 2;
nbits_in : integer := 32; nbits_in : integer := 32;
nbits_in_frac : integer := 30; nbits_in_frac : integer := 30;
nbits_stages : integer := 32; nbits_stages : integer := 32;
@@ -170,13 +170,15 @@ BEGIN
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk) and rdy = '1';
din_vld <= '1'; din_vld <= '1';
d_in <= to_sfixed(real(i)*0.01, d_in); d_in <= to_sfixed(real(i)*0.01, d_in);
wait until rising_edge(clk);
din_vld <= '0';
end loop; end loop;
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk) and rdy = '1';
------------------------------------------ ------------------------------------------
din_vld <= '1'; din_vld <= '1';
d_in <= to_sfixed(0.0, d_in); d_in <= to_sfixed(0.0, d_in);
wait for 64*ntaps*PERIOD; wait for 64*ntaps*PERIOD;
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk);
din_vld <= '0'; din_vld <= '0';
wait for 64*ntaps*PERIOD; wait for 64*ntaps*PERIOD;