From e4dc3e69a1e3d01c72012a3b03b72dd7c98583d8 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 4 Jan 2009 15:31:46 +0000
Subject: [PATCH] - fixed rdy-signal

git-svn-id: http://moon:8086/svn/vhdl/trunk@200 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/filter/src/fir_semi_parallel.vhd    | 26 +++++++++++++++----------
 lib/filter/src/tb_fir_semi_parallel.vhd |  8 +++++---
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index c02cdae..41d03e3 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -113,7 +113,6 @@ begin
 	y(0)		<= to_sfixed(0.0, y(0));
 
 	accu_load	<= accu_ld_pipe(accu_ld_pipe'left);
-	rdy			<= '1';
 	
 din_register:	
 	process(clk)
@@ -172,16 +171,21 @@ counter:
 			ce0	<= '0';
 			count0	<= cnt;
 			if rst = '1' then
+				rdy	<= '1';
 				en	<= '0';
 				cnt := count_t'high;
 			elsif cnt /= count_t'high then
 				cnt := cnt + 1;
+				if cnt = count_t'high-1 then
+					rdy	<= '1';
+				end if;	
 			else
 				en	<= '0';
 				if din_vld = '1' then
 					en	<= '1';
 					cnt := 0;
 					ce0	<= '1';
+					rdy	<= '0';
 				end if;
 			end if;
 		end if;
@@ -260,15 +264,17 @@ gen_delays:
 acumulator:
 	process(clk)
 	begin
-		if rising_edge(clk) and en = '1' then
-			dout_vld	<= accu_load;
-			if accu_load = '1' then
-				dout		<= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
-			end if;
-			if accu_load = '1' then
-				accu 	<= y(nstages);
-			else
-				accu	<= resize(accu + y(nstages), accu);
+		if rising_edge(clk) then
+			if rst = '1' then
+				dout_vld	<= '0';
+			elsif en = '1' then
+				dout_vld	<= accu_load;
+				if accu_load = '1' then
+					dout		<= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
+					accu 	<= y(nstages);
+				else
+					accu	<= resize(accu + y(nstages), accu);
+				end if;
 			end if;
 		end if;
 	end process;
diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd
index 2ef7af8..95d7cf6 100644
--- a/lib/filter/src/tb_fir_semi_parallel.vhd
+++ b/lib/filter/src/tb_fir_semi_parallel.vhd
@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
 ENTITY tb_fir_semi_parallel IS
 	Generic
 	(
-		ntaps_per_stage		: integer := 4;
-		nstages				: integer := 8;
+		ntaps_per_stage		: integer := 32;
+		nstages				: integer := 2;
 		nbits_in			: integer := 32;
 		nbits_in_frac		: integer := 30;
 		nbits_stages		: integer := 32;
@@ -170,13 +170,15 @@ BEGIN
 			wait until rising_edge(clk) and rdy = '1';
 			din_vld <= '1';
 			d_in <= to_sfixed(real(i)*0.01, d_in);
+			wait until rising_edge(clk);
+			din_vld <= '0';
 		end loop;
 		wait until rising_edge(clk) and rdy = '1';
 		------------------------------------------
 		din_vld <= '1';
 		d_in <= to_sfixed(0.0, d_in);
 		wait for 64*ntaps*PERIOD;
-		wait until rising_edge(clk) and rdy = '1';
+		wait until rising_edge(clk);
 		din_vld <= '0';
 		
  		wait for 64*ntaps*PERIOD;