- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1420 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:09:13 +00:00
parent b06e84a2b7
commit e3aeadebf5
7 changed files with 210 additions and 0 deletions
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 work
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 vhdl work "scopetest.vhd"
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 #
 #     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
 #     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
 #     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
 #     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
 #     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
 #     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
 #     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
 #     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
 #     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
 #     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
 #     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
 #     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 #     FOR A PARTICULAR PURPOSE.
 #     
 #     (c) Copyright 2005 Xilinx, Inc.
 #     All rights reserved.
 #
 # Bus clock nets
 NET "sys_clk"  TNM_NET = "sys_clk";
 TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
 NET sys_clk LOC = AE14;
 NET sys_clk IOSTANDARD = LVCMOS33;
 NET sys_rst_n LOC = D6;
 NET sys_rst_n PULLUP;
 NET sys_rst_n TIG;
 NET sys_rst_n IOSTANDARD = LVCMOS33;
 #------------------------------------------------------------------------------
 # IO Pad Location Constraints / Properties for Expansion Header GPIO
 #------------------------------------------------------------------------------
 #SMA Connectors
 NET clk_out_sma<0> LOC = C12; # SMA_IN_N
 NET clk_out_sma<1> LOC = C13; # SMA_IN_P
 NET clk_out_sma<2> LOC = D7;  # SMA_OUT_N
 NET clk_out_sma<3> LOC = D8;  # SMA_OUT_P
 NET clk_out_sma<*> IOSTANDARD = LVCMOS33;
 NET clk_out_sma<*> SLEW = FAST;
 NET clk_out_sma<*> DRIVE = 12;
 # Headers
 NET clk_out_bus<0> LOC = AF24; # HDR1_64
 NET clk_out_bus<1> LOC = AE24; # HDR1_62
 NET clk_out_bus<2> LOC = AD22; # HDR1_8
 NET clk_out_bus<3> LOC = AB21; # HDR1_58
 NET clk_out_bus<4> LOC = W20;  # HDR1_44
 NET clk_out_bus<5> LOC = W21;  # HDR1_48
 NET clk_out_bus<6> LOC = AB22; # HDR1_14
 NET clk_out_bus<7> LOC = AD25; # HDR1_20
 NET clk_out_bus<*> IOSTANDARD = LVCMOS33;
 NET clk_out_bus<*> SLEW = FAST;
 NET clk_out_bus<*> DRIVE = 12;
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 -w
 -g DebugBitstream:No
 -g Binary:no
 -g CRC:Enable
 -g ConfigRate:4
 -g CclkPin:PullUp
 -g M0Pin:PullUp
 -g M1Pin:PullUp
 -g M2Pin:PullUp
 -g ProgPin:PullUp
 -g DonePin:PullUp
 -g InitPin:Pullup
 -g CsPin:Pullup
 -g DinPin:Pullup
 -g BusyPin:Pullup
 -g RdWrPin:Pullup
 -g TckPin:PullUp
 -g TdiPin:PullUp
 -g TdoPin:PullUp
 -g TmsPin:PullUp
 -g UnusedPin:PullDown
 -g UserID:0xFFFFFFFF
 -g DCIUpdateMode:AsRequired
 -g StartUpClk:JtagClk
 -g DONE_cycle:4
 -g GTS_cycle:5
 -g GWE_cycle:6
 -g LCK_cycle:NoWait
 -g Match_cycle:Auto
 -g Security:None
 -g DonePipe:No
 -g DriveDone:No
 -g Encrypt:No
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 set -tmpdir "W:/vhdl/projects/scopetest/xst/projnav.tmp"
 set -xsthdpdir "W:/vhdl/projects/scopetest/xst"
 run
 -ifn scopetest.prj
 -ifmt mixed
 -ofn scopetest
 -ofmt NGC
 -p xc4vsx35-10-ff668
 -top scopetest
 -opt_mode Speed
 -opt_level 1
 -power NO
 -iuc NO
 -lso scopetest.lso
 -keep_hierarchy NO
 -netlist_hierarchy as_optimized
 -rtlview Yes
 -glob_opt AllClockNets
 -read_cores YES
 -write_timing_constraints NO
 -cross_clock_analysis NO
 -hierarchy_separator /
 -bus_delimiter <>
 -case maintain
 -slice_utilization_ratio 100
 -bram_utilization_ratio 100
 -dsp_utilization_ratio 100
 -verilog2001 YES
 -fsm_extract YES -fsm_encoding Auto
 -safe_implementation No
 -fsm_style lut
 -ram_extract Yes
 -ram_style Auto
 -rom_extract Yes
 -mux_style Auto
 -decoder_extract YES
 -priority_extract YES
 -shreg_extract YES
 -shift_extract YES
 -xor_collapse YES
 -rom_style Auto
 -auto_bram_packing NO
 -mux_extract YES
 -resource_sharing YES
 -async_to_sync NO
 -use_dsp48 auto
 -iobuf YES
 -max_fanout 500
 -bufg 32
 -bufr 24
 -register_duplication YES
 -register_balancing No
 -slice_packing YES
 -optimize_primitives NO
 -use_clock_enable Auto
 -use_sync_set Auto
 -use_sync_reset Auto
 -iob auto
 -equivalent_register_removal YES
 -slice_utilization_ratio_maxmargin 5
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 vhdl work "W:\vhdl\projects\scopetest\scopetest.vhd"
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 ----------------------------------------------------------------------------------
 -- Company: 
 -- Engineer: 
 -- 
 -- Create Date:    08:22:40 01/17/2009 
 -- Design Name: 
 -- Module Name:    scopetest - Behavioral 
 -- Project Name: 
 -- Target Devices: 
 -- Tool versions: 
 -- Description: 
 --
 -- Dependencies: 
 --
 -- Revision: 
 -- Revision 0.01 - File Created
 -- Additional Comments: 
 --
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 ---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 entity scopetest is
    Port ( sys_clk : in  STD_LOGIC;
           sys_rst_n : in  STD_LOGIC;
           clk_out_bus : out  STD_LOGIC_VECTOR (7 downto 0);
           clk_out_sma : out  STD_LOGIC_VECTOR (3 downto 0)
 			  );
 end scopetest;
 architecture Behavioral of scopetest is
 signal count : STD_LOGIC_VECTOR (6 downto 0);
 begin
 clk_out_bus <= count & sys_clk;
 clk_out_sma <= count(3 downto 1) & sys_clk;
 process (sys_clk) 
 begin
   if sys_clk='1' and sys_clk'event then
      if sys_rst_n='0' then 
         count <= (others => '0');
      else
         count <= count + 1;
      end if;
   end if;
 end process; 
 end Behavioral;
		`@@ -0,0 +1 @@`
							`vhdl work "W:\vhdl\projects\scopetest\scopetest.vhd"`