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git-svn-id: http://moon:8086/svn/vhdl/trunk@1420 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-21 11:09:13 +00:00
parent b06e84a2b7
commit e3aeadebf5
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projects/scopetest/project/scopetest.ucf
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#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE.
#
# (c) Copyright 2005 Xilinx, Inc.
# All rights reserved.
#
# Bus clock nets
NET "sys_clk" TNM_NET = "sys_clk";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET sys_clk LOC = AE14;
NET sys_clk IOSTANDARD = LVCMOS33;
NET sys_rst_n LOC = D6;
NET sys_rst_n PULLUP;
NET sys_rst_n TIG;
NET sys_rst_n IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for Expansion Header GPIO
#------------------------------------------------------------------------------
#SMA Connectors
NET clk_out_sma<0> LOC = C12; # SMA_IN_N
NET clk_out_sma<1> LOC = C13; # SMA_IN_P
NET clk_out_sma<2> LOC = D7; # SMA_OUT_N
NET clk_out_sma<3> LOC = D8; # SMA_OUT_P
NET clk_out_sma<*> IOSTANDARD = LVCMOS33;
NET clk_out_sma<*> SLEW = FAST;
NET clk_out_sma<*> DRIVE = 12;
# Headers
NET clk_out_bus<0> LOC = AF24; # HDR1_64
NET clk_out_bus<1> LOC = AE24; # HDR1_62
NET clk_out_bus<2> LOC = AD22; # HDR1_8
NET clk_out_bus<3> LOC = AB21; # HDR1_58
NET clk_out_bus<4> LOC = W20; # HDR1_44
NET clk_out_bus<5> LOC = W21; # HDR1_48
NET clk_out_bus<6> LOC = AB22; # HDR1_14
NET clk_out_bus<7> LOC = AD25; # HDR1_20
NET clk_out_bus<*> IOSTANDARD = LVCMOS33;
NET clk_out_bus<*> SLEW = FAST;
NET clk_out_bus<*> DRIVE = 12;