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git-svn-id: http://moon:8086/svn/vhdl/trunk@1420 cc03376c-175c-47c8-b038-4cd826a8556b
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work
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vhdl work "scopetest.vhd"
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#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE.
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#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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# Bus clock nets
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NET "sys_clk" TNM_NET = "sys_clk";
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TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
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NET sys_clk LOC = AE14;
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NET sys_clk IOSTANDARD = LVCMOS33;
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NET sys_rst_n LOC = D6;
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NET sys_rst_n PULLUP;
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NET sys_rst_n TIG;
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NET sys_rst_n IOSTANDARD = LVCMOS33;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for Expansion Header GPIO
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#------------------------------------------------------------------------------
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#SMA Connectors
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NET clk_out_sma<0> LOC = C12; # SMA_IN_N
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NET clk_out_sma<1> LOC = C13; # SMA_IN_P
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NET clk_out_sma<2> LOC = D7; # SMA_OUT_N
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NET clk_out_sma<3> LOC = D8; # SMA_OUT_P
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NET clk_out_sma<*> IOSTANDARD = LVCMOS33;
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NET clk_out_sma<*> SLEW = FAST;
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NET clk_out_sma<*> DRIVE = 12;
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# Headers
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NET clk_out_bus<0> LOC = AF24; # HDR1_64
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NET clk_out_bus<1> LOC = AE24; # HDR1_62
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NET clk_out_bus<2> LOC = AD22; # HDR1_8
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NET clk_out_bus<3> LOC = AB21; # HDR1_58
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NET clk_out_bus<4> LOC = W20; # HDR1_44
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NET clk_out_bus<5> LOC = W21; # HDR1_48
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NET clk_out_bus<6> LOC = AB22; # HDR1_14
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NET clk_out_bus<7> LOC = AD25; # HDR1_20
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NET clk_out_bus<*> IOSTANDARD = LVCMOS33;
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NET clk_out_bus<*> SLEW = FAST;
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NET clk_out_bus<*> DRIVE = 12;
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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g ConfigRate:4
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-g CclkPin:PullUp
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-g M0Pin:PullUp
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-g M1Pin:PullUp
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-g M2Pin:PullUp
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-g ProgPin:PullUp
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-g DonePin:PullUp
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-g InitPin:Pullup
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-g CsPin:Pullup
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-g DinPin:Pullup
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-g BusyPin:Pullup
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-g RdWrPin:Pullup
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g DCIUpdateMode:AsRequired
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-g StartUpClk:JtagClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Match_cycle:Auto
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-g Security:None
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-g DonePipe:No
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-g DriveDone:No
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-g Encrypt:No
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set -tmpdir "W:/vhdl/projects/scopetest/xst/projnav.tmp"
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set -xsthdpdir "W:/vhdl/projects/scopetest/xst"
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run
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-ifn scopetest.prj
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-ifmt mixed
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-ofn scopetest
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-ofmt NGC
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-p xc4vsx35-10-ff668
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-top scopetest
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-lso scopetest.lso
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-keep_hierarchy NO
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-netlist_hierarchy as_optimized
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-verilog2001 YES
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-mux_style Auto
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-decoder_extract YES
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-priority_extract YES
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-shreg_extract YES
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-shift_extract YES
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-xor_collapse YES
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-rom_style Auto
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-auto_bram_packing NO
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-mux_extract YES
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf YES
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-max_fanout 500
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-bufg 32
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-bufr 24
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-register_duplication YES
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-register_balancing No
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-slice_packing YES
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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vhdl work "W:\vhdl\projects\scopetest\scopetest.vhd"
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