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git-svn-id: http://moon:8086/svn/vhdl/trunk@782 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-13 10:50:30 +00:00
parent 874df39347
commit e27c0f791a
4 changed files with 861 additions and 731 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.syr
+32 -30
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: mips_sys.prj
@@ -271,7 +271,8 @@ Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <
data_width = 16
f_sysclk = 100.000000
Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>).
Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>) with generics.
simulate_tx = false
Analyzing hierarchy for entity <clockgen> in library <work> (architecture <tech>) with generics.
clk_in_freq = 100.000000
@@ -688,7 +689,8 @@ Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <beha
f_sysclk = 100.000000
Entity <async_port_wb.2> analyzed. Unit <async_port_wb.2> generated.
Analyzing Entity <uart_wb> in library <work> (Architecture <behavior>).
Analyzing generic Entity <uart_wb> in library <work> (Architecture <behavior>).
simulate_tx = false
INFO:Xst:2679 - Register <DAT_O<31>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<30>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<29>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
@@ -2654,7 +2656,7 @@ WARNING:Xst:646 - Signal <tx_complete> is assigned but never used. This unconnec
Found 16-bit register for signal <DAT_O<15:0>>.
Found 1-bit register for signal <ACK_O>.
Found 16-bit up counter for signal <baud_count>.
Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 146.
Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 162.
Found 1-bit register for signal <en_16_x_baud>.
Found 1-bit register for signal <irq_rx>.
Found 1-bit register for signal <irq_tx>.
@@ -4902,28 +4904,28 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_18) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/was_write) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_4) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift18) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_4)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_8) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_ps2_phy_1/Inst_debounce_data/count_2) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_6) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_1) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift1) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_3) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift17) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
Timing Summary:
---------------
@@ -5212,12 +5214,12 @@ Delay: 10.288ns (Levels of Logic = 11)
=========================================================================
Total REAL time to Xst completion: 126.00 secs
Total CPU time to Xst completion: 126.49 secs
Total REAL time to Xst completion: 128.00 secs
Total CPU time to Xst completion: 128.61 secs
-->
Total memory usage is 371060 kilobytes
Total memory usage is 357364 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1003 ( 0 filtered)