From e27c0f791a745d30f4935d0106ca665021fe80c3 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 13 Mar 2010 10:50:30 +0000 Subject: [PATCH] update Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@782 cc03376c-175c-47c8-b038-4cd826a8556b --- .../mips_sys/ise101/mips_sys/mips_sys.par | 115 +- .../mips_sys/ise101/mips_sys/mips_sys.syr | 62 +- .../mips_sys/ise101/mips_sys/mips_sys.twr | 1230 +++++++++-------- .../mips_sys/ise101/mips_sys/mips_sys_map.mrp | 185 +-- 4 files changed, 861 insertions(+), 731 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par index 8c1082d..20658d1 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.par +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -1,7 +1,7 @@ Release 10.1.03 par K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -JUPITER:: Sun Feb 14 18:14:54 2010 +JUPITER:: Tue Mar 09 13:07:50 2010 par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd mips_sys.pcf @@ -31,8 +31,8 @@ Device Utilization Summary: Number of OLOGICs 182 out of 448 40% Number of RAMB16s 51 out of 192 26% - Number of Slices 6008 out of 15360 39% - Number of SLICEMs 558 out of 7680 7% + Number of Slices 5907 out of 15360 38% + Number of SLICEMs 543 out of 7680 7% @@ -40,42 +40,44 @@ Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 14 secs -Finished initial Timing Analysis. REAL time: 14 secs +Finished initial Timing Analysis. REAL time: 15 secs Starting Router -Phase 1: 48218 unrouted; REAL time: 15 secs +Phase 1: 47928 unrouted; REAL time: 16 secs -Phase 2: 41114 unrouted; REAL time: 16 secs +Phase 2: 40960 unrouted; REAL time: 17 secs -Phase 3: 15775 unrouted; REAL time: 22 secs +Phase 3: 15655 unrouted; REAL time: 24 secs -Phase 4: 15775 unrouted; (290927) REAL time: 23 secs +Phase 4: 15655 unrouted; (245197) REAL time: 24 secs -Phase 5: 16549 unrouted; (7681) REAL time: 26 secs +Phase 5: 16281 unrouted; (4341) REAL time: 27 secs -Phase 6: 16600 unrouted; (0) REAL time: 26 secs +Phase 6: 16339 unrouted; (710) REAL time: 28 secs -Phase 7: 0 unrouted; (942) REAL time: 53 secs +Phase 7: 0 unrouted; (9891) REAL time: 53 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 8: 0 unrouted; (942) REAL time: 1 mins 14 secs +Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs -Phase 9: 0 unrouted; (942) REAL time: 1 mins 20 secs +Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs -Phase 10: 0 unrouted; (0) REAL time: 1 mins 26 secs - -Phase 11: 0 unrouted; (0) REAL time: 1 mins 27 secs +Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 12: 0 unrouted; (0) REAL time: 1 mins 46 secs +Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs -Phase 13: 0 unrouted; (0) REAL time: 1 mins 52 secs +Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs -Total REAL time to Router completion: 1 mins 54 secs -Total CPU time to Router completion: 1 mins 49 secs +Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs + +Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs + +Total REAL time to Router completion: 3 mins 9 secs +Total CPU time to Router completion: 3 mins 3 secs Partition Implementation Status ------------------------------- @@ -93,28 +95,28 @@ Generating Clock Report +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ -| cpu_clk |BUFGCTRL_X0Y12| No | 1638 | 0.443 | 4.049 | +| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 | +---------------------+--------------+------+------+------------+-------------+ -| CLK_O | BUFGCTRL_X0Y2| No | 2331 | 0.533 | 3.922 | -+---------------------+--------------+------+------+------------+-------------+ -| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.287 | 3.881 | +| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 | +---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_clk1 | BUFGCTRL_X0Y0| No | 75 | 0.416 | 3.851 | +| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 | +---------------------+--------------+------+------+------------+-------------+ -| sdram_clk0 |BUFGCTRL_X0Y31| No | 241 | 0.494 | 3.933 | +| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 | +---------------------+--------------+------+------+------------+-------------+ |sys_ac97_bit_clk_IBU | | | | | | -| F | BUFGCTRL_X0Y8| No | 251 | 0.356 | 3.903 | +| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 | +---------------------+--------------+------+------+------------+-------------+ -| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 62 | 0.223 | 3.686 | +| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 | +---------------------+--------------+------+------+------------+-------------+ -| sdram_clk270 |BUFGCTRL_X0Y16| No | 65 | 0.160 | 3.932 | +| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 | +---------------------+--------------+------+------+------------+-------------+ | sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 | +---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.146 | 3.628 | +| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing @@ -122,7 +124,20 @@ only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. -Timing Score: 0 +Timing Score: 1304 + +WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in + your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and select + the "Timing Improvement Wizard" link for suggestions to correct each problem. + + Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to + ensure the best options are set in the tools for timing closure. + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -133,31 +148,31 @@ Asterisk (*) preceding a constraint indicates it was not met. Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ - TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.018ns| 9.864ns| 0| 0 - ns HIGH 50% | HOLD | 0.314ns| | 0| 0 +* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107 + HIGH 50% | HOLD | 0.365ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.054ns| 7.392ns| 0| 0 - 7.5 ns HIGH 50% | HOLD | 0.518ns| | 0| 0 +* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197 + ns HIGH 50% | HOLD | 0.346ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.109ns| 7.891ns| 0| 0 - s HIGH 50% | HOLD | 0.480ns| | 0| 0 + TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0 + 7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.166ns| 9.734ns| 0| 0 - HIGH 50% | HOLD | 0.333ns| | 0| 0 + TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0 + s HIGH 50% | HOLD | 0.514ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.896ns| 8.208ns| 0| 0 + NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0 ns HIGH 50% | HOLD | 0.518ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.311ns| 4.689ns| 0| 0 - ns HIGH 50% | HOLD | 0.783ns| | 0| 0 + TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0 + ns HIGH 50% | HOLD | 0.802ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.588ns| N/A| 0 + PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.296ns| N/A| 0 + PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0 ------------------------------------------------------------------------------------------------------ -All constraints were met. +2 constraints not met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. @@ -166,17 +181,17 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 2 mins 3 secs -Total CPU time to PAR completion: 1 mins 55 secs +Total REAL time to PAR completion: 3 mins 18 secs +Total CPU time to PAR completion: 3 mins 9 secs -Peak Memory Usage: 453 MB +Peak Memory Usage: 428 MB Placer: Placement generated during map. Routing: Completed - No errors found. -Timing: Completed - No errors found. +Timing: Completed - 10 errors found. Number of error messages: 0 -Number of warning messages: 0 +Number of warning messages: 1 Number of info messages: 1 Writing design to file mips_sys.ncd diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr index 1957dc4..51fc424 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.11 secs +Total CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.11 secs +Total CPU time to Xst completion: 0.13 secs --> Reading design: mips_sys.prj @@ -271,7 +271,8 @@ Analyzing hierarchy for entity in library (architecture < data_width = 16 f_sysclk = 100.000000 -Analyzing hierarchy for entity in library (architecture ). +Analyzing hierarchy for entity in library (architecture ) with generics. + simulate_tx = false Analyzing hierarchy for entity in library (architecture ) with generics. clk_in_freq = 100.000000 @@ -688,7 +689,8 @@ Analyzing generic Entity in library (Architecture analyzed. Unit generated. -Analyzing Entity in library (Architecture ). +Analyzing generic Entity in library (Architecture ). + simulate_tx = false INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. @@ -2654,7 +2656,7 @@ WARNING:Xst:646 - Signal is assigned but never used. This unconnec Found 16-bit register for signal >. Found 1-bit register for signal . Found 16-bit up counter for signal . - Found 16-bit comparator equal for signal created at line 146. + Found 16-bit comparator equal for signal created at line 162. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -4902,28 +4904,28 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG Asynchronous Control Signals Information: ---------------------------------------- ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ -RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0)| 289 | -inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_18) | 96 | -RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/was_write) | 75 | -inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out) | 52 | -inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_4) | 29 | -inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 | -inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 | -inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 20 | -inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift18) | 20 | -rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+ +RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_4)| 289 | +inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_8) | 96 | +RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_ps2_phy_1/Inst_debounce_data/count_2) | 75 | +inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_6) | 52 | +inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_1) | 29 | +inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 | +inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift1) | 20 | +inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_3) | 20 | +inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift17) | 20 | +rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+ Timing Summary: --------------- @@ -5212,12 +5214,12 @@ Delay: 10.288ns (Levels of Logic = 11) ========================================================================= -Total REAL time to Xst completion: 126.00 secs -Total CPU time to Xst completion: 126.49 secs +Total REAL time to Xst completion: 128.00 secs +Total CPU time to Xst completion: 128.61 secs --> -Total memory usage is 371060 kilobytes +Total memory usage is 357364 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1003 ( 0 filtered) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr index 2c3a3e4..1852459 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.twr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.twr @@ -30,93 +30,93 @@ Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%; 3447 paths analyzed, 643 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 8.208ns. + Minimum period is 6.700ns. -------------------------------------------------------------------------------- -Slack: 35.896ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 36.650ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 (FF) Requirement: 40.000ns - Data Path Delay: 4.041ns (Levels of Logic = 0) - Clock Path Skew: -0.063ns (2.774 - 2.837) + Data Path Delay: 3.345ns (Levels of Logic = 0) + Clock Path Skew: -0.005ns (2.621 - 2.626) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X33Y79.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 - SLICE_X17Y86.BY net (fanout=14) 3.442 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - SLICE_X17Y86.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 - inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 + SLICE_X58Y78.BY net (fanout=14) 2.779 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X58Y78.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 ------------------------------------------------- --------------------------- - Total 4.041ns (0.599ns logic, 3.442ns route) - (14.8% logic, 85.2% route) + Total 3.345ns (0.566ns logic, 2.779ns route) + (16.9% logic, 83.1% route) -------------------------------------------------------------------------------- -Slack: 36.344ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 (FF) +Slack: 37.046ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF) Requirement: 40.000ns - Data Path Delay: 3.616ns (Levels of Logic = 0) - Clock Path Skew: -0.040ns (2.797 - 2.837) + Data Path Delay: 2.678ns (Levels of Logic = 0) + Clock Path Skew: -0.276ns (2.456 - 2.732) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 - SLICE_X15Y82.BY net (fanout=14) 3.017 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - SLICE_X15Y82.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 - inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 + SLICE_X27Y85.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 + SLICE_X47Y78.BY net (fanout=13) 2.100 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> + SLICE_X47Y78.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15> + inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 ------------------------------------------------- --------------------------- - Total 3.616ns (0.599ns logic, 3.017ns route) - (16.6% logic, 83.4% route) + Total 2.678ns (0.578ns logic, 2.100ns route) + (21.6% logic, 78.4% route) -------------------------------------------------------------------------------- -Slack: 36.860ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 (FF) +Slack: 37.336ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 (FF) Requirement: 40.000ns - Data Path Delay: 3.100ns (Levels of Logic = 0) - Clock Path Skew: -0.040ns (2.797 - 2.837) + Data Path Delay: 2.643ns (Levels of Logic = 0) + Clock Path Skew: -0.021ns (2.621 - 2.642) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 - SLICE_X14Y82.BY net (fanout=14) 2.513 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> - SLICE_X14Y82.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 - inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 + SLICE_X32Y89.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 + SLICE_X58Y78.BX net (fanout=13) 2.057 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> + SLICE_X58Y78.CLK Tdick 0.279 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 ------------------------------------------------- --------------------------- - Total 3.100ns (0.587ns logic, 2.513ns route) - (18.9% logic, 81.1% route) + Total 2.643ns (0.586ns logic, 2.057ns route) + (22.2% logic, 77.8% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%; - 450917 paths analyzed, 11152 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.734ns. + 450849 paths analyzed, 11154 endpoints analyzed, 9 failing endpoints + 9 timing errors detected. (9 setup errors, 0 hold errors) + Minimum period is 10.193ns. -------------------------------------------------------------------------------- -Slack: 0.166ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/s_FSM_FFd6 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 (FF) +Slack: -0.293ns (requirement - (data path - clock path skew + uncertainty)) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F (RAM) Requirement: 9.900ns - Data Path Delay: 9.625ns (Levels of Logic = 9) + Data Path Delay: 10.084ns (Levels of Logic = 10) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -128,53 +128,52 @@ Slack: 0.166ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd6 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X43Y67.XQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd6 - inst_vga_frontend/s_FSM_FFd6 - SLICE_X46Y81.F4 net (fanout=10) 1.470 inst_vga_frontend/s_FSM_FFd6 - SLICE_X46Y81.X Tilo 0.195 N379 - inst_vga_frontend/inst_blitfifo/mem_wr_en1_SW0 - SLICE_X54Y96.F1 net (fanout=1) 1.438 N379 - SLICE_X54Y96.X Tilo 0.195 inst_ps2_wb_1/ACK_O - inst_vga_frontend/inst_blitfifo/mem_wr_en1 - SLICE_X59Y126.G4 net (fanout=20) 1.112 inst_vga_frontend/read_cnt_and0000 - SLICE_X59Y126.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb<0> - inst_vga_frontend/inst_linefifo/mem_wr_en1 - SLICE_X58Y128.G3 net (fanout=41) 0.492 inst_vga_frontend/inst_linefifo/mem_wr_en - SLICE_X58Y128.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<0>_FRB - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<1>1 - SLICE_X59Y131.G2 net (fanout=3) 0.513 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<1> - SLICE_X59Y131.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<5>_FRB - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X59Y132.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> - SLICE_X59Y132.XMUX Tcinx 0.438 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<6>_FRB - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> - SLICE_X60Y131.F1 net (fanout=2) 0.785 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> - SLICE_X60Y131.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<4>_FRB - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X60Y132.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> - SLICE_X60Y132.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB2 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<4> - SLICE_X63Y132.G3 net (fanout=1) 0.457 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<4> - SLICE_X63Y132.CLK Tgck 0.231 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<4>1 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 + SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0> + SLICE_X38Y63.Y Tilo 0.195 N739 + Mmux_ADDR_O241 + SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30> + SLICE_X40Y59.XMUX Tbxx 0.513 N105 + CYC_O1_SW1 + SLICE_X40Y61.G4 net (fanout=2) 0.416 N105 + SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb + CYC_I_ac971 + SLICE_X38Y67.G4 net (fanout=15) 0.917 CYC_I_ac971 + SLICE_X38Y67.Y Tilo 0.195 MDAT_I<8>27 + CYC_I_gpio1 + SLICE_X36Y60.G3 net (fanout=27) 0.668 CYC_I_gpio + SLICE_X36Y60.Y Tilo 0.195 N54 + MDAT_I<2>56_SW0_SW0 + SLICE_X47Y59.G4 net (fanout=1) 0.949 N135 + SLICE_X47Y59.Y Tilo 0.194 MDAT_I<2>56 + MDAT_I<2>56_SW0 + SLICE_X47Y59.F4 net (fanout=1) 0.159 N1197 + SLICE_X47Y59.X Tilo 0.194 MDAT_I<2>56 + MDAT_I<2>56 + SLICE_X44Y57.G4 net (fanout=1) 0.384 MDAT_I<2>56 + SLICE_X44Y57.Y Tilo 0.195 MDAT_I<2> + MDAT_I<2>89_SW0 + SLICE_X44Y57.F3 net (fanout=1) 0.213 N1324 + SLICE_X44Y57.X Tilo 0.195 MDAT_I<2> + MDAT_I<2>89 + SLICE_X34Y53.BY net (fanout=1) 0.774 MDAT_I<2> + SLICE_X34Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<2> + inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F ------------------------------------------------- --------------------------- - Total 9.625ns (3.358ns logic, 6.267ns route) - (34.9% logic, 65.1% route) + Total 10.084ns (3.493ns logic, 6.591ns route) + (34.6% logic, 65.4% route) -------------------------------------------------------------------------------- -Slack: 0.169ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/s_FSM_FFd5 (FF) - Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 (FF) +Slack: -0.194ns (requirement - (data path - clock path skew + uncertainty)) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM) Requirement: 9.900ns - Data Path Delay: 9.622ns (Levels of Logic = 12) + Data Path Delay: 9.985ns (Levels of Logic = 10) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -186,62 +185,53 @@ Slack: 0.169ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X43Y73.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 - inst_vga_frontend/s_FSM_FFd5 - SLICE_X43Y72.G3 net (fanout=49) 0.433 inst_vga_frontend/s_FSM_FFd5 - SLICE_X43Y72.Y Tilo 0.194 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW<0> - inst_vga_frontend/s_FSM_Out61 - SLICE_X38Y65.G4 net (fanout=4) 1.002 inst_vga_frontend/CYC_O_blit_src - SLICE_X38Y65.Y Tilo 0.195 CYC_O - inst_vga_frontend/CYC_O1 - SLICE_X38Y65.F3 net (fanout=8) 0.236 CYC_O_vga - SLICE_X38Y65.X Tilo 0.195 CYC_O - CYC_O1 - SLICE_X39Y64.F1 net (fanout=6) 0.670 CYC_O - SLICE_X39Y64.X Tilo 0.194 N701 - SRDY_I16_SW0 - SLICE_X39Y65.G2 net (fanout=2) 0.503 N701 - SLICE_X39Y65.Y Tilo 0.194 SRDY_I_cpu - SRDY_I26_SW1 - SLICE_X39Y65.F4 net (fanout=1) 0.159 SRDY_I26_SW1/O - SLICE_X39Y65.X Tilo 0.194 SRDY_I_cpu - SRDY_I_cpu1 - SLICE_X39Y51.G4 net (fanout=2) 0.578 SRDY_I_cpu - SLICE_X39Y51.Y Tilo 0.194 ADDR_O_cpu<4> - inst_mips_top/inst_biu/bout_fifo_re1 - SLICE_X37Y52.G4 net (fanout=4) 0.386 inst_mips_top/inst_biu/bout_fifo_re - SLICE_X37Y52.Y Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<3> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>_bdd0 - SLICE_X37Y53.G4 net (fanout=2) 0.331 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>_bdd0 - SLICE_X37Y53.Y Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<4> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>11 - SLICE_X37Y53.F4 net (fanout=1) 0.159 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/bnxt_r<4> - SLICE_X37Y53.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<4> - inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en41 - SLICE_X39Y50.BX net (fanout=1) 0.336 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en_bdd4 - SLICE_X39Y50.XMUX Tbxx 0.511 ADDR_O_cpu<11> - inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en21_f5 - SLICE_X39Y48.F4 net (fanout=2) 0.403 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en_bdd0 - SLICE_X39Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<0> - inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en11 - SLICE_X38Y33.CE net (fanout=38) 0.885 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en - SLICE_X38Y33.CLK Tceck 0.554 MDAT_O_cpu<10> - inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 + SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0> + SLICE_X38Y63.Y Tilo 0.195 N739 + Mmux_ADDR_O241 + SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30> + SLICE_X40Y59.XMUX Tbxx 0.513 N105 + CYC_O1_SW1 + SLICE_X40Y61.G4 net (fanout=2) 0.416 N105 + SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb + CYC_I_ac971 + SLICE_X38Y67.G4 net (fanout=15) 0.917 CYC_I_ac971 + SLICE_X38Y67.Y Tilo 0.195 MDAT_I<8>27 + CYC_I_gpio1 + SLICE_X42Y64.G3 net (fanout=27) 0.918 CYC_I_gpio + SLICE_X42Y64.Y Tilo 0.195 N851 + MDAT_I<0>56_SW0_SW0 + SLICE_X45Y64.G4 net (fanout=1) 0.322 N143 + SLICE_X45Y64.Y Tilo 0.194 MDAT_I<0>56 + MDAT_I<0>56_SW0 + SLICE_X45Y64.F3 net (fanout=1) 0.222 N1205 + SLICE_X45Y64.X Tilo 0.194 MDAT_I<0>56 + MDAT_I<0>56 + SLICE_X40Y53.G2 net (fanout=1) 0.757 MDAT_I<0>56 + SLICE_X40Y53.Y Tilo 0.195 MDAT_I<0> + MDAT_I<0>89_SW0 + SLICE_X40Y53.F3 net (fanout=1) 0.213 N1332 + SLICE_X40Y53.X Tilo 0.195 MDAT_I<0> + MDAT_I<0>89 + SLICE_X38Y53.BY net (fanout=1) 0.616 MDAT_I<0> + SLICE_X38Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0> + inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F ------------------------------------------------- --------------------------- - Total 9.622ns (3.541ns logic, 6.081ns route) - (36.8% logic, 63.2% route) + Total 9.985ns (3.493ns logic, 6.492ns route) + (35.0% logic, 65.0% route) -------------------------------------------------------------------------------- -Slack: 0.173ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty (FF) - Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 (FF) +Slack: -0.174ns (requirement - (data path - clock path skew + uncertainty)) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM) Requirement: 9.900ns - Data Path Delay: 9.458ns (Levels of Logic = 8) - Clock Path Skew: -0.160ns (2.487 - 2.647) + Data Path Delay: 9.965ns (Levels of Logic = 10) + Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns Clock Uncertainty: 0.109ns @@ -252,42 +242,45 @@ Slack: 0.173ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X39Y53.YQ Tcko 0.340 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<2> - inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty - SLICE_X39Y52.G4 net (fanout=7) 0.398 inst_mips_top/inst_biu/bout_fifo_empty - SLICE_X39Y52.Y Tilo 0.194 ADDR_O_cpu<30> - inst_mips_top/inst_biu/CYC_O1 - SLICE_X38Y63.F3 net (fanout=7) 0.805 CYC_O_cpu - SLICE_X38Y63.X Tilo 0.195 N113 - CYC_O1_SW2 - SLICE_X36Y62.G1 net (fanout=2) 1.238 N113 - SLICE_X36Y62.Y Tilo 0.195 N104 - CYC_I_flash_1 - SLICE_X39Y71.G2 net (fanout=41) 0.992 CYC_I_flash - SLICE_X39Y71.Y Tilo 0.194 N843 - SRDY_I26 - SLICE_X39Y84.G4 net (fanout=1) 0.726 SRDY_I26 - SLICE_X39Y84.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pR<0> - SRDY_I36 - SLICE_X39Y92.G3 net (fanout=3) 0.604 SRDY_I - SLICE_X39Y92.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pR<1> - inst_vga_frontend/inst_bus_fifo/rinc1 - SLICE_X39Y93.G2 net (fanout=5) 0.358 inst_vga_frontend/inst_bus_fifo/rinc - SLICE_X39Y93.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pW<0> - inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 - SLICE_X38Y92.F1 net (fanout=2) 0.396 N405 - SLICE_X38Y92.X Tilo 0.195 inst_vga_frontend/inst_bus_fifo/mem_rd_en - inst_vga_frontend/inst_bus_fifo/mem_rd_en1 - SLICE_X40Y69.CE net (fanout=103) 1.492 inst_vga_frontend/inst_bus_fifo/mem_rd_en - SLICE_X40Y69.CLK Tceck 0.554 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b<12> - inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 + SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0> + SLICE_X38Y63.Y Tilo 0.195 N739 + Mmux_ADDR_O241 + SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30> + SLICE_X40Y59.XMUX Tbxx 0.513 N105 + CYC_O1_SW1 + SLICE_X40Y61.G4 net (fanout=2) 0.416 N105 + SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb + CYC_I_ac971 + SLICE_X39Y61.G4 net (fanout=15) 0.719 CYC_I_ac971 + SLICE_X39Y61.Y Tilo 0.194 N1207 + CYC_I_ac972 + SLICE_X42Y64.G2 net (fanout=58) 1.097 CYC_I_ac97 + SLICE_X42Y64.Y Tilo 0.195 N851 + MDAT_I<0>56_SW0_SW0 + SLICE_X45Y64.G4 net (fanout=1) 0.322 N143 + SLICE_X45Y64.Y Tilo 0.194 MDAT_I<0>56 + MDAT_I<0>56_SW0 + SLICE_X45Y64.F3 net (fanout=1) 0.222 N1205 + SLICE_X45Y64.X Tilo 0.194 MDAT_I<0>56 + MDAT_I<0>56 + SLICE_X40Y53.G2 net (fanout=1) 0.757 MDAT_I<0>56 + SLICE_X40Y53.Y Tilo 0.195 MDAT_I<0> + MDAT_I<0>89_SW0 + SLICE_X40Y53.F3 net (fanout=1) 0.213 N1332 + SLICE_X40Y53.X Tilo 0.195 MDAT_I<0> + MDAT_I<0>89 + SLICE_X38Y53.BY net (fanout=1) 0.616 MDAT_I<0> + SLICE_X38Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0> + inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F ------------------------------------------------- --------------------------- - Total 9.458ns (2.449ns logic, 7.009ns route) - (25.9% logic, 74.1% route) + Total 9.965ns (3.492ns logic, 6.473ns route) + (35.0% logic, 65.0% route) -------------------------------------------------------------------------------- @@ -296,16 +289,16 @@ Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%; 1524 paths analyzed, 435 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.392ns. + Minimum period is 7.330ns. -------------------------------------------------------------------------------- -Slack: 0.054ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 (FF) - Requirement: 3.750ns - Data Path Delay: 3.572ns (Levels of Logic = 1) +Slack: 0.170ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty (FF) + Requirement: 7.500ns + Data Path Delay: 7.206ns (Levels of Logic = 6) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 falling at 3.750ns + Destination Clock: sdram_clk0 rising at 7.500ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -314,61 +307,42 @@ Slack: 0.054ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X6Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X0Y167.G1 net (fanout=9) 1.296 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X0Y167.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_8_mux00041 - OLOGIC_X0Y185.D1 net (fanout=1) 1.094 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 - OLOGIC_X0Y185.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<8> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 + RAMB16_X1Y18.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X14Y155.G1 net (fanout=15) 1.217 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26> + SLICE_X14Y155.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0 + SLICE_X16Y156.G2 net (fanout=6) 0.794 N318 + SLICE_X16Y156.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc + SLICE_X17Y155.G1 net (fanout=7) 0.595 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc + SLICE_X17Y155.XMUX Tif5x 0.574 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<5> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>1 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>_f5 + SLICE_X16Y157.F3 net (fanout=3) 0.464 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<5> + SLICE_X16Y157.X Tilo 0.195 N1006 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677_SW0 + SLICE_X17Y156.G3 net (fanout=1) 0.226 N1006 + SLICE_X17Y156.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677 + SLICE_X17Y156.F3 net (fanout=1) 0.222 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677/O + SLICE_X17Y156.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty6100 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty ------------------------------------------------- --------------------------- - Total 3.572ns (1.182ns logic, 2.390ns route) - (33.1% logic, 66.9% route) + Total 7.206ns (3.688ns logic, 3.518ns route) + (51.2% logic, 48.8% route) -------------------------------------------------------------------------------- -Slack: 0.248ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 (FF) - Requirement: 3.750ns - Data Path Delay: 3.378ns (Levels of Logic = 1) - Clock Path Skew: 0.000ns - Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 falling at 3.750ns - Clock Uncertainty: 0.124ns - - Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.248ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X6Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X2Y164.F3 net (fanout=9) 1.090 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 - SLICE_X2Y164.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB0 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_6_mux00041 - OLOGIC_X0Y188.D1 net (fanout=1) 1.106 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 - OLOGIC_X0Y188.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<6> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 - ------------------------------------------------- --------------------------- - Total 3.378ns (1.182ns logic, 2.196ns route) - (35.0% logic, 65.0% route) - --------------------------------------------------------------------------------- -Slack: 0.275ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 0.180ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5 (FF) Requirement: 3.750ns - Data Path Delay: 3.351ns (Levels of Logic = 1) + Data Path Delay: 3.446ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns Destination Clock: sdram_clk0 falling at 3.750ns @@ -380,21 +354,66 @@ Slack: 0.275ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X2Y162.XQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 + SLICE_X6Y167.XQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 - SLICE_X3Y154.G1 net (fanout=9) 1.248 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 - SLICE_X3Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB2 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_3_mux00041 - OLOGIC_X0Y179.D1 net (fanout=1) 0.922 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3 - OLOGIC_X0Y179.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<3> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 + SLICE_X6Y171.G3 net (fanout=9) 0.927 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 + SLICE_X6Y171.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_5_mux00041 + OLOGIC_X0Y187.D1 net (fanout=1) 1.337 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5 + OLOGIC_X0Y187.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<5> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5 ------------------------------------------------- --------------------------- - Total 3.351ns (1.181ns logic, 2.170ns route) - (35.2% logic, 64.8% route) + Total 3.446ns (1.182ns logic, 2.264ns route) + (34.3% logic, 65.7% route) + +-------------------------------------------------------------------------------- +Slack: 0.190ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3 (FF) + Requirement: 7.500ns + Data Path Delay: 7.186ns (Levels of Logic = 5) + Clock Path Skew: 0.000ns + Source Clock: sdram_clk0 rising at 0.000ns + Destination Clock: sdram_clk0 rising at 7.500ns + Clock Uncertainty: 0.124ns + + Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + RAMB16_X1Y18.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X14Y155.G1 net (fanout=15) 1.217 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26> + SLICE_X14Y155.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0 + SLICE_X13Y158.G2 net (fanout=6) 0.745 N318 + SLICE_X13Y158.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6 + SLICE_X13Y158.F3 net (fanout=2) 0.228 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N24 + SLICE_X13Y158.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en1 + SLICE_X13Y161.G2 net (fanout=6) 0.562 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en + SLICE_X13Y161.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001_SW0 + SLICE_X13Y161.F4 net (fanout=2) 0.168 N316 + SLICE_X13Y161.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001 + SLICE_X15Y160.CE net (fanout=4) 0.642 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001 + SLICE_X15Y160.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3 + ------------------------------------------------- --------------------------- + Total 7.186ns (3.624ns logic, 3.562ns route) + (50.4% logic, 49.6% route) -------------------------------------------------------------------------------- @@ -404,43 +423,11 @@ Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG; 24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 9.588ns (data path - clock path skew + uncertainty) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) - Data Path Delay: 3.045ns (Levels of Logic = 1) - Clock Path Skew: -6.299ns (-2.395 - 3.904) - Source Clock: CLK_O rising - Destination Clock: sdram_clk0 rising - Clock Uncertainty: 0.244ns - - Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.248ns - Phase Error (PE): 0.120ns - - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X13Y172.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X5Y154.G3 net (fanout=9) 1.527 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X5Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 - SLICE_X4Y155.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke - SLICE_X4Y155.CLK Tceck 0.554 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 - ------------------------------------------------- --------------------------- - Total 3.045ns (1.088ns logic, 1.957ns route) - (35.7% logic, 64.3% route) - --------------------------------------------------------------------------------- -Delay: 9.568ns (data path - clock path skew + uncertainty) +Delay: 9.594ns (data path - clock path skew + uncertainty) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) - Data Path Delay: 3.049ns (Levels of Logic = 1) - Clock Path Skew: -6.275ns (-2.395 - 3.880) + Data Path Delay: 3.036ns (Levels of Logic = 1) + Clock Path Skew: -6.314ns (-2.401 - 3.913) Source Clock: CLK_O rising Destination Clock: sdram_clk0 rising Clock Uncertainty: 0.244ns @@ -455,24 +442,24 @@ Delay: 9.568ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X11Y185.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X9Y176.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X5Y154.G2 net (fanout=20) 1.531 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X5Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + SLICE_X4Y154.G1 net (fanout=20) 1.519 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X4Y154.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 - SLICE_X4Y155.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke - SLICE_X4Y155.CLK Tceck 0.554 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + SLICE_X5Y154.CE net (fanout=1) 0.429 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X5Y154.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 ------------------------------------------------- --------------------------- - Total 3.049ns (1.088ns logic, 1.961ns route) - (35.7% logic, 64.3% route) + Total 3.036ns (1.088ns logic, 1.948ns route) + (35.8% logic, 64.2% route) -------------------------------------------------------------------------------- -Delay: 9.480ns (data path - clock path skew + uncertainty) +Delay: 9.133ns (data path - clock path skew + uncertainty) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) - Data Path Delay: 2.940ns (Levels of Logic = 2) - Clock Path Skew: -6.296ns (-2.392 - 3.904) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) + Data Path Delay: 2.602ns (Levels of Logic = 1) + Clock Path Skew: -6.287ns (-2.401 - 3.886) Source Clock: CLK_O rising Destination Clock: sdram_clk0 rising Clock Uncertainty: 0.244ns @@ -483,37 +470,69 @@ Delay: 9.480ns (data path - clock path skew + uncertainty) Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.120ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X13Y172.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X11Y167.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X8Y162.F3 net (fanout=9) 1.362 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X8Y162.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X4Y154.G4 net (fanout=9) 1.085 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X4Y154.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 + SLICE_X5Y154.CE net (fanout=1) 0.429 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X5Y154.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + ------------------------------------------------- --------------------------- + Total 2.602ns (1.088ns logic, 1.514ns route) + (41.8% logic, 58.2% route) + +-------------------------------------------------------------------------------- +Delay: 8.894ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) + Data Path Delay: 2.328ns (Levels of Logic = 2) + Clock Path Skew: -6.322ns (-2.409 - 3.913) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y176.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X10Y162.F2 net (fanout=20) 1.171 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X10Y162.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X7Y162.F1 net (fanout=1) 0.808 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X7Y162.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + SLICE_X11Y162.F1 net (fanout=1) 0.387 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X11Y162.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 ------------------------------------------------- --------------------------- - Total 2.940ns (0.770ns logic, 2.170ns route) - (26.2% logic, 73.8% route) + Total 2.328ns (0.770ns logic, 1.558ns route) + (33.1% logic, 66.9% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%; - 12615 paths analyzed, 692 endpoints analyzed, 0 failing endpoints + 12615 paths analyzed, 693 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.891ns. + Minimum period is 7.614ns. -------------------------------------------------------------------------------- -Slack: 0.109ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_char_gen/char_draw_en (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_red_0 (FF) +Slack: 0.386ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF) + Destination: inst_vga_frontend/inst_vga_backend/Result<5>1_FRB (FF) Requirement: 8.000ns - Data Path Delay: 7.756ns (Levels of Logic = 2) + Data Path Delay: 7.479ns (Levels of Logic = 5) Clock Path Skew: 0.000ns Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns @@ -525,31 +544,40 @@ Slack: 0.109ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_char_gen/char_draw_en to inst_vga_frontend/inst_vga_backend/vga_red_0 + Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<5>1_FRB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X62Y105.YQ Tcko 0.360 inst_vga_frontend/inst_char_gen/char_draw_en - inst_vga_frontend/inst_char_gen/char_draw_en - SLICE_X64Y129.G3 net (fanout=25) 1.143 inst_vga_frontend/inst_char_gen/char_draw_en - SLICE_X64Y129.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>13 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<0>11 - SLICE_X44Y98.F1 net (fanout=24) 3.269 inst_vga_frontend/inst_vga_backend/N6 - SLICE_X44Y98.X Tilo 0.195 inst_vga_frontend/blit_dimx_src_1<25> - inst_vga_frontend/inst_vga_backend/vga_red_mux0003<0>13 - OLOGIC_X0Y97.D1 net (fanout=1) 1.967 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<0>13 - OLOGIC_X0Y97.CLK Todck 0.627 inst_vga_frontend/inst_vga_backend/vga_red<0> - inst_vga_frontend/inst_vga_backend/vga_red_0 + SLICE_X60Y177.YQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7> + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 + SLICE_X55Y173.F4 net (fanout=2) 1.037 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7> + SLICE_X55Y173.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3> + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311 + SLICE_X54Y173.BX net (fanout=3) 0.154 inst_vga_frontend/inst_vga_backend/N13 + SLICE_X54Y173.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/N15 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5 + SLICE_X54Y171.BX net (fanout=3) 0.827 inst_vga_frontend/inst_vga_backend/N15 + SLICE_X54Y171.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5 + SLICE_X54Y170.G1 net (fanout=1) 0.587 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111 + SLICE_X54Y170.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129 + SLICE_X54Y172.G1 net (fanout=2) 0.568 inst_vga_frontend/inst_vga_backend/N11 + SLICE_X54Y172.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001 + SLICE_X60Y179.SR net (fanout=14) 1.179 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000 + SLICE_X60Y179.CLK Tsrck 1.157 inst_vga_frontend/inst_vga_backend/Result<5>1_FRB + inst_vga_frontend/inst_vga_backend/Result<5>1_FRB ------------------------------------------------- --------------------------- - Total 7.756ns (1.377ns logic, 6.379ns route) - (17.8% logic, 82.2% route) + Total 7.479ns (3.127ns logic, 4.352ns route) + (41.8% logic, 58.2% route) -------------------------------------------------------------------------------- -Slack: 0.141ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_char_gen/char_draw_en (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_red_2 (FF) +Slack: 0.496ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF) + Destination: inst_vga_frontend/inst_vga_backend/Result<4>1_FRB (FF) Requirement: 8.000ns - Data Path Delay: 7.724ns (Levels of Logic = 2) + Data Path Delay: 7.369ns (Levels of Logic = 5) Clock Path Skew: 0.000ns Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns @@ -561,32 +589,41 @@ Slack: 0.141ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_char_gen/char_draw_en to inst_vga_frontend/inst_vga_backend/vga_red_2 + Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<4>1_FRB Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X62Y105.YQ Tcko 0.360 inst_vga_frontend/inst_char_gen/char_draw_en - inst_vga_frontend/inst_char_gen/char_draw_en - SLICE_X64Y129.G3 net (fanout=25) 1.143 inst_vga_frontend/inst_char_gen/char_draw_en - SLICE_X64Y129.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>13 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<0>11 - SLICE_X39Y99.G4 net (fanout=24) 3.281 inst_vga_frontend/inst_vga_backend/N6 - SLICE_X39Y99.Y Tilo 0.194 MDAT_O<44> - inst_vga_frontend/inst_vga_backend/vga_red_mux0003<2>13 - OLOGIC_X0Y99.D1 net (fanout=1) 1.924 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<2>13 - OLOGIC_X0Y99.CLK Todck 0.627 inst_vga_frontend/inst_vga_backend/vga_red<2> - inst_vga_frontend/inst_vga_backend/vga_red_2 + SLICE_X60Y177.YQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7> + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 + SLICE_X55Y173.F4 net (fanout=2) 1.037 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7> + SLICE_X55Y173.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3> + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311 + SLICE_X54Y173.BX net (fanout=3) 0.154 inst_vga_frontend/inst_vga_backend/N13 + SLICE_X54Y173.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/N15 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5 + SLICE_X54Y171.BX net (fanout=3) 0.827 inst_vga_frontend/inst_vga_backend/N15 + SLICE_X54Y171.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5 + SLICE_X54Y170.G1 net (fanout=1) 0.587 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111 + SLICE_X54Y170.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129 + SLICE_X54Y172.G1 net (fanout=2) 0.568 inst_vga_frontend/inst_vga_backend/N11 + SLICE_X54Y172.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001 + SLICE_X59Y178.SR net (fanout=14) 1.189 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000 + SLICE_X59Y178.CLK Tsrck 1.037 inst_vga_frontend/inst_vga_backend/Result<4>1_FRB + inst_vga_frontend/inst_vga_backend/Result<4>1_FRB ------------------------------------------------- --------------------------- - Total 7.724ns (1.376ns logic, 6.348ns route) - (17.8% logic, 82.2% route) + Total 7.369ns (3.007ns logic, 4.362ns route) + (40.8% logic, 59.2% route) -------------------------------------------------------------------------------- -Slack: 0.199ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_blue_2 (FF) +Slack: 0.505ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) Requirement: 8.000ns - Data Path Delay: 7.666ns (Levels of Logic = 1) - Clock Path Skew: 0.000ns + Data Path Delay: 7.156ns (Levels of Logic = 7) + Clock Path Skew: -0.204ns (2.503 - 2.707) Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -597,21 +634,44 @@ Slack: 0.199ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 to inst_vga_frontend/inst_vga_backend/vga_blue_2 + Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X73Y112.XQ Tcko 0.340 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - SLICE_X56Y131.G2 net (fanout=8) 1.941 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 - SLICE_X56Y131.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/stat_scan_inv - inst_vga_frontend/inst_vga_backend/stat_scan_inv1 - OLOGIC_X0Y105.SR net (fanout=24) 3.893 inst_vga_frontend/inst_vga_backend/stat_scan_inv - OLOGIC_X0Y105.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<2> - inst_vga_frontend/inst_vga_backend/vga_blue_2 + SLICE_X56Y157.XQ Tcko 0.360 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 + SLICE_X57Y156.G3 net (fanout=3) 0.633 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1> + SLICE_X57Y156.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>_rt + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X57Y157.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X57Y157.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X57Y158.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X57Y158.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + SLICE_X57Y159.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + SLICE_X57Y159.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<6> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + SLICE_X57Y160.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + SLICE_X57Y160.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<8> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9> + SLICE_X57Y161.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9> + SLICE_X57Y161.XMUX Tcinx 0.438 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<11> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<10> + SLICE_X57Y153.G4 net (fanout=1) 0.728 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<10> + SLICE_X57Y153.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<9> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<10>1 + RAMB16_X4Y13.ADDRB13 net (fanout=10) 3.474 inst_vga_frontend/inst_linefifo/ptr_r<10> + RAMB16_X4Y13.CLKB Trcck_ADDRB 0.426 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 ------------------------------------------------- --------------------------- - Total 7.666ns (1.832ns logic, 5.834ns route) - (23.9% logic, 76.1% route) + Total 7.156ns (2.321ns logic, 4.835ns route) + (32.4% logic, 67.6% route) -------------------------------------------------------------------------------- @@ -621,42 +681,10 @@ Timing constraint: PATH "TS_unrelate_VGA_path" TIG; 64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 6.296ns (data path - clock path skew + uncertainty) - Source: inst_vga_frontend/cg_color_2_6 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_blue_6 (FF) - Data Path Delay: 5.755ns (Levels of Logic = 1) - Clock Path Skew: 0.000ns - Source Clock: CLK_O rising - Destination Clock: vga_clk rising - Clock Uncertainty: 0.541ns - - Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.347ns - Phase Error (PE): 0.367ns - - Maximum Data Path: inst_vga_frontend/cg_color_2_6 to inst_vga_frontend/inst_vga_backend/vga_blue_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X48Y110.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_6 - inst_vga_frontend/cg_color_2_6 - SLICE_X67Y140.G1 net (fanout=2) 2.063 inst_vga_frontend/cg_color_2_6 - SLICE_X67Y140.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 - OLOGIC_X2Y172.REV net (fanout=1) 1.841 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 - OLOGIC_X2Y172.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<6> - inst_vga_frontend/inst_vga_backend/vga_blue_6 - ------------------------------------------------- --------------------------- - Total 5.755ns (1.851ns logic, 3.904ns route) - (32.2% logic, 67.8% route) - --------------------------------------------------------------------------------- -Delay: 6.118ns (data path - clock path skew + uncertainty) +Delay: 6.138ns (data path - clock path skew + uncertainty) Source: inst_vga_frontend/cg_color_2_5 (FF) Destination: inst_vga_frontend/inst_vga_backend/vga_blue_5 (FF) - Data Path Delay: 5.577ns (Levels of Logic = 1) + Data Path Delay: 5.597ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -672,23 +700,23 @@ Delay: 6.118ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X52Y110.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_5 + SLICE_X47Y109.YQ Tcko 0.340 inst_vga_frontend/cg_color_2_4 inst_vga_frontend/cg_color_2_5 - SLICE_X67Y150.F3 net (fanout=2) 2.105 inst_vga_frontend/cg_color_2_5 - SLICE_X67Y150.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + SLICE_X65Y142.G1 net (fanout=2) 2.110 inst_vga_frontend/cg_color_2_5 + SLICE_X65Y142.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 - OLOGIC_X2Y171.REV net (fanout=1) 1.621 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + OLOGIC_X2Y171.REV net (fanout=1) 1.656 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 OLOGIC_X2Y171.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<5> inst_vga_frontend/inst_vga_backend/vga_blue_5 ------------------------------------------------- --------------------------- - Total 5.577ns (1.851ns logic, 3.726ns route) - (33.2% logic, 66.8% route) + Total 5.597ns (1.831ns logic, 3.766ns route) + (32.7% logic, 67.3% route) -------------------------------------------------------------------------------- -Delay: 5.925ns (data path - clock path skew + uncertainty) - Source: inst_vga_frontend/cg_color_2_7 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_blue_7 (FF) - Data Path Delay: 5.384ns (Levels of Logic = 1) +Delay: 6.087ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_0_7 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_red_7 (FF) + Data Path Delay: 5.546ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -700,88 +728,69 @@ Delay: 5.925ns (data path - clock path skew + uncertainty) Discrete Jitter (DJ): 0.347ns Phase Error (PE): 0.367ns - Maximum Data Path: inst_vga_frontend/cg_color_2_7 to inst_vga_frontend/inst_vga_backend/vga_blue_7 + Maximum Data Path: inst_vga_frontend/cg_color_0_7 to inst_vga_frontend/inst_vga_backend/vga_red_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X47Y118.YQ Tcko 0.340 inst_vga_frontend/cg_color_2_7 - inst_vga_frontend/cg_color_2_7 - SLICE_X67Y150.G2 net (fanout=2) 2.065 inst_vga_frontend/cg_color_2_7 - SLICE_X67Y150.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 - inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<7>0 - OLOGIC_X2Y173.REV net (fanout=1) 1.488 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<7>0 - OLOGIC_X2Y173.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<7> - inst_vga_frontend/inst_vga_backend/vga_blue_7 + SLICE_X48Y107.XQ Tcko 0.360 inst_vga_frontend/cg_color_0_7 + inst_vga_frontend/cg_color_0_7 + SLICE_X66Y137.G2 net (fanout=2) 2.036 inst_vga_frontend/cg_color_0_7 + SLICE_X66Y137.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0 + inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0 + OLOGIC_X2Y157.REV net (fanout=1) 1.658 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0 + OLOGIC_X2Y157.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_red<7> + inst_vga_frontend/inst_vga_backend/vga_red_7 ------------------------------------------------- --------------------------- - Total 5.384ns (1.831ns logic, 3.553ns route) - (34.0% logic, 66.0% route) + Total 5.546ns (1.852ns logic, 3.694ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Delay: 6.021ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_1_3 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_green_3 (FF) + Data Path Delay: 5.480ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising + Destination Clock: vga_clk rising + Clock Uncertainty: 0.541ns + + Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.347ns + Phase Error (PE): 0.367ns + + Maximum Data Path: inst_vga_frontend/cg_color_1_3 to inst_vga_frontend/inst_vga_backend/vga_green_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X50Y108.YQ Tcko 0.360 inst_vga_frontend/cg_color_1_3 + inst_vga_frontend/cg_color_1_3 + SLICE_X66Y133.G3 net (fanout=2) 2.016 inst_vga_frontend/cg_color_1_3 + SLICE_X66Y133.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0 + inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0 + OLOGIC_X2Y148.REV net (fanout=1) 1.612 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0 + OLOGIC_X2Y148.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_green<3> + inst_vga_frontend/inst_vga_backend/vga_green_3 + ------------------------------------------------- --------------------------- + Total 5.480ns (1.852ns logic, 3.628ns route) + (33.8% logic, 66.2% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%; - 862302 paths analyzed, 11634 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.864ns. + 864692 paths analyzed, 11651 endpoints analyzed, 1 failing endpoint + 1 timing error detected. (1 setup error, 0 hold errors) + Minimum period is 10.294ns. -------------------------------------------------------------------------------- -Slack: 0.018ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) - Destination: inst_mips_top/inst_pipeline/pc.branch_take_2 (FF) - Requirement: 4.950ns - Data Path Delay: 4.777ns (Levels of Logic = 5) - Clock Path Skew: -0.095ns (1.163 - 1.258) - Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk falling at 4.950ns - Clock Uncertainty: 0.060ns - - Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.120ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> - inst_mips_top/inst_pipeline/bcu_op_a_16 - SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> - SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> - SLICE_X26Y15.G4 net (fanout=2) 0.789 inst_mips_top/inst_pipeline/bcu_flags_eq - SLICE_X26Y15.XMUX Tif5x 0.560 inst_mips_top/inst_pipeline/pc.branch_take - inst_mips_top/inst_pipeline/pc_branch_take_mux000267_F - inst_mips_top/inst_pipeline/pc_branch_take_mux000267 - SLICE_X29Y14.BY net (fanout=3) 0.658 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 - SLICE_X29Y14.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 - inst_mips_top/inst_pipeline/pc.branch_take_2 - ------------------------------------------------- --------------------------- - Total 4.777ns (2.093ns logic, 2.684ns route) - (43.8% logic, 56.2% route) - --------------------------------------------------------------------------------- -Slack: 0.018ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) +Slack: -0.197ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_2 (FF) Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF) Requirement: 4.950ns - Data Path Delay: 4.777ns (Levels of Logic = 5) - Clock Path Skew: -0.095ns (1.163 - 1.258) + Data Path Delay: 4.917ns (Levels of Logic = 10) + Clock Path Skew: -0.170ns (2.881 - 3.051) Source Clock: cpu_clk rising at 0.000ns Destination Clock: cpu_clk falling at 4.950ns Clock Uncertainty: 0.060ns @@ -792,47 +801,64 @@ Slack: 0.018ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.120ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_1 + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> - inst_mips_top/inst_pipeline/bcu_op_a_16 - SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> - SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> + SLICE_X8Y30.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<2> + inst_mips_top/inst_pipeline/bcu_op_a_2 + SLICE_X10Y30.G3 net (fanout=1) 0.816 inst_mips_top/inst_pipeline/bcu_op_a<2> + SLICE_X10Y30.COUT Topcyg 0.561 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> + SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 + SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> - SLICE_X26Y15.G4 net (fanout=2) 0.789 inst_mips_top/inst_pipeline/bcu_flags_eq - SLICE_X26Y15.XMUX Tif5x 0.560 inst_mips_top/inst_pipeline/pc.branch_take - inst_mips_top/inst_pipeline/pc_branch_take_mux000267_F - inst_mips_top/inst_pipeline/pc_branch_take_mux000267 - SLICE_X29Y14.BX net (fanout=3) 0.669 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 - SLICE_X29Y14.CLK Tdick 0.331 inst_mips_top/inst_pipeline/pc.branch_take_1 + SLICE_X13Y42.G4 net (fanout=2) 1.015 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X13Y42.Y Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take + _LC_2_0 + SLICE_X13Y42.F3 net (fanout=1) 0.222 _LC_2_0 + SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 inst_mips_top/inst_pipeline/pc.branch_take_1 ------------------------------------------------- --------------------------- - Total 4.777ns (2.082ns logic, 2.695ns route) - (43.6% logic, 56.4% route) + Total 4.917ns (2.274ns logic, 2.643ns route) + (46.2% logic, 53.8% route) -------------------------------------------------------------------------------- -Slack: 0.036ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) - Destination: inst_mips_top/inst_pipeline/pc.branch_take_2 (FF) +Slack: -0.140ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_2 (FF) + Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF) Requirement: 4.950ns - Data Path Delay: 4.759ns (Levels of Logic = 5) - Clock Path Skew: -0.095ns (1.163 - 1.258) + Data Path Delay: 4.860ns (Levels of Logic = 10) + Clock Path Skew: -0.170ns (2.881 - 3.051) Source Clock: cpu_clk rising at 0.000ns Destination Clock: cpu_clk falling at 4.950ns Clock Uncertainty: 0.060ns @@ -843,39 +869,125 @@ Slack: 0.036ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.120ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_2 + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> - inst_mips_top/inst_pipeline/bcu_op_a_16 - SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> - SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 - inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> + SLICE_X8Y30.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<2> + inst_mips_top/inst_pipeline/bcu_op_a_2 + SLICE_X10Y30.G3 net (fanout=1) 0.816 inst_mips_top/inst_pipeline/bcu_op_a<2> + SLICE_X10Y30.COUT Topcyg 0.561 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> - SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> - SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> + SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> - SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 + SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> - SLICE_X26Y15.F4 net (fanout=2) 0.776 inst_mips_top/inst_pipeline/bcu_flags_eq - SLICE_X26Y15.XMUX Tif5x 0.555 inst_mips_top/inst_pipeline/pc.branch_take - inst_mips_top/inst_pipeline/pc_branch_take_mux000267_G - inst_mips_top/inst_pipeline/pc_branch_take_mux000267 - SLICE_X29Y14.BY net (fanout=3) 0.658 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 - SLICE_X29Y14.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 - inst_mips_top/inst_pipeline/pc.branch_take_2 + SLICE_X13Y39.F4 net (fanout=2) 0.836 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X13Y39.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_branch_take_mux000240 + inst_mips_top/inst_pipeline/pc_branch_take_mux000240 + SLICE_X13Y42.F4 net (fanout=1) 0.344 inst_mips_top/inst_pipeline/pc_branch_take_mux000240 + SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 + inst_mips_top/inst_pipeline/pc.branch_take_1 ------------------------------------------------- --------------------------- - Total 4.759ns (2.088ns logic, 2.671ns route) - (43.9% logic, 56.1% route) + Total 4.860ns (2.274ns logic, 2.586ns route) + (46.8% logic, 53.2% route) + +-------------------------------------------------------------------------------- +Slack: -0.073ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_0 (FF) + Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF) + Requirement: 4.950ns + Data Path Delay: 4.793ns (Levels of Logic = 10) + Clock Path Skew: -0.170ns (2.881 - 3.051) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk falling at 4.950ns + Clock Uncertainty: 0.060ns + + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_0 to inst_mips_top/inst_pipeline/pc.branch_take_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y30.YQ Tcko 0.340 inst_mips_top/inst_pipeline/bcu_op_b<13> + inst_mips_top/inst_pipeline/bcu_op_a_0 + SLICE_X10Y30.F2 net (fanout=1) 0.697 inst_mips_top/inst_pipeline/bcu_op_a<0> + SLICE_X10Y30.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<0> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<0> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1> + SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3> + SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5> + SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7> + SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> + SLICE_X13Y42.G4 net (fanout=2) 1.015 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X13Y42.Y Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take + _LC_2_0 + SLICE_X13Y42.F3 net (fanout=1) 0.222 _LC_2_0 + SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 + inst_mips_top/inst_pipeline/pc.branch_take_1 + ------------------------------------------------- --------------------------- + Total 4.793ns (2.269ns logic, 2.524ns route) + (47.3% logic, 52.7% route) -------------------------------------------------------------------------------- @@ -884,13 +996,13 @@ Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%; 787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 4.689ns. + Minimum period is 5.284ns. -------------------------------------------------------------------------------- -Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) +Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) Destination: inst_ac97_wb/inst_ac_io/cnt_7 (FF) Requirement: 80.000ns - Data Path Delay: 4.580ns (Levels of Logic = 4) + Data Path Delay: 5.175ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -902,37 +1014,37 @@ Slack: 75.311ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_7 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> - inst_ac97_wb/inst_ac_io/cnt_6 - SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> - SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 - SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018 + SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9 + SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X55Y12.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X55Y12.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<6> + SLICE_X65Y26.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X65Y26.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<6> inst_ac97_wb/inst_ac_io/cnt_7 ------------------------------------------------- --------------------------- - Total 4.580ns (1.670ns logic, 2.910ns route) - (36.5% logic, 63.5% route) + Total 5.175ns (1.672ns logic, 3.503ns route) + (32.3% logic, 67.7% route) -------------------------------------------------------------------------------- -Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) +Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) Requirement: 80.000ns - Data Path Delay: 4.580ns (Levels of Logic = 4) + Data Path Delay: 5.175ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -944,37 +1056,37 @@ Slack: 75.311ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_9 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> - inst_ac97_wb/inst_ac_io/cnt_6 - SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> - SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 - SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018 + SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9 + SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X55Y13.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X55Y13.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> + SLICE_X65Y27.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X65Y27.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> inst_ac97_wb/inst_ac_io/cnt_9 ------------------------------------------------- --------------------------- - Total 4.580ns (1.670ns logic, 2.910ns route) - (36.5% logic, 63.5% route) + Total 5.175ns (1.672ns logic, 3.503ns route) + (32.3% logic, 67.7% route) -------------------------------------------------------------------------------- -Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) +Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) Destination: inst_ac97_wb/inst_ac_io/cnt_8 (FF) Requirement: 80.000ns - Data Path Delay: 4.580ns (Levels of Logic = 4) + Data Path Delay: 5.175ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -986,35 +1098,35 @@ Slack: 75.311ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_8 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> - inst_ac97_wb/inst_ac_io/cnt_6 - SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> - SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 - SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018 + SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9 + SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X55Y13.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X55Y13.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> + SLICE_X65Y27.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X65Y27.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> inst_ac97_wb/inst_ac_io/cnt_8 ------------------------------------------------- --------------------------- - Total 4.580ns (1.670ns logic, 2.910ns route) - (36.5% logic, 63.5% route) + Total 5.175ns (1.672ns logic, 3.503ns route) + (32.3% logic, 67.7% route) -------------------------------------------------------------------------------- -All constraints were met. +2 constraints not met. Data Sheet report: @@ -1026,7 +1138,7 @@ Clock to Setup on destination clock sys_ac97_bit_clk | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -sys_ac97_bit_clk| 7.481| 4.104| | 3.221| +sys_ac97_bit_clk| 6.390| 3.350| | 2.174| ----------------+---------+---------+---------+---------+ Clock to Setup on destination clock sys_clk_in @@ -1034,25 +1146,25 @@ Clock to Setup on destination clock sys_clk_in | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ -sys_clk_in | 9.851| 4.837| 4.932| 3.398| +sys_clk_in | 10.193| 4.880| 5.147| 3.200| ---------------+---------+---------+---------+---------+ Timing summary: --------------- -Timing errors: 0 Score: 0 +Timing errors: 10 Score: 1304 -Constraints cover 1331680 paths, 0 nets, and 42800 connections +Constraints cover 1334002 paths, 0 nets, and 42582 connections Design statistics: - Minimum period: 9.864ns{1} (Maximum frequency: 101.379MHz) + Minimum period: 10.294ns{1} (Maximum frequency: 97.144MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Sun Feb 14 18:17:22 2010 +Analysis completed Tue Mar 09 13:11:34 2010 -------------------------------------------------------------------------------- Trace Settings: diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp index d86ce62..7ea5658 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -10,28 +10,27 @@ Target Device : xc4vsx35 Target Package : ff668 Target Speed : -10 Stepping Level : ES -Mapper Version : virtex4 -- $Revision: 1.4 $ -Mapped Date : Sun Feb 14 18:06:35 2010 +Mapper Version : virtex4 -- $Revision: 1.5 $ +Mapped Date : Tue Mar 09 12:59:05 2010 Design Summary -------------- Number of errors: 0 Number of warnings: 68 Logic Utilization: - Number of Slice Flip Flops: 5,411 out of 30,720 17% - Number of 4 input LUTs: 8,647 out of 30,720 28% + Number of Slice Flip Flops: 5,422 out of 30,720 17% + Number of 4 input LUTs: 8,643 out of 30,720 28% Logic Distribution: - Number of occupied Slices: 6,008 out of 15,360 39% - Number of Slices containing only related logic: 6,008 out of 6,008 100% - Number of Slices containing unrelated logic: 0 out of 6,008 0% + Number of occupied Slices: 5,907 out of 15,360 38% + Number of Slices containing only related logic: 5,907 out of 5,907 100% + Number of Slices containing unrelated logic: 0 out of 5,907 0% *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 9,036 out of 30,720 29% - Number used as logic: 7,647 + Total Number of 4 input LUTs: 9,032 out of 30,720 29% + Number used as logic: 7,643 Number used as a route-thru: 389 - Number used as 16x1 RAMs: 6 Number used for Dual Port RAMs: 792 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 202 + Number used as Shift registers: 208 Number of bonded IOBs: 226 out of 448 50% IOB Flip Flops: 350 IOB Dual-Data Rate Flops: 42 @@ -42,9 +41,9 @@ Logic Distribution: Number of DCM_ADVs: 4 out of 8 50% Number of BSCAN_VIRTEX4s: 1 out of 4 25% -Peak Memory Usage: 533 MB -Total REAL time to MAP completion: 8 mins 4 secs -Total CPU time to MAP completion: 7 mins 55 secs +Peak Memory Usage: 530 MB +Total REAL time to MAP completion: 8 mins 27 secs +Total CPU time to MAP completion: 8 mins 9 secs Table of Contents ----------------- @@ -542,6 +541,9 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) +INFO:Pack:1679 - FLOP symbol "inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0" (Output Signal = + inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0) was replicated from FLOP symbol + "inst_mips_top/inst_pipeline/EX_stage.reg_b_3" (Output Signal = inst_mips_top/inst_pipeline/EX_stage.reg_b_3) INFO:Pack:1650 - Map created a placed design. INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet. @@ -1496,17 +1498,16 @@ Area Group "AG_inst_mips_top" RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X 3Y0:RAMB16_X3Y6 Area Group Logic Utilization: - Number of Slice Flip Flops: 1,951 out of 4,320 45% + Number of Slice Flip Flops: 1,962 out of 4,320 45% Logic Distribution: Number of occupied Slices: 2,157 out of 2,160 99% Number of Slices containing only related logic: 2,157 out of 2,157 100% - Total Number of 4 input LUTs: 4,308 out of 4,320 99% - Number used as logic: 3,648 + Total Number of 4 input LUTs: 4,309 out of 4,320 99% + Number used as logic: 3,649 Number used as route-thru: 49 - Number used as 16x1 RAMs: 2 Number used as Dual Port RAMs: 586 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 23 + Number used as Shift registers: 25 Number of Block RAMs: 27 out of 28 96% @@ -1539,34 +1540,34 @@ Section 14 - Utilization by Hierarchy +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| mips_sys/ | | 1395/8308 | 28/5411 | 849/9036 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | -| +inst_ac97_wb | | 183/796 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | -| ++inst_ac_io | | 20/574 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | -| +++inst_ac_in | | 261/265 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | -| ++++singleshot_inst1 | | 2/2 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | -| ++++singleshot_inst2 | | 2/2 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | -| +++inst_ac_out | | 286/289 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | +| mips_sys/ | | 1376/8103 | 28/5422 | 845/9032 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | +| +inst_ac97_wb | | 181/823 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | +| ++inst_ac_io | | 21/598 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | +| +++inst_ac_in | | 254/260 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | +| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | +| ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | +| +++inst_ac_out | | 314/317 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | | ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 | -| ++inst_tx_fifo | | 1/39 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | +| ++inst_tx_fifo | | 1/44 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 38/38 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | -| +inst_clockgen | | 44/50 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | +| +++inst_fifo_sync_ctrl | | 43/43 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | +| +inst_clockgen | | 41/47 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | | ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 | | ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 | | ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 | | ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 | | ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 | | ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 | -| +inst_flash_port | | 80/80 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | -| +inst_gpio_wb | | 301/301 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | -| +inst_mips_top | | 26/2930 | 22/1950 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | +| +inst_flash_port | | 81/81 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | +| +inst_gpio_wb | | 285/285 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | +| +inst_mips_top | | 23/2822 | 22/1961 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | | ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 | | ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 | | ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 | -| ++inst_biu | | 191/816 | 97/561 | 210/926 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | -| +++inst_bin_fifo | | 2/97 | 0/62 | 2/106 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | +| ++inst_biu | | 177/800 | 97/570 | 211/936 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | +| +++inst_bin_fifo | | 2/100 | 0/62 | 2/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | | ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 12/38 | 12/30 | 6/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | +| ++++inst_fifo_async_ctrl | | 13/41 | 12/30 | 6/41 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1577,11 +1578,11 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_r | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | +++++inst_gray_counter_w | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_bout_fifo | | 6/150 | 0/97 | 6/177 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | -| ++++inst_dpram_1w1r | | 105/105 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 10/39 | 12/30 | 3/37 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | +| +++inst_bout_fifo | | 3/146 | 0/97 | 3/179 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | +| ++++inst_dpram_1w1r | | 102/102 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 12/41 | 12/30 | 6/42 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1592,9 +1593,9 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 9/9 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_r | | 9/9 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | +++++inst_gray_counter_w | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_dcache | | 174/174 | 147/147 | 149/149 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | +| +++inst_dcache | | 172/172 | 156/156 | 155/155 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | | ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram | | ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram | | ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram | @@ -1603,35 +1604,35 @@ Section 14 - Utilization by Hierarchy | +++inst_icache | | 117/117 | 81/81 | 123/123 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | | ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram | | ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram | -| +++inst_write_fifo | | 2/87 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | +| +++inst_write_fifo | | 2/88 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | | ++++inst_dpram_1w1r | | 66/66 | 66/66 | 132/132 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | -| ++++inst_fifo_sync_ctrl | | 19/19 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | -| ++inst_cop | | 239/239 | 190/190 | 237/237 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | -| ++inst_pipeline | | 921/1846 | 650/1177 | 1386/3044 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | -| +++inst_alu | | 62/62 | 0/0 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | +| ++++inst_fifo_sync_ctrl | | 20/20 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | +| ++inst_cop | | 219/219 | 190/190 | 234/234 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | +| ++inst_pipeline | | 880/1777 | 651/1179 | 1380/3037 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | +| +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | | +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu | -| +++inst_muldiv | | 572/572 | 527/527 | 1027/1027 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | +| +++inst_muldiv | | 554/554 | 527/527 | 1028/1028 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | | +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual | -| +++inst_shifter | | 155/155 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | -| +inst_ps2_phy_0 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | -| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | +| +++inst_shifter | | 144/144 | 0/0 | 238/238 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | +| +inst_ps2_phy_0 | | 0/10 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | +| ++Inst_debounce_clk | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | | ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | | +inst_ps2_phy_1 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | -| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | -| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | -| +inst_ps2_wb_0 | | 35/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | -| ++inst_ps2_core | | 122/122 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | -| +inst_ps2_wb_1 | | 32/150 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | -| ++inst_ps2_core | | 118/118 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | -| +inst_rom_wb | | 1/76 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | -| ++inst_rom | | 75/75 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | -| +inst_sdram_ctrl_frontend_wb | | 110/669 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | -| ++inst_cat_fifo | | 2/17 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | +| ++Inst_debounce_clk | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | +| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | +| +inst_ps2_wb_0 | | 33/159 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | +| ++inst_ps2_core | | 126/126 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | +| +inst_ps2_wb_1 | | 33/146 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | +| ++inst_ps2_core | | 113/113 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | +| +inst_rom_wb | | 1/77 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | +| ++inst_rom | | 76/76 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | +| +inst_sdram_ctrl_frontend_wb | | 100/629 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | +| ++inst_cat_fifo | | 2/15 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 15/15 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | -| ++inst_read_fifo | | 2/54 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | +| +++inst_fifo_sync_ctrl | | 13/13 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | +| ++inst_read_fifo | | 2/50 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 17/48 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1644,14 +1645,14 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_sdram_ctrl | | 0/433 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | -| +++inst_ddr_phy | | 179/180 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | +| ++++inst_gray_counter_r | | 9/9 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_sdram_ctrl | | 0/410 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | +| +++inst_ddr_phy | | 167/168 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | | ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 | -| +++inst_sd_cmd_fifo | | 4/64 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | +| +++inst_sd_cmd_fifo | | 4/61 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | | ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 21/60 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | +| ++++inst_fifo_async_ctrl | | 19/57 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1667,12 +1668,12 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_p2_3_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1 | | +++++Mshreg_p2_3_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2 | | +++++inst_gray_counter_r | | 14/14 | 13/13 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_sdram_cmd | | 46/46 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | -| +++inst_sdram_ctrl | | 143/143 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | -| ++inst_write_fifo | | 3/55 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | +| +++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_sdram_cmd | | 47/47 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | +| +++inst_sdram_ctrl | | 134/134 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | +| ++inst_write_fifo | | 3/54 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 19/52 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1687,29 +1688,29 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | | ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +inst_uart_wb_0 | | 59/105 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | -| ++inst_uart_rx | | 0/29 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | +| +inst_uart_wb_0 | | 61/109 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | +| ++inst_uart_rx | | 0/30 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf | -| +++kcuart | | 21/21 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | +| +++kcuart | | 22/22 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/18 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf | -| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | -| +inst_uart_wb_1 | | 56/103 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | +| +++kcuart | | 10/10 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | +| +inst_uart_wb_1 | | 60/107 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | | ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf | | +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | | ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf | | +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | -| +inst_usb_port | | 37/37 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | -| +inst_vga_frontend | | 802/1436 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | +| +inst_usb_port | | 36/36 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | +| +inst_vga_frontend | | 762/1384 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | | ++inst_blitfifo | | 4/31 | 0/23 | 4/45 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r | | +++inst_fifo_sync_ctrl | | 27/27 | 23/23 | 41/41 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | -| ++inst_bus_fifo | | 3/116 | 0/110 | 3/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | +| ++inst_bus_fifo | | 4/115 | 0/110 | 4/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | | +++inst_dpram_1w1r | | 103/103 | 103/103 | 206/206 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 10/10 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | -| ++inst_char_gen | | 194/206 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | +| +++inst_fifo_sync_ctrl | | 8/8 | 7/7 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | +| ++inst_char_gen | | 202/214 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | | +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 | | +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 | | +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 | @@ -1724,9 +1725,9 @@ Section 14 - Utilization by Hierarchy | +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 | | +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram | | +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom | -| ++inst_linefifo | | 2/178 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | +| ++inst_linefifo | | 2/161 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 83/176 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 72/159 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | | ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 | | ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 | | ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 | @@ -1774,11 +1775,11 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 | | ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 | | ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 27/27 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_vga_backend | | 61/103 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | -| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | -| ++++inst_vga_sync_h | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | -| ++++inst_vga_sync_v | | 22/22 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +| ++++inst_gray_counter_w | | 21/21 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_vga_backend | | 61/101 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | +| +++inst_vga_timing | | 0/40 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | +| ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | +| ++++inst_vga_sync_v | | 19/19 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slices can be packed with basic elements from multiple hierarchies.