jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

update

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@782 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-13 10:50:30 +00:00
parent 874df39347
commit e27c0f791a
4 changed files with 861 additions and 731 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/ise101/mips_sys/mips_sys.par
+65 -50
View File
@@ -1,7 +1,7 @@
Release 10.1.03 par K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
JUPITER:: Sun Feb 14 18:14:54 2010
JUPITER:: Tue Mar 09 13:07:50 2010
par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
@@ -31,8 +31,8 @@ Device Utilization Summary:
Number of OLOGICs 182 out of 448 40%
Number of RAMB16s 51 out of 192 26%
Number of Slices 6008 out of 15360 39%
Number of SLICEMs 558 out of 7680 7%
Number of Slices 5907 out of 15360 38%
Number of SLICEMs 543 out of 7680 7%
@@ -40,42 +40,44 @@ Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1: 48218 unrouted; REAL time: 15 secs
Phase 1: 47928 unrouted; REAL time: 16 secs
Phase 2: 41114 unrouted; REAL time: 16 secs
Phase 2: 40960 unrouted; REAL time: 17 secs
Phase 3: 15775 unrouted; REAL time: 22 secs
Phase 3: 15655 unrouted; REAL time: 24 secs
Phase 4: 15775 unrouted; (290927) REAL time: 23 secs
Phase 4: 15655 unrouted; (245197) REAL time: 24 secs
Phase 5: 16549 unrouted; (7681) REAL time: 26 secs
Phase 5: 16281 unrouted; (4341) REAL time: 27 secs
Phase 6: 16600 unrouted; (0) REAL time: 26 secs
Phase 6: 16339 unrouted; (710) REAL time: 28 secs
Phase 7: 0 unrouted; (942) REAL time: 53 secs
Phase 7: 0 unrouted; (9891) REAL time: 53 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 8: 0 unrouted; (942) REAL time: 1 mins 14 secs
Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs
Phase 9: 0 unrouted; (942) REAL time: 1 mins 20 secs
Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs
Phase 10: 0 unrouted; (0) REAL time: 1 mins 26 secs
Phase 11: 0 unrouted; (0) REAL time: 1 mins 27 secs
Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 12: 0 unrouted; (0) REAL time: 1 mins 46 secs
Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs
Phase 13: 0 unrouted; (0) REAL time: 1 mins 52 secs
Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs
Total REAL time to Router completion: 1 mins 54 secs
Total CPU time to Router completion: 1 mins 49 secs
Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs
Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs
Total REAL time to Router completion: 3 mins 9 secs
Total CPU time to Router completion: 3 mins 3 secs
Partition Implementation Status
-------------------------------
@@ -93,28 +95,28 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y12| No | 1638 | 0.443 | 4.049 |
| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 |
+---------------------+--------------+------+------+------------+-------------+
| CLK_O | BUFGCTRL_X0Y2| No | 2331 | 0.533 | 3.922 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.287 | 3.881 |
| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 | BUFGCTRL_X0Y0| No | 75 | 0.416 | 3.851 |
| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y31| No | 241 | 0.494 | 3.933 |
| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 |
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F | BUFGCTRL_X0Y8| No | 251 | 0.356 | 3.903 |
| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 62 | 0.223 | 3.686 |
| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y16| No | 65 | 0.160 | 3.932 |
| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.146 | 3.628 |
| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@@ -122,7 +124,20 @@ only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
Timing Score: 1304
WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and select
the "Timing Improvement Wizard" link for suggestions to correct each problem.
Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
@@ -133,31 +148,31 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.018ns| 9.864ns| 0| 0
ns HIGH 50% | HOLD | 0.314ns| | 0| 0
* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107
HIGH 50% | HOLD | 0.365ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.054ns| 7.392ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.518ns| | 0| 0
* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197
ns HIGH 50% | HOLD | 0.346ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.109ns| 7.891ns| 0| 0
s HIGH 50% | HOLD | 0.480ns| | 0| 0
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.166ns| 9.734ns| 0| 0
HIGH 50% | HOLD | 0.333ns| | 0| 0
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0
s HIGH 50% | HOLD | 0.514ns| | 0| 0
------------------------------------------------------------------------------------------------------
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.896ns| 8.208ns| 0| 0
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0
ns HIGH 50% | HOLD | 0.518ns| | 0| 0
------------------------------------------------------------------------------------------------------
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.311ns| 4.689ns| 0| 0
ns HIGH 50% | HOLD | 0.783ns| | 0| 0
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0
ns HIGH 50% | HOLD | 0.802ns| | 0| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.588ns| N/A| 0
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.296ns| N/A| 0
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
@@ -166,17 +181,17 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 2 mins 3 secs
Total CPU time to PAR completion: 1 mins 55 secs
Total REAL time to PAR completion: 3 mins 18 secs
Total CPU time to PAR completion: 3 mins 9 secs
Peak Memory Usage: 453 MB
Peak Memory Usage: 428 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Timing: Completed - 10 errors found.
Number of error messages: 0
Number of warning messages: 0
Number of warning messages: 1
Number of info messages: 1
Writing design to file mips_sys.ncd
projects/mips_sys/ise101/mips_sys/mips_sys.syr
+32 -30
View File
@@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.13 secs
--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.13 secs
--> Reading design: mips_sys.prj
@@ -271,7 +271,8 @@ Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <
data_width = 16
f_sysclk = 100.000000
Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>).
Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>) with generics.
simulate_tx = false
Analyzing hierarchy for entity <clockgen> in library <work> (architecture <tech>) with generics.
clk_in_freq = 100.000000
@@ -688,7 +689,8 @@ Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <beha
f_sysclk = 100.000000
Entity <async_port_wb.2> analyzed. Unit <async_port_wb.2> generated.
Analyzing Entity <uart_wb> in library <work> (Architecture <behavior>).
Analyzing generic Entity <uart_wb> in library <work> (Architecture <behavior>).
simulate_tx = false
INFO:Xst:2679 - Register <DAT_O<31>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<30>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DAT_O<29>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
@@ -2654,7 +2656,7 @@ WARNING:Xst:646 - Signal <tx_complete> is assigned but never used. This unconnec
Found 16-bit register for signal <DAT_O<15:0>>.
Found 1-bit register for signal <ACK_O>.
Found 16-bit up counter for signal <baud_count>.
Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 146.
Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 162.
Found 1-bit register for signal <en_16_x_baud>.
Found 1-bit register for signal <irq_rx>.
Found 1-bit register for signal <irq_tx>.
@@ -4902,28 +4904,28 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_18) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/was_write) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_4) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift18) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_4)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_8) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_ps2_phy_1/Inst_debounce_data/count_2) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_6) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_1) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift1) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_3) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift17) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
Timing Summary:
---------------
@@ -5212,12 +5214,12 @@ Delay: 10.288ns (Levels of Logic = 11)
=========================================================================
Total REAL time to Xst completion: 126.00 secs
Total CPU time to Xst completion: 126.49 secs
Total REAL time to Xst completion: 128.00 secs
Total CPU time to Xst completion: 128.61 secs
-->
Total memory usage is 371060 kilobytes
Total memory usage is 357364 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1003 ( 0 filtered)
projects/mips_sys/ise101/mips_sys/mips_sys.twr
+671 -559
View File
File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
+93 -92
View File
@@ -10,28 +10,27 @@ Target Device : xc4vsx35
Target Package : ff668
Target Speed : -10
Stepping Level : ES
Mapper Version : virtex4 -- $Revision: 1.4 $
Mapped Date : Sun Feb 14 18:06:35 2010
Mapper Version : virtex4 -- $Revision: 1.5 $
Mapped Date : Tue Mar 09 12:59:05 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 68
Logic Utilization:
Number of Slice Flip Flops: 5,411 out of 30,720 17%
Number of 4 input LUTs: 8,647 out of 30,720 28%
Number of Slice Flip Flops: 5,422 out of 30,720 17%
Number of 4 input LUTs: 8,643 out of 30,720 28%
Logic Distribution:
Number of occupied Slices: 6,008 out of 15,360 39%
Number of Slices containing only related logic: 6,008 out of 6,008 100%
Number of Slices containing unrelated logic: 0 out of 6,008 0%
Number of occupied Slices: 5,907 out of 15,360 38%
Number of Slices containing only related logic: 5,907 out of 5,907 100%
Number of Slices containing unrelated logic: 0 out of 5,907 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 9,036 out of 30,720 29%
Number used as logic: 7,647
Total Number of 4 input LUTs: 9,032 out of 30,720 29%
Number used as logic: 7,643
Number used as a route-thru: 389
Number used as 16x1 RAMs: 6
Number used for Dual Port RAMs: 792
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 202
Number used as Shift registers: 208
Number of bonded IOBs: 226 out of 448 50%
IOB Flip Flops: 350
IOB Dual-Data Rate Flops: 42
@@ -42,9 +41,9 @@ Logic Distribution:
Number of DCM_ADVs: 4 out of 8 50%
Number of BSCAN_VIRTEX4s: 1 out of 4 25%
Peak Memory Usage: 533 MB
Total REAL time to MAP completion: 8 mins 4 secs
Total CPU time to MAP completion: 7 mins 55 secs
Peak Memory Usage: 530 MB
Total REAL time to MAP completion: 8 mins 27 secs
Total CPU time to MAP completion: 8 mins 9 secs
Table of Contents
-----------------
@@ -542,6 +541,9 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Pack:1679 - FLOP symbol "inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0" (Output Signal =
inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0) was replicated from FLOP symbol
"inst_mips_top/inst_pipeline/EX_stage.reg_b_3" (Output Signal = inst_mips_top/inst_pipeline/EX_stage.reg_b_3)
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet.
@@ -1496,17 +1498,16 @@ Area Group "AG_inst_mips_top"
RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X
3Y0:RAMB16_X3Y6
Area Group Logic Utilization:
Number of Slice Flip Flops: 1,951 out of 4,320 45%
Number of Slice Flip Flops: 1,962 out of 4,320 45%
Logic Distribution:
Number of occupied Slices: 2,157 out of 2,160 99%
Number of Slices containing only related logic: 2,157 out of 2,157 100%
Total Number of 4 input LUTs: 4,308 out of 4,320 99%
Number used as logic: 3,648
Total Number of 4 input LUTs: 4,309 out of 4,320 99%
Number used as logic: 3,649
Number used as route-thru: 49
Number used as 16x1 RAMs: 2
Number used as Dual Port RAMs: 586
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 23
Number used as Shift registers: 25
Number of Block RAMs: 27 out of 28 96%
@@ -1539,34 +1540,34 @@ Section 14 - Utilization by Hierarchy
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| mips_sys/ | | 1395/8308 | 28/5411 | 849/9036 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys |
| +inst_ac97_wb | | 183/796 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb |
| ++inst_ac_io | | 20/574 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io |
| +++inst_ac_in | | 261/265 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in |
| ++++singleshot_inst1 | | 2/2 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 |
| ++++singleshot_inst2 | | 2/2 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 |
| +++inst_ac_out | | 286/289 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out |
| mips_sys/ | | 1376/8103 | 28/5422 | 845/9032 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys |
| +inst_ac97_wb | | 181/823 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb |
| ++inst_ac_io | | 21/598 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io |
| +++inst_ac_in | | 254/260 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in |
| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 |
| ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 |
| +++inst_ac_out | | 314/317 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out |
| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 |
| ++inst_tx_fifo | | 1/39 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo |
| ++inst_tx_fifo | | 1/44 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 38/38 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl |
| +inst_clockgen | | 44/50 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen |
| +++inst_fifo_sync_ctrl | | 43/43 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl |
| +inst_clockgen | | 41/47 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen |
| ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 |
| ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 |
| ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 |
| ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 |
| ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 |
| ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 |
| +inst_flash_port | | 80/80 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port |
| +inst_gpio_wb | | 301/301 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb |
| +inst_mips_top | | 26/2930 | 22/1950 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top |
| +inst_flash_port | | 81/81 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port |
| +inst_gpio_wb | | 285/285 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb |
| +inst_mips_top | | 23/2822 | 22/1961 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top |
| ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 |
| ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 |
| ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 |
| ++inst_biu | | 191/816 | 97/561 | 210/926 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu |
| +++inst_bin_fifo | | 2/97 | 0/62 | 2/106 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo |
| ++inst_biu | | 177/800 | 97/570 | 211/936 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu |
| +++inst_bin_fifo | | 2/100 | 0/62 | 2/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo |
| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 12/38 | 12/30 | 6/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl |
| ++++inst_fifo_async_ctrl | | 13/41 | 12/30 | 6/41 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
@@ -1577,11 +1578,11 @@ Section 14 - Utilization by Hierarchy
| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_r | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_bout_fifo | | 6/150 | 0/97 | 6/177 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo |
| ++++inst_dpram_1w1r | | 105/105 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 10/39 | 12/30 | 3/37 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl |
| +++inst_bout_fifo | | 3/146 | 0/97 | 3/179 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo |
| ++++inst_dpram_1w1r | | 102/102 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 12/41 | 12/30 | 6/42 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
@@ -1592,9 +1593,9 @@ Section 14 - Utilization by Hierarchy
| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| +++++inst_gray_counter_r | | 9/9 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_r | | 9/9 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_dcache | | 174/174 | 147/147 | 149/149 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache |
| +++inst_dcache | | 172/172 | 156/156 | 155/155 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache |
| ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram |
| ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram |
| ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram |
@@ -1603,35 +1604,35 @@ Section 14 - Utilization by Hierarchy
| +++inst_icache | | 117/117 | 81/81 | 123/123 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache |
| ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram |
| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram |
| +++inst_write_fifo | | 2/87 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo |
| +++inst_write_fifo | | 2/88 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo |
| ++++inst_dpram_1w1r | | 66/66 | 66/66 | 132/132 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r |
| ++++inst_fifo_sync_ctrl | | 19/19 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl |
| ++inst_cop | | 239/239 | 190/190 | 237/237 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop |
| ++inst_pipeline | | 921/1846 | 650/1177 | 1386/3044 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline |
| +++inst_alu | | 62/62 | 0/0 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu |
| ++++inst_fifo_sync_ctrl | | 20/20 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl |
| ++inst_cop | | 219/219 | 190/190 | 234/234 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop |
| ++inst_pipeline | | 880/1777 | 651/1179 | 1380/3037 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline |
| +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu |
| +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu |
| +++inst_muldiv | | 572/572 | 527/527 | 1027/1027 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv |
| +++inst_muldiv | | 554/554 | 527/527 | 1028/1028 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv |
| +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual |
| +++inst_shifter | | 155/155 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter |
| +inst_ps2_phy_0 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 |
| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk |
| +++inst_shifter | | 144/144 | 0/0 | 238/238 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter |
| +inst_ps2_phy_0 | | 0/10 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 |
| ++Inst_debounce_clk | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk |
| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data |
| +inst_ps2_phy_1 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 |
| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk |
| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data |
| +inst_ps2_wb_0 | | 35/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 |
| ++inst_ps2_core | | 122/122 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core |
| +inst_ps2_wb_1 | | 32/150 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 |
| ++inst_ps2_core | | 118/118 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core |
| +inst_rom_wb | | 1/76 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb |
| ++inst_rom | | 75/75 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom |
| +inst_sdram_ctrl_frontend_wb | | 110/669 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb |
| ++inst_cat_fifo | | 2/17 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo |
| ++Inst_debounce_clk | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk |
| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data |
| +inst_ps2_wb_0 | | 33/159 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 |
| ++inst_ps2_core | | 126/126 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core |
| +inst_ps2_wb_1 | | 33/146 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 |
| ++inst_ps2_core | | 113/113 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core |
| +inst_rom_wb | | 1/77 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb |
| ++inst_rom | | 76/76 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom |
| +inst_sdram_ctrl_frontend_wb | | 100/629 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb |
| ++inst_cat_fifo | | 2/15 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 15/15 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl |
| ++inst_read_fifo | | 2/54 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo |
| +++inst_fifo_sync_ctrl | | 13/13 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl |
| ++inst_read_fifo | | 2/50 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl |
| +++inst_fifo_async_ctrl | | 17/48 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl |
| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
@@ -1644,14 +1645,14 @@ Section 14 - Utilization by Hierarchy
| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_sdram_ctrl | | 0/433 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl |
| +++inst_ddr_phy | | 179/180 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy |
| ++++inst_gray_counter_r | | 9/9 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_sdram_ctrl | | 0/410 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl |
| +++inst_ddr_phy | | 167/168 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy |
| ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 |
| +++inst_sd_cmd_fifo | | 4/64 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo |
| +++inst_sd_cmd_fifo | | 4/61 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo |
| ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 21/60 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl |
| ++++inst_fifo_async_ctrl | | 19/57 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
@@ -1667,12 +1668,12 @@ Section 14 - Utilization by Hierarchy
| +++++Mshreg_p2_3_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1 |
| +++++Mshreg_p2_3_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2 |
| +++++inst_gray_counter_r | | 14/14 | 13/13 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_sdram_cmd | | 46/46 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd |
| +++inst_sdram_ctrl | | 143/143 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl |
| ++inst_write_fifo | | 3/55 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo |
| +++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_sdram_cmd | | 47/47 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd |
| +++inst_sdram_ctrl | | 134/134 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl |
| ++inst_write_fifo | | 3/54 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 19/52 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl |
| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl |
| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
@@ -1687,29 +1688,29 @@ Section 14 - Utilization by Hierarchy
| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +inst_uart_wb_0 | | 59/105 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 |
| ++inst_uart_rx | | 0/29 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx |
| +inst_uart_wb_0 | | 61/109 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 |
| ++inst_uart_rx | | 0/30 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf |
| +++kcuart | | 21/21 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart |
| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx |
| +++kcuart | | 22/22 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart |
| ++inst_uart_tx | | 0/18 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf |
| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart |
| +inst_uart_wb_1 | | 56/103 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 |
| +++kcuart | | 10/10 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart |
| +inst_uart_wb_1 | | 60/107 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 |
| ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf |
| +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart |
| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf |
| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart |
| +inst_usb_port | | 37/37 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port |
| +inst_vga_frontend | | 802/1436 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend |
| +inst_usb_port | | 36/36 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port |
| +inst_vga_frontend | | 762/1384 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend |
| ++inst_blitfifo | | 4/31 | 0/23 | 4/45 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 27/27 | 23/23 | 41/41 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl |
| ++inst_bus_fifo | | 3/116 | 0/110 | 3/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo |
| ++inst_bus_fifo | | 4/115 | 0/110 | 4/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo |
| +++inst_dpram_1w1r | | 103/103 | 103/103 | 206/206 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 10/10 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl |
| ++inst_char_gen | | 194/206 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen |
| +++inst_fifo_sync_ctrl | | 8/8 | 7/7 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl |
| ++inst_char_gen | | 202/214 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen |
| +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 |
| +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 |
| +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 |
@@ -1724,9 +1725,9 @@ Section 14 - Utilization by Hierarchy
| +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 |
| +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram |
| +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom |
| ++inst_linefifo | | 2/178 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo |
| ++inst_linefifo | | 2/161 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 83/176 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl |
| +++inst_fifo_async_ctrl | | 72/159 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl |
| ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 |
| ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 |
| ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 |
@@ -1774,11 +1775,11 @@ Section 14 - Utilization by Hierarchy
| ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 |
| ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 |
| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 27/27 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_vga_backend | | 61/103 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend |
| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing |
| ++++inst_vga_sync_h | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h |
| ++++inst_vga_sync_v | | 22/22 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v |
| ++++inst_gray_counter_w | | 21/21 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_vga_backend | | 61/101 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend |
| +++inst_vga_timing | | 0/40 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing |
| ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h |
| ++++inst_vga_sync_v | | 19/19 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.