jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- reworked FIFOs

Browse Source 
- use synchronous resets

git-svn-id: http://moon:8086/svn/vhdl/trunk@1090 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 15:05:04 +00:00
parent bbd2673d42
commit deefbcffb3
5 changed files with 145 additions and 120 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/sim/tb_fifo_async.fdo
+1 -1
View File
@@ -3,7 +3,7 @@
vlib work vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../src/gray_counter.vhd" vcom -explicit -93 "../src/gray_counter.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
vcom -explicit -93 "../src/fifo_async_ctrl.vhd" vcom -explicit -93 "../src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../src/fifo_async.vhd" vcom -explicit -93 "../src/fifo_async.vhd"
vcom -explicit -93 "../src/tb_fifo_async.vhd" vcom -explicit -93 "../src/tb_fifo_async.vhd"
lib/FIFO/sim/tb_fifo_sync.fdo
+1 -1
View File
@@ -2,7 +2,7 @@
## ##
vlib work vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd" vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
vcom -explicit -93 "../src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../src/fifo_sync.vhd" vcom -explicit -93 "../src/fifo_sync.vhd"
vcom -explicit -93 "../src/tb_fifo_sync.vhd" vcom -explicit -93 "../src/tb_fifo_sync.vhd"
lib/FIFO/src/fifo_async_ctrl.vhd
+40 -15
View File
@@ -71,6 +71,7 @@ architecture Behavioral of fifo_async_ctrl is
signal pre_empty, pre_full : std_logic; signal pre_empty, pre_full : std_logic;
signal full, empty : std_logic; signal full, empty : std_logic;
signal rst_w, rst_r : std_logic;
-- synthesis translate_off -- synthesis translate_off
signal diffw : signed (addr_width downto 0); signal diffw : signed (addr_width downto 0);
@@ -86,24 +87,44 @@ begin
fifo_pre_full <= pre_full; fifo_pre_full <= pre_full;
fifo_pre_empty <= pre_empty; fifo_pre_empty <= pre_empty;
proc_write_inhibit: sync_reset_w:
process(rst, clk_w) process(clk_w)
begin begin
if rst = '1' then if rising_edge(clk_w) then
rst_w <= rst;
end if;
end process;
sync_reset_r:
process(clk_r)
begin
if rising_edge(clk_r) then
rst_r <= rst;
end if;
end process;
proc_write_inhibit:
process(clk_w)
begin
if rising_edge(clk_w) then
if rst_w = '1' then
full <= '0'; full <= '0';
elsif rising_edge(clk_w) then else
full <= pre_full; full <= pre_full;
end if; end if;
end if;
end process; end process;
proc_read_inhibit: proc_read_inhibit:
process(rst, clk_r) process(clk_r)
begin begin
if rst = '1' then if rising_edge(clk_r) then
if rst_r = '1' then
empty <= '1'; empty <= '1';
elsif rising_edge(clk_r) then else
empty <= pre_empty; empty <= pre_empty;
end if; end if;
end if;
end process; end process;
proc_sync_grptr: proc_sync_grptr:
@@ -171,16 +192,17 @@ proc_ptr_awptr:
end process; end process;
proc_status_almost_full: proc_status_almost_full:
process(rst, clk_w) process(clk_w)
variable diff : unsigned (addr_width downto 0); variable diff : unsigned (addr_width downto 0);
begin begin
-- synthesis translate_off -- synthesis translate_off
diffw <= signed(diff); diffw <= signed(diff);
-- synthesis translate_on -- synthesis translate_on
if rst = '1' then if rising_edge(clk_w) then
if rst_w = '1' then
fifo_afull <= '0'; fifo_afull <= '0';
diff := (others => '0'); diff := (others => '0');
elsif rising_edge(clk_w) then else
if diff >= almost_full_thresh-1 then if diff >= almost_full_thresh-1 then
fifo_afull <= '1'; fifo_afull <= '1';
else else
@@ -188,19 +210,21 @@ proc_status_almost_full:
end if; end if;
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar))); diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
end if; end if;
end if;
end process; end process;
proc_status_almost_empty: proc_status_almost_empty:
process(rst, clk_r) process(clk_r)
variable diff : unsigned (addr_width downto 0); variable diff : unsigned (addr_width downto 0);
begin begin
-- synthesis translate_off -- synthesis translate_off
diffr <= signed(diff); diffr <= signed(diff);
-- synthesis translate_on -- synthesis translate_on
if rst = '1' then if rising_edge(clk_r) then
if rst_r = '1' then
fifo_aempty <= '1'; fifo_aempty <= '1';
diff := (others => '0'); diff := (others => '0');
elsif rising_edge(clk_r) then else
if diff <= almost_empty_thresh+1 then if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1'; fifo_aempty <= '1';
else else
@@ -208,6 +232,7 @@ proc_status_almost_empty:
end if; end if;
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r))); diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
end if; end if;
end if;
end process; end process;
inst_gray_counter_w : entity work.gray_counter inst_gray_counter_w : entity work.gray_counter
@@ -218,7 +243,7 @@ inst_gray_counter_w : entity work.gray_counter
) )
port map port map
( (
rst => rst, rst => rst_w,
clk => clk_w, clk => clk_w,
ce => winc, ce => winc,
bcnt => bcnt_w, bcnt => bcnt_w,
@@ -235,7 +260,7 @@ inst_gray_counter_r : entity work.gray_counter
) )
port map port map
( (
rst => rst, rst => rst_r,
clk => clk_r, clk => clk_r,
ce => rinc, ce => rinc,
bcnt => bcnt_r, bcnt => bcnt_r,
lib/FIFO/src/fifo_sync_ctrl.vhd
+34 -30
View File
@@ -68,65 +68,75 @@ begin
proc_diff_gen: proc_diff_gen:
process(rst, clk) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
diff <= (others => '0'); diff <= (others => '0');
elsif rising_edge(clk) then else
if winc = '1' and rinc = '0' then if winc = '1' and rinc = '0' then
diff <= diff + 1; diff <= diff + 1;
elsif winc = '0' and rinc = '1' then elsif winc = '0' and rinc = '1' then
diff <= diff - 1; diff <= diff - 1;
end if; end if;
end if; end if;
end if;
end process; end process;
proc_status_almost_full: proc_status_almost_full:
process(rst, clk) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
fifo_afull <= '0'; fifo_afull <= '0';
elsif rising_edge(clk) then else
if diff >= almost_full_thresh-1 then if diff >= almost_full_thresh-1 then
fifo_afull <= '1'; fifo_afull <= '1';
else else
fifo_afull <= '0'; fifo_afull <= '0';
end if; end if;
end if; end if;
end if;
end process; end process;
proc_status_almost_empty: proc_status_almost_empty:
process(rst, clk) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
fifo_aempty <= '1'; fifo_aempty <= '1';
elsif rising_edge(clk) then else
if diff <= almost_empty_thresh+1 then if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1'; fifo_aempty <= '1';
else else
fifo_aempty <= '0'; fifo_aempty <= '0';
end if; end if;
end if; end if;
end if;
end process; end process;
proc_full_reg: proc_full_reg:
process(rst, clk) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
full <= '0'; full <= '0';
elsif rising_edge(clk) then else
full <= pre_full; full <= pre_full;
end if; end if;
end if;
end process; end process;
proc_empty_reg: proc_empty_reg:
process(rst, clk) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
empty <= '1'; empty <= '1';
elsif rising_edge(clk) then else
empty <= pre_empty; empty <= pre_empty;
end if; end if;
end if;
end process; end process;
proc_status_w: proc_status_w:
@@ -147,10 +157,10 @@ proc_status_w:
proc_flag_write: proc_flag_write:
process(rst, clk) process(rst, clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
was_write <= '0'; was_write <= '0';
elsif rising_edge(clk) then elsif winc = '1' then
if winc = '1' then
was_write <= '1'; was_write <= '1';
elsif rinc = '1' then elsif rinc = '1' then
was_write <= '0'; was_write <= '0';
@@ -158,40 +168,34 @@ proc_flag_write:
end if; end if;
end process; end process;
pW_next <= (pW + 1) when winc = '1' else pW;
ptr_w <= pW;
proc_ptr_w: proc_ptr_w:
process(rst, clk, pW, winc) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
pW <= to_unsigned(0, addr_width); pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width); else
elsif rising_edge(clk) then
if winc = '1' then
pW <= pW_next; pW <= pW_next;
end if; end if;
end if; end if;
pW_next <= pW;
if winc = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process; end process;
pR_next <= (pR + 1) when rinc = '1' else pR;
ptr_r <= pR_next;
proc_ptr_r: proc_ptr_r:
process(rst, clk, pR_next, pR, rinc) process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
pR <= to_unsigned(0, addr_width); pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width); else
elsif rising_edge(clk) then
if rinc = '1' then
pR <= pR_next; pR <= pR_next;
end if; end if;
end if; end if;
pR_next <= pR;
if rinc = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;
end process; end process;
end Behavioral; end Behavioral;
lib/FIFO/src/gray_counter.vhd
+5 -9
View File
@@ -60,23 +60,19 @@ begin
bcnt <= cntb; bcnt <= cntb;
gcnt <= cntg; gcnt <= cntg;
process(rst, clk, ce, cntb, nxtb) nxtg <= bin2gray(nxtb);
nxtb <= (cntb + 1) when ce = '1' else cntb;
process(clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
cntb <= to_unsigned(init_value, width); cntb <= to_unsigned(init_value, width);
nxtb <= to_unsigned(init_value, width);
nxtg <= to_unsigned(init_value, width);
cntg <= to_unsigned(init_value, width); cntg <= to_unsigned(init_value, width);
else else
if rising_edge(clk) then
cntg <= nxtg; cntg <= nxtg;
cntb <= nxtb; cntb <= nxtb;
end if; end if;
nxtg <= bin2gray(nxtb);
nxtb <= cntb;
if ce = '1' then
nxtb <= cntb + 1;
end if;
end if; end if;
end process; end process;